Page MenuHomePhabricator

[RISCV] Split zvlsseg searchable table into 4 separate tables. Index by properties rather than intrinsic ID.

Authored by craig.topper on Feb 17 2021, 1:16 PM.



Intrinsic ID is a 32-bit value which made each row of the table 4
byte aligned. The remaining fields used 5 bytes. This meant 3 bytes
of padding per row.

This patch breaks the table into 4 separate tables and indexes them
by properties we know about the intrinsic. NF, masked,
strided, ordered, etc. The indexed load/store tables have no
padding in their rows now.

All together this reduces the size of llc binary by ~28K.

I'm considering adding similar tables for isel of non-segment
load/store as well to cut down the size of the isel table and
probably improve our isel performance. Those tables would need to
indexed from intrinsics, IR loads/stores, gathers/scatters, and
RISCVISD opcodes. So having a table that can be indexed without using
intrinsic ID is more flexible.

Diff Detail

Event Timeline

craig.topper created this revision.Feb 17 2021, 1:16 PM
craig.topper requested review of this revision.Feb 17 2021, 1:16 PM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 17 2021, 1:16 PM
Herald added a subscriber: MaskRay. · View Herald Transcript
HsiangKai added inline comments.Feb 17 2021, 11:28 PM








Address review comments

craig.topper marked 4 inline comments as done.Feb 18 2021, 10:44 AM
This revision is now accepted and ready to land.Feb 18 2021, 5:43 PM

-Move all the tables into RISCV namespace instead of separate namespaces. Give
each a separate get*Pseudo function.
-Import all tables with one include of
-Move the declarations of the structs to RISCVISelDAGToDAG.h to limit the number
of lines devoted to the tables in the cpp file.

HsiangKai accepted this revision.Feb 18 2021, 6:41 PM
This revision was landed with ongoing or failed builds.Feb 18 2021, 7:08 PM
This revision was automatically updated to reflect the committed changes.