[FPEnv][ARM] Implement lowering of llvm.set.rounding

[simon_tatham]

The table-lookup strategy seems like overkill to me. As far as I can see, the integer mapping required is: 0→3, 3→2. 2→1, 1→0. In other words, all four input values (that can be handled at all) are just reduced by 1, mod 4. So instead of (147 >> (value << 1)) & 3, you could compute (value - 1) & 3, surely more cheaply.

What about RoundingMode::NearestTiesToAway? There's no support for that in the FPSCR dynamic rounding-mode field, but it looks as if this patch will lower @llvm.set.rounding(i32 4) to some kind of code that silently does the wrong thing.

Perhaps that should have been error-checked by whatever generated the @llvm.set.rounding call in the first place? If so, I think at least a mention in the comments would be useful.

llvm/lib/Target/ARM/ARMISelLowering.cpp

6131

Corresponding Arm mode, surely!

[sepavloff]

Optimized FPSCR bits calculation

[sepavloff]

In D96501#2557041, @simon_tatham wrote:

The table-lookup strategy seems like overkill to me. As far as I can see, the integer mapping required is: 0→3, 3→2. 2→1, 1→0. In other words, all four input values (that can be handled at all) are just reduced by 1, mod 4. So instead of (147 >> (value << 1)) & 3, you could compute (value - 1) & 3, surely more cheaply.

Indeed, it provides more compact code, thank you.

What about RoundingMode::NearestTiesToAway? There's no support for that in the FPSCR dynamic rounding-mode field, but it looks as if this patch will lower @llvm.set.rounding(i32 4) to some kind of code that silently does the wrong thing.

Perhaps that should have been error-checked by whatever generated the @llvm.set.rounding call in the first place? If so, I think at least a mention in the comments would be useful.

Yes, this intrinsic is a low level entity so it is expected that some code elsewhere makes the necessary checks. Appropriate comment is added.

llvm/lib/Target/ARM/ARMISelLowering.cpp

6131

Sure) Copy-past error.

[simon_tatham]

LGTM. Thanks!

[craig.topper]

llvm/lib/Target/ARM/ARMISelLowering.cpp

6148

Intrinsic IDs should use getTargetConstant I think, but it looks like ARM is already inconsistent on this. Not sure about other targets.

[sepavloff]

llvm/lib/Target/ARM/ARMISelLowering.cpp

6148

AArch64 is inconsistent as well.

llvm/lib/Target/ARM/ARMISelLowering.h

enum NodeType : unsigned {
 
       // Load/Store of dual registers
       LDRD,
       STRD
     };
 
   } // end namespace ARMISD
 
+  namespace ARM {
+  /// Possible values of current rounding mode, which is specified in bits
+  /// 23:22 of FPSCR.
+  enum Rounding {
+    RN = 0,    // Round to Nearest
+    RP = 1,    // Round towards Plus infinity
+    RM = 2,    // Round towards Minus infinity
+    RZ = 3,    // Round towards Zero
+    rmMask = 3 // Bit mask selecting rounding mode
+  };
+
+  // Bit position of rounding mode bits in FPSCR.
+  const unsigned RoundingBitsPos = 22;
+  } // namespace ARM
+
   /// Define some predicates that are used for node matching.
   namespace ARM {
 
     bool isBitFieldInvertedMask(unsigned v);
 
   } // end namespace ARM
 
   //===--------------------------------------------------------------------===//
private:
     SDValue LowerBRCOND(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerFCOPYSIGN(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerFRAMEADDR(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerShiftRightParts(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerShiftLeftParts(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerFLT_ROUNDS_(SDValue Op, SelectionDAG &DAG) const;
+    SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerConstantFP(SDValue Op, SelectionDAG &DAG,
                             const ARMSubtarget *ST) const;
     SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
                               const ARMSubtarget *ST) const;
     SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerFSINCOS(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerDivRem(SDValue Op, SelectionDAG &DAG) const;
     SDValue LowerDIV_Windows(SDValue Op, SelectionDAG &DAG, bool Signed) const;

llvm/lib/Target/ARM/ARMISelLowering.cpp

 //===- ARMISelLowering.cpp - ARM DAG Lowering Implementation --------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines the interfaces that ARM uses to lower LLVM code into a
ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM,
   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
 
   if (!Subtarget->useSoftFloat() && Subtarget->hasFPRegs() &&
       !Subtarget->isThumb1Only()) {
     // Turn f64->i64 into VMOVRRD, i64 -> f64 to VMOVDRR
     // iff target supports vfp2.
     setOperationAction(ISD::BITCAST, MVT::i64, Custom);
     setOperationAction(ISD::FLT_ROUNDS_, MVT::i32, Custom);
+    setOperationAction(ISD::SET_ROUNDING, MVT::Other, Custom);
   }
 
   // We want to custom lower some of our intrinsics.
   setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
   setOperationAction(ISD::EH_SJLJ_SETJMP, MVT::i32, Custom);
   setOperationAction(ISD::EH_SJLJ_LONGJMP, MVT::Other, Custom);
   setOperationAction(ISD::EH_SJLJ_SETUP_DISPATCH, MVT::Other, Custom);
   if (Subtarget->useSjLjEH())
SDValue FltRounds = DAG.getNode(ISD::ADD, dl, MVT::i32, FPSCR,
                                   DAG.getConstant(1U << 22, dl, MVT::i32));
   SDValue RMODE = DAG.getNode(ISD::SRL, dl, MVT::i32, FltRounds,
                               DAG.getConstant(22, dl, MVT::i32));
   SDValue And = DAG.getNode(ISD::AND, dl, MVT::i32, RMODE,
                             DAG.getConstant(3, dl, MVT::i32));
   return DAG.getMergeValues({And, Chain}, dl);
 }
 
+SDValue ARMTargetLowering::LowerSET_ROUNDING(SDValue Op,
+                                             SelectionDAG &DAG) const {
+  SDLoc DL(Op);
+  SDValue Chain = Op->getOperand(0);
+  SDValue RMValue = Op->getOperand(1);
+
+  // Encoding used for rounding mode in FPSCR differs from that used in
+  // FLT_ROUNDS. To convert it the C rounding mode is used as an index in
+  // a table, which consists of a sequence of 2-bit fields, each representing
+  // corresponding RISCV mode.
+  static const unsigned Table =
+      (ARM::Rounding::RN << 2 * int(RoundingMode::NearestTiesToEven)) |
+      (ARM::Rounding::RZ << 2 * int(RoundingMode::TowardZero)) |
+      (ARM::Rounding::RM << 2 * int(RoundingMode::TowardNegative)) |
+      (ARM::Rounding::RP << 2 * int(RoundingMode::TowardPositive));
+
+  // Calculate new value of FPSCR[23:22].
+  SDValue Shift = DAG.getNode(ISD::SHL, DL, MVT::i32, RMValue,
+                              DAG.getConstant(1, DL, MVT::i32));
+  SDValue Shifted = DAG.getNode(ISD::SRL, DL, MVT::i32,
+                                DAG.getConstant(Table, DL, MVT::i32), Shift);
+  RMValue = DAG.getNode(ISD::AND, DL, MVT::i32, Shifted,
+                        DAG.getConstant(0x3, DL, MVT::i32));
+  RMValue = DAG.getNode(ISD::SHL, DL, MVT::i32, RMValue,
+                        DAG.getConstant(ARM::RoundingBitsPos, DL, MVT::i32));
+
+  // Get current value of FPSCR.
+  SDValue Ops[] = {Chain,
+                   DAG.getConstant(Intrinsic::arm_get_fpscr, DL, MVT::i32)};
+  SDValue FPSCR =
+      DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL, {MVT::i32, MVT::Other}, Ops);
+  Chain = FPSCR.getValue(1);
+  FPSCR = FPSCR.getValue(0);
+
+  // Put new rounding mode into FPSCR[23:22].
+  const unsigned RMMask = ~(ARM::Rounding::rmMask << ARM::RoundingBitsPos);
+  FPSCR = DAG.getNode(ISD::AND, DL, MVT::i32, FPSCR,
+                      DAG.getConstant(RMMask, DL, MVT::i32));
+  FPSCR = DAG.getNode(ISD::OR, DL, MVT::i32, FPSCR, RMValue);
+  SDValue Ops2[] = {
+      Chain, DAG.getConstant(Intrinsic::arm_set_fpscr, DL, MVT::i32), FPSCR};
+  return DAG.getNode(ISD::INTRINSIC_VOID, DL, MVT::Other, Ops2);
+}
+
 static SDValue LowerCTTZ(SDNode *N, SelectionDAG &DAG,
                          const ARMSubtarget *ST) {
   SDLoc dl(N);
   EVT VT = N->getValueType(0);
   if (VT.isVector() && ST->hasNEON()) {
 
     // Compute the least significant set bit: LSB = X & -X
     SDValue X = N->getOperand(0);
SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
   case ISD::BUILD_VECTOR:  return LowerBUILD_VECTOR(Op, DAG, Subtarget);
   case ISD::VECTOR_SHUFFLE: return LowerVECTOR_SHUFFLE(Op, DAG, Subtarget);
   case ISD::EXTRACT_SUBVECTOR: return LowerEXTRACT_SUBVECTOR(Op, DAG, Subtarget);
   case ISD::INSERT_VECTOR_ELT: return LowerINSERT_VECTOR_ELT(Op, DAG);
   case ISD::EXTRACT_VECTOR_ELT: return LowerEXTRACT_VECTOR_ELT(Op, DAG, Subtarget);
   case ISD::CONCAT_VECTORS: return LowerCONCAT_VECTORS(Op, DAG, Subtarget);
   case ISD::TRUNCATE:      return LowerTruncatei1(Op, DAG, Subtarget);
   case ISD::FLT_ROUNDS_:   return LowerFLT_ROUNDS_(Op, DAG);
+  case ISD::SET_ROUNDING:  return LowerSET_ROUNDING(Op, DAG);
   case ISD::MUL:           return LowerMUL(Op, DAG);
   case ISD::SDIV:
     if (Subtarget->isTargetWindows() && !Op.getValueType().isVector())
       return LowerDIV_Windows(Op, DAG, /* Signed */ true);
     return LowerSDIV(Op, DAG, Subtarget);
   case ISD::UDIV:
     if (Subtarget->isTargetWindows() && !Op.getValueType().isVector())
       return LowerDIV_Windows(Op, DAG, /* Signed */ false);

llvm/test/CodeGen/ARM/fpenv.ll

+; RUN: llc -mtriple=arm-eabi -float-abi=soft -mattr=+vfp2 %s -o - | FileCheck %s
+
+define void @func_02(i32 %rm) {
+  call void @llvm.set.rounding(i32 %rm)
+  ret void
+}
+
+; CHECK-LABEL: func_02:
+; CHECK:       vmrs  r1, fpscr
+; CHECK:       lsl   r0, r0, #1
+; CHECK:       mov   r2, #147
+; CHECK:       mov   r3, #3
+; CHECK:       and   r0, r3, r2, lsr r0
+; CHECK:       bic   r1, r1, #12582912
+; CHECK:       orr   r0, r1, r0, lsl #22
+; CHECK:       vmsr  fpscr, r0
+; CHECK:       mov   pc, lr
+
+
+define void @func_03() {
+  call void @llvm.set.rounding(i32 0)
+  ret void
+}
+
+; CHECK-LABEL: func_03
+; CHECK:       vmrs  r0, fpscr
+; CHECK:       orr   r0, r0, #12582912
+; CHECK:       vmsr  fpscr, r0
+; CHECK:       mov   pc, lr
+
+
+define void @func_04() {
+  call void @llvm.set.rounding(i32 1)
+  ret void
+}
+
+; CHECK-LABEL: func_04
+; CHECK:       vmrs    r0, fpscr
+; CHECK:       bic     r0, r0, #12582912
+; CHECK:       vmsr    fpscr, r0
+; CHECK:       mov     pc, lr
+
+
+define void @func_05() {
+  call void @llvm.set.rounding(i32 2)
+  ret void
+}
+
+
+; CHECK-LABEL: func_05
+; CHECK:       vmrs    r0, fpscr
+; CHECK:       bic     r0, r0, #12582912
+; CHECK:       orr     r0, r0, #4194304
+; CHECK:       vmsr    fpscr, r0
+; CHECK:       mov     pc, lr
+
+
+define void @func_06() {
+  call void @llvm.set.rounding(i32 3)
+  ret void
+}
+
+; CHECK-LABEL: func_06
+; CHECK:       vmrs   r0, fpscr
+; CHECK:       bic    r0, r0, #12582912
+; CHECK:       orr    r0, r0, #8388608
+; CHECK:       vmsr   fpscr, r0
+; CHECK:       mov    pc, lr
+
+
+declare void @llvm.set.rounding(i32)