[AMDGPU] Add f16 to i1 CodeGen patterns.

[whchung]

Summary

Follow patterns used for f32 and f64 types.

[whchung]

The patterns were found in some MLIR-based applications.

[rampitec]

LGTM

[arsenm]

Should also test globalisel

[whchung]

@arsenm Could you help me understand if my understanding is correct to fulfill your requirement of 'test globalisel'?

• change the followings under llvm/test/CodeGen/AMDGPU/GlobalISel:
  • inst-select-fptosi.mir
  • legalize-fptosi.mir
  • inst-select-fptoui.mir
  • legalize-fptoui.mir
• populate FileCheck macros with update_mir_test_checks.py

[whchung]

Add MIR-level tests.

[arsenm]

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir

117–122

This isn't testing a target with f16 instructions

[whchung]

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir

117–122

@arsenm Could you help review if https://reviews.llvm.org/D96061 addresses your concerns? Thanks.

[arsenm]

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir

123–126

Hmm. It looks like these patterns aren't working. The MIR register banks are also not what I would expect. I think this needs some up-front work in the legalizer/regbankselect to handle properly, and would need end to end IR tests

[whchung]

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir

123–126

@arsenm I'll take a look into AMDGPULegalizerInfo and AMDGPURegisterBankInfo. I'm not that well-versed in these aspect so I may come up with questions initially.

For end-to-end IR tests, do you feel any additions to fptosi.f16.ll and fptoui.f16.ll in this patch needed?

[arsenm]

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir

123–126

Some cases that use the i1 result in a boolean context (e.g. branch or select condition) would be helpful

llvm/lib/Target/AMDGPU/SIInstructions.td

(V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
                        /*src1mod*/(i32 0), /*src1*/(i32 -1), $src), sub1)
 >;
 
 class FPToI1Pat<Instruction Inst, int KOne, ValueType kone_type, ValueType vt, SDPatternOperator fp_to_int> : GCNPat <
   (i1 (fp_to_int (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)))),
   (i1 (Inst 0, (kone_type KOne), $src0_modifiers, $src0, DSTCLAMP.NONE))
 >;
 
+def : FPToI1Pat<V_CMP_EQ_F16_e64, CONST.FP16_ONE, i16, f16, fp_to_uint>;
+def : FPToI1Pat<V_CMP_EQ_F16_e64, CONST.FP16_NEG_ONE, i16, f16, fp_to_sint>;
 def : FPToI1Pat<V_CMP_EQ_F32_e64, CONST.FP32_ONE, i32, f32, fp_to_uint>;
 def : FPToI1Pat<V_CMP_EQ_F32_e64, CONST.FP32_NEG_ONE, i32, f32, fp_to_sint>;
 def : FPToI1Pat<V_CMP_EQ_F64_e64, CONST.FP64_ONE, i64, f64, fp_to_uint>;
 def : FPToI1Pat<V_CMP_EQ_F64_e64, CONST.FP64_NEG_ONE, i64, f64, fp_to_sint>;
 
 // If we need to perform a logical operation on i1 values, we need to
 // use vector comparisons since there is only one SCC register. Vector
 // comparisons may write to a pair of SGPRs or a single SGPR, so treat

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptosi.mir

bb.0:
     ; GCN: %3:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %4, implicit $mode, implicit $exec
     ; GCN: $vgpr0 = COPY %3
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s16) = G_TRUNC %0
     %2:vgpr(s16) = G_FNEG %1
     %3:vgpr(s32) = G_FPTOSI %2
     $vgpr0 = COPY %3
 ...
+
+---
+name: fptosi_s16_to_s1_vv
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; GCN-LABEL: name: fptosi_s16_to_s1_vv
+    ; GCN: liveins: $vgpr0
+    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GCN: %4:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec
+    ; GCN: %2:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %4, implicit $mode, implicit $exec
+    ; GCN: S_ENDPGM 0, implicit %2
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s16) = G_TRUNC %0
+    %2:vgpr(s32) = G_FPTOSI %1
+    %3:vgpr(s1)  = G_TRUNC %2
+    S_ENDPGM 0, implicit %3
+...
+
+---
+name: fptosi_s16_to_s1_vs
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+
+    ; GCN-LABEL: name: fptosi_s16_to_s1_vs
+    ; GCN: liveins: $sgpr0
+    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; GCN: %4:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec
+    ; GCN: %2:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %4, implicit $mode, implicit $exec
+    ; GCN: S_ENDPGM 0, implicit %2
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s16) = G_TRUNC %0
+    %2:vgpr(s32) = G_FPTOSI %1
+    %3:vgpr(s1)  = G_TRUNC %2
+    S_ENDPGM 0, implicit %3
+...
+
+---
+name: fptosi_s16_to_s1_fneg_vv
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; GCN-LABEL: name: fptosi_s16_to_s1_fneg_vv
+    ; GCN: liveins: $vgpr0
+    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
+    ; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
+    ; GCN: %5:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[V_XOR_B32_e32_]], implicit $mode, implicit $exec
+    ; GCN: %3:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %5, implicit $mode, implicit $exec
+    ; GCN: S_ENDPGM 0, implicit %3
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s16) = G_TRUNC %0
+    %2:vgpr(s16) = G_FNEG %1
+    %3:vgpr(s32) = G_FPTOSI %2
+    %4:vgpr(s1)  = G_TRUNC %3
+    S_ENDPGM 0, implicit %4
+...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir

bb.0:
     ; GCN: %3:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 %4, implicit $mode, implicit $exec
     ; GCN: $vgpr0 = COPY %3
     %0:vgpr(s32) = COPY $vgpr0
     %1:vgpr(s16) = G_TRUNC %0
     %2:vgpr(s16) = G_FNEG %1
     %3:vgpr(s32) = G_FPTOUI %2
     $vgpr0 = COPY %3
 ...
+
+---
+name: fptoui_s16_to_s1_vv
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; GCN-LABEL: name: fptoui_s16_to_s1_vv
+    ; GCN: liveins: $vgpr0
+    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GCN: %4:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec
+    ; GCN: %2:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 %4, implicit $mode, implicit $exec
+    ; GCN: S_ENDPGM 0, implicit %2
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s16) = G_TRUNC %0
+    %2:vgpr(s32) = G_FPTOUI %1
+    %3:vgpr(s1)  = G_TRUNC %2
+    S_ENDPGM 0, implicit %3
+...
+
+---
+name: fptoui_s16_to_s1_vs
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $sgpr0
+
+    ; GCN-LABEL: name: fptoui_s16_to_s1_vs
+    ; GCN: liveins: $sgpr0
+    ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
+    ; GCN: %4:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec
+    ; GCN: %2:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 %4, implicit $mode, implicit $exec
+    ; GCN: S_ENDPGM 0, implicit %2
+    %0:sgpr(s32) = COPY $sgpr0
+    %1:sgpr(s16) = G_TRUNC %0
+    %2:vgpr(s32) = G_FPTOUI %1
+    %3:vgpr(s1)  = G_TRUNC %2
+    S_ENDPGM 0, implicit %3
+...
+
+---
+name: fptoui_s16_to_s1_fneg_vv
+legalized: true
+regBankSelected: true
+tracksRegLiveness: true
+
+body: |
+  bb.0:
+    liveins: $vgpr0
+
+    ; GCN-LABEL: name: fptoui_s16_to_s1_fneg_vv
+    ; GCN: liveins: $vgpr0
+    ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
+    ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
+    ; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
+    ; GCN: %5:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[V_XOR_B32_e32_]], implicit $mode, implicit $exec
+    ; GCN: %3:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 %5, implicit $mode, implicit $exec
+    ; GCN: S_ENDPGM 0, implicit %3
+    %0:vgpr(s32) = COPY $vgpr0
+    %1:vgpr(s16) = G_TRUNC %0
+    %2:vgpr(s16) = G_FNEG %1
+    %3:vgpr(s32) = G_FPTOUI %2
+    %4:vgpr(s1)  = G_TRUNC %3
+    S_ENDPGM 0, implicit %4
+...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptosi.mir

bb.0:
     ; VI: [[FPTOSI1:%[0-9]+]]:_(s32) = G_FPTOSI [[TRUNC1]](s16)
     ; VI: [[SEXT1:%[0-9]+]]:_(s64) = G_SEXT [[FPTOSI1]](s32)
     ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[SEXT]](s64), [[SEXT1]](s64)
     ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
     %0:_(<2 x s16>) = COPY $vgpr0
     %1:_(<2 x s64>) = G_FPTOSI %0
     $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
 ...
+
+---
+name: test_fptosi_s16_to_s1
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; SI-LABEL: name: test_fptosi_s16_to_s1
+    ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+    ; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
+    ; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](s32)
+    ; SI: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[FPTOSI]](s32)
+    ; SI: S_ENDPGM 0, implicit [[TRUNC1]](s1)
+    ; VI-LABEL: name: test_fptosi_s16_to_s1
+    ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+    ; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[TRUNC]](s16)
+    ; VI: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[FPTOSI]](s32)
+    ; VI: S_ENDPGM 0, implicit [[TRUNC1]](s1)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s16) = G_TRUNC %0
+    %2:_(s1)  = G_FPTOSI %1
+    S_ENDPGM 0, implicit %2
+...

llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-fptoui.mir

bb.0:
     ; VI: [[FPTOUI1:%[0-9]+]]:_(s32) = G_FPTOUI [[TRUNC1]](s16)
     ; VI: [[ZEXT1:%[0-9]+]]:_(s64) = G_ZEXT [[FPTOUI1]](s32)
     ; VI: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[ZEXT]](s64), [[ZEXT1]](s64)
     ; VI: $vgpr0_vgpr1_vgpr2_vgpr3 = COPY [[BUILD_VECTOR]](<2 x s64>)
     %0:_(<2 x s16>) = COPY $vgpr0
     %1:_(<2 x s64>) = G_FPTOUI %0
     $vgpr0_vgpr1_vgpr2_vgpr3 = COPY %1
 ...
+
+---
+name: test_fptoui_s16_to_s1
+body: |
+  bb.0:
+    liveins: $vgpr0
+    ; SI-LABEL: name: test_fptoui_s16_to_s1
+    ; SI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; SI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+    ; SI: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[TRUNC]](s16)
+    ; SI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[FPEXT]](s32)
+    ; SI: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[FPTOSI]](s32)
+    ; SI: S_ENDPGM 0, implicit [[TRUNC1]](s1)
+    ; VI-LABEL: name: test_fptoui_s16_to_s1
+    ; VI: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
+    ; VI: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32)
+    ; VI: [[FPTOSI:%[0-9]+]]:_(s32) = G_FPTOSI [[TRUNC]](s16)
+    ; VI: [[TRUNC1:%[0-9]+]]:_(s1) = G_TRUNC [[FPTOSI]](s32)
+    ; VI: S_ENDPGM 0, implicit [[TRUNC1]](s1)
+    %0:_(s32) = COPY $vgpr0
+    %1:_(s16) = G_TRUNC %0
+    %2:_(s1)  = G_FPTOSI %1
+    S_ENDPGM 0, implicit %2
+...

llvm/test/CodeGen/AMDGPU/fptosi.f16.ll

define amdgpu_kernel void @fptosi_v2f16_to_v2i64(
     <2 x i64> addrspace(1)* %r,
     <2 x half> addrspace(1)* %a) {
 entry:
   %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
   %r.val = fptosi <2 x half> %a.val to <2 x i64>
   store <2 x i64> %r.val, <2 x i64> addrspace(1)* %r
   ret void
 }
+
+; GCN-LABEL: {{^}}fptosi_f16_to_i1:
+; SI: v_cvt_f32_f16_e32 v{{[0-9+]}}, s{{[0-9]+}}
+; SI: v_cmp_eq_f32_e32 vcc, -1.0, v{{[0-9]+}}
+; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc
+; VI: v_cmp_eq_f16_e64 s{{\[[0-9]+:[0-9]+\]}}, 0xbc00, s{{[0-9]+}}
+; VI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, s[0:1]
+define amdgpu_kernel void @fptosi_f16_to_i1(i1 addrspace(1)* %out, half %in) {
+entry:
+  %conv = fptosi half %in to i1
+  store i1 %conv, i1 addrspace(1)* %out
+  ret void
+}

llvm/test/CodeGen/AMDGPU/fptoui.f16.ll

define amdgpu_kernel void @fptoui_v2f16_to_v2i64(
     <2 x i64> addrspace(1)* %r,
     <2 x half> addrspace(1)* %a) {
 entry:
   %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
   %r.val = fptoui <2 x half> %a.val to <2 x i64>
   store <2 x i64> %r.val, <2 x i64> addrspace(1)* %r
   ret void
 }
+
+; GCN-LABEL: {{^}}fptoui_f16_to_i1:
+; SI: v_cvt_f32_f16_e32 v{{[0-9+]}}, s{{[0-9]+}}
+; SI: v_cmp_eq_f32_e32 vcc, 1.0, v{{[0-9]+}}
+; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc
+; VI: v_cmp_eq_f16_e64 s{{\[[0-9]+:[0-9]+\]}}, 1.0, s{{[0-9]+}}
+; VI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, s[0:1]
+define amdgpu_kernel void @fptoui_f16_to_i1(i1 addrspace(1)* %out, half %in) {
+entry:
+  %conv = fptoui half %in to i1
+  store i1 %conv, i1 addrspace(1)* %out
+  ret void
+}