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Differential D96061

[AMDGPU] Add Fiji target in fptosi/fptoui instruction-select MIR tests.
ClosedPublic

Authored by whchung on Feb 4 2021, 10:18 AM.

Details

Reviewers
arsenm
Commits
rG04766c401ba5: [AMDGPU] Add Fiji target in fptosi/fptoui instruction-select MIR tests.
Summary

In response to review comments in D95964, add a target with f16 instructions.

Diff Detail

Event Timeline

whchung created this revision.Feb 4 2021, 10:18 AM
Herald added subscribers: kerbowa, t-tye, tpr and 5 others. · View Herald TranscriptFeb 4 2021, 10:18 AM
whchung requested review of this revision.Feb 4 2021, 10:18 AM
Herald added a project: Restricted Project. · View Herald TranscriptFeb 4 2021, 10:18 AM
Herald added subscribers: llvm-commits, wdng. · View Herald Transcript
whchung mentioned this in D95964: [AMDGPU] Add f16 to i1 CodeGen patterns..Feb 4 2021, 10:19 AM
Harbormaster completed remote builds in B87954: Diff 321508.Feb 4 2021, 1:49 PM
arsenm accepted this revision.Feb 4 2021, 6:05 PM
This revision is now accepted and ready to land.Feb 4 2021, 6:05 PM
This revision was landed with ongoing or failed builds.Feb 5 2021, 9:34 AM
Closed by commit rG04766c401ba5: [AMDGPU] Add Fiji target in fptosi/fptoui instruction-select MIR tests. (authored by whchung). · Explain Why
This revision was automatically updated to reflect the committed changes.
whchung added a commit: rG04766c401ba5: [AMDGPU] Add Fiji target in fptosi/fptoui instruction-select MIR tests..

Revision Contents

PathSize
llvm/
test/
CodeGen/
AMDGPU/
GlobalISel/
56 lines
49 lines

Diff 321803

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptosi.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefix=GCN # RUN: llc -march=amdgcn -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefix=GCN
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefix=VI
--- ---
name: fptosi_s32_to_s32_vv name: fptosi_s32_to_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GCN-LABEL: name: fptosi_s32_to_s32_vv ; GCN-LABEL: name: fptosi_s32_to_s32_vv
; GCN: liveins: $vgpr0 ; GCN: liveins: $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: %1:vgpr_32 = nofpexcept V_CVT_I32_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %1:vgpr_32 = nofpexcept V_CVT_I32_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: $vgpr0 = COPY %1 ; GCN: $vgpr0 = COPY %1
; VI-LABEL: name: fptosi_s32_to_s32_vv
; VI: liveins: $vgpr0
; VI: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; VI: %1:vgpr_32 = nofpexcept V_CVT_I32_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; VI: $vgpr0 = COPY %1
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_FPTOSI %0 %1:vgpr(s32) = G_FPTOSI %0
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...
--- ---
name: fptosi_s32_to_s32_vs name: fptosi_s32_to_s32_vs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; GCN-LABEL: name: fptosi_s32_to_s32_vs ; GCN-LABEL: name: fptosi_s32_to_s32_vs
; GCN: liveins: $sgpr0 ; GCN: liveins: $sgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: %1:vgpr_32 = nofpexcept V_CVT_I32_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %1:vgpr_32 = nofpexcept V_CVT_I32_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: $vgpr0 = COPY %1 ; GCN: $vgpr0 = COPY %1
; VI-LABEL: name: fptosi_s32_to_s32_vs
; VI: liveins: $sgpr0
; VI: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; VI: %1:vgpr_32 = nofpexcept V_CVT_I32_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; VI: $vgpr0 = COPY %1
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = G_FPTOSI %0 %1:vgpr(s32) = G_FPTOSI %0
$vgpr0 = COPY %1 $vgpr0 = COPY %1
... ...
--- ---
name: fptosi_s32_to_s32_fneg_vv name: fptosi_s32_to_s32_fneg_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GCN-LABEL: name: fptosi_s32_to_s32_fneg_vv ; GCN-LABEL: name: fptosi_s32_to_s32_fneg_vv
; GCN: liveins: $vgpr0 ; GCN: liveins: $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: %2:vgpr_32 = nofpexcept V_CVT_I32_F32_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %2:vgpr_32 = nofpexcept V_CVT_I32_F32_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: $vgpr0 = COPY %2 ; GCN: $vgpr0 = COPY %2
; VI-LABEL: name: fptosi_s32_to_s32_fneg_vv
; VI: liveins: $vgpr0
; VI: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; VI: %2:vgpr_32 = nofpexcept V_CVT_I32_F32_e64 1, [[COPY]], 0, 0, implicit $mode, implicit $exec
; VI: $vgpr0 = COPY %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s32) = G_FNEG %0 %1:vgpr(s32) = G_FNEG %0
%2:vgpr(s32) = G_FPTOSI %1 %2:vgpr(s32) = G_FPTOSI %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: fptosi_s16_to_s32_vv name: fptosi_s16_to_s32_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GCN-LABEL: name: fptosi_s16_to_s32_vv ; GCN-LABEL: name: fptosi_s16_to_s32_vv
; GCN: liveins: $vgpr0 ; GCN: liveins: $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: %3:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec ; GCN: %3:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GCN: %2:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %3, implicit $mode, implicit $exec ; GCN: %2:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %3, implicit $mode, implicit $exec
; GCN: $vgpr0 = COPY %2 ; GCN: $vgpr0 = COPY %2
; VI-LABEL: name: fptosi_s16_to_s32_vv
; VI: liveins: $vgpr0
; VI: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; VI: %3:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec
; VI: %2:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %3, implicit $mode, implicit $exec
; VI: $vgpr0 = COPY %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0 %1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s32) = G_FPTOSI %1 %2:vgpr(s32) = G_FPTOSI %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: fptosi_s16_to_s32_vs name: fptosi_s16_to_s32_vs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; GCN-LABEL: name: fptosi_s16_to_s32_vs ; GCN-LABEL: name: fptosi_s16_to_s32_vs
; GCN: liveins: $sgpr0 ; GCN: liveins: $sgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: %3:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec ; GCN: %3:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GCN: %2:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %3, implicit $mode, implicit $exec ; GCN: %2:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %3, implicit $mode, implicit $exec
; GCN: $vgpr0 = COPY %2 ; GCN: $vgpr0 = COPY %2
; VI-LABEL: name: fptosi_s16_to_s32_vs
; VI: liveins: $sgpr0
; VI: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; VI: %3:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec
; VI: %2:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %3, implicit $mode, implicit $exec
; VI: $vgpr0 = COPY %2
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0 %1:sgpr(s16) = G_TRUNC %0
%2:vgpr(s32) = G_FPTOSI %1 %2:vgpr(s32) = G_FPTOSI %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: fptosi_s16_to_s32_fneg_vv name: fptosi_s16_to_s32_fneg_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GCN-LABEL: name: fptosi_s16_to_s32_fneg_vv ; GCN-LABEL: name: fptosi_s16_to_s32_fneg_vv
; GCN: liveins: $vgpr0 ; GCN: liveins: $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768 ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec ; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
; GCN: %4:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[V_XOR_B32_e32_]], implicit $mode, implicit $exec ; GCN: %4:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[V_XOR_B32_e32_]], implicit $mode, implicit $exec
; GCN: %3:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %4, implicit $mode, implicit $exec ; GCN: %3:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %4, implicit $mode, implicit $exec
; GCN: $vgpr0 = COPY %3 ; GCN: $vgpr0 = COPY %3
; VI-LABEL: name: fptosi_s16_to_s32_fneg_vv
; VI: liveins: $vgpr0
; VI: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; VI: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
; VI: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
; VI: %4:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[V_XOR_B32_e32_]], implicit $mode, implicit $exec
; VI: %3:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %4, implicit $mode, implicit $exec
; VI: $vgpr0 = COPY %3
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0 %1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s16) = G_FNEG %1 %2:vgpr(s16) = G_FNEG %1
%3:vgpr(s32) = G_FPTOSI %2 %3:vgpr(s32) = G_FPTOSI %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
--- ---
name: fptosi_s16_to_s1_vv name: fptosi_s16_to_s1_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GCN-LABEL: name: fptosi_s16_to_s1_vv ; GCN-LABEL: name: fptosi_s16_to_s1_vv
; GCN: liveins: $vgpr0 ; GCN: liveins: $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: %4:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec ; GCN: %4:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GCN: %2:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %4, implicit $mode, implicit $exec ; GCN: %2:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %4, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit %2 ; GCN: S_ENDPGM 0, implicit %2
; VI-LABEL: name: fptosi_s16_to_s1_vv
; VI: liveins: $vgpr0
; VI: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; VI: %4:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec
; VI: %2:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %4, implicit $mode, implicit $exec
; VI: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0 %1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s32) = G_FPTOSI %1 %2:vgpr(s32) = G_FPTOSI %1
%3:vgpr(s1) = G_TRUNC %2 %3:vgpr(s1) = G_TRUNC %2
S_ENDPGM 0, implicit %3 S_ENDPGM 0, implicit %3
... ...
--- ---
name: fptosi_s16_to_s1_vs name: fptosi_s16_to_s1_vs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; GCN-LABEL: name: fptosi_s16_to_s1_vs ; GCN-LABEL: name: fptosi_s16_to_s1_vs
; GCN: liveins: $sgpr0 ; GCN: liveins: $sgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: %4:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec ; GCN: %4:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GCN: %2:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %4, implicit $mode, implicit $exec ; GCN: %2:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %4, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit %2 ; GCN: S_ENDPGM 0, implicit %2
; VI-LABEL: name: fptosi_s16_to_s1_vs
; VI: liveins: $sgpr0
; VI: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; VI: %4:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec
; VI: %2:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %4, implicit $mode, implicit $exec
; VI: S_ENDPGM 0, implicit %2
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0 %1:sgpr(s16) = G_TRUNC %0
%2:vgpr(s32) = G_FPTOSI %1 %2:vgpr(s32) = G_FPTOSI %1
%3:vgpr(s1) = G_TRUNC %2 %3:vgpr(s1) = G_TRUNC %2
S_ENDPGM 0, implicit %3 S_ENDPGM 0, implicit %3
... ...
--- ---
Show All 9 Lines bb.0:
; GCN-LABEL: name: fptosi_s16_to_s1_fneg_vv ; GCN-LABEL: name: fptosi_s16_to_s1_fneg_vv
; GCN: liveins: $vgpr0 ; GCN: liveins: $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768 ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec ; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
; GCN: %5:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[V_XOR_B32_e32_]], implicit $mode, implicit $exec ; GCN: %5:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[V_XOR_B32_e32_]], implicit $mode, implicit $exec
; GCN: %3:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %5, implicit $mode, implicit $exec ; GCN: %3:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %5, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit %3 ; GCN: S_ENDPGM 0, implicit %3
; VI-LABEL: name: fptosi_s16_to_s1_fneg_vv
; VI: liveins: $vgpr0
; VI: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; VI: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
; VI: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
; VI: %5:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[V_XOR_B32_e32_]], implicit $mode, implicit $exec
; VI: %3:vgpr_32 = nofpexcept V_CVT_I32_F32_e32 %5, implicit $mode, implicit $exec
; VI: S_ENDPGM 0, implicit %3
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0 %1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s16) = G_FNEG %1 %2:vgpr(s16) = G_FNEG %1
%3:vgpr(s32) = G_FPTOSI %2 %3:vgpr(s32) = G_FPTOSI %2
%4:vgpr(s1) = G_TRUNC %3 %4:vgpr(s1) = G_TRUNC %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefix=GCN # RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefix=GCN
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -run-pass=instruction-select -verify-machineinstrs -o - %s | FileCheck %s -check-prefix=VI
--- ---
name: fptoui name: fptoui
legalized: true legalized: true
regBankSelected: true regBankSelected: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0, $vgpr0, $vgpr3_vgpr4 liveins: $sgpr0, $vgpr0, $vgpr3_vgpr4
; GCN-LABEL: name: fptoui ; GCN-LABEL: name: fptoui
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4 ; GCN: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
; GCN: %3:vgpr_32 = nofpexcept V_CVT_U32_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec ; GCN: %3:vgpr_32 = nofpexcept V_CVT_U32_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; GCN: %4:vgpr_32 = nofpexcept V_CVT_U32_F32_e64 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec ; GCN: %4:vgpr_32 = nofpexcept V_CVT_U32_F32_e64 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; GCN: FLAT_STORE_DWORD [[COPY2]], %3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GCN: FLAT_STORE_DWORD [[COPY2]], %3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; GCN: FLAT_STORE_DWORD [[COPY2]], %4, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1) ; GCN: FLAT_STORE_DWORD [[COPY2]], %4, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; VI-LABEL: name: fptoui
; VI: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; VI: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; VI: [[COPY2:%[0-9]+]]:vreg_64 = COPY $vgpr3_vgpr4
; VI: %3:vgpr_32 = nofpexcept V_CVT_U32_F32_e64 0, [[COPY]], 0, 0, implicit $mode, implicit $exec
; VI: %4:vgpr_32 = nofpexcept V_CVT_U32_F32_e64 0, [[COPY1]], 0, 0, implicit $mode, implicit $exec
; VI: FLAT_STORE_DWORD [[COPY2]], %3, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
; VI: FLAT_STORE_DWORD [[COPY2]], %4, 0, 0, 0, 0, implicit $exec, implicit $flat_scr :: (store 4, addrspace 1)
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:vgpr(s32) = COPY $vgpr0 %1:vgpr(s32) = COPY $vgpr0
%2:vgpr(p1) = COPY $vgpr3_vgpr4 %2:vgpr(p1) = COPY $vgpr3_vgpr4
; fptoui s ; fptoui s
%3:vgpr(s32) = G_FPTOUI %0 %3:vgpr(s32) = G_FPTOUI %0
Show All 16 Lines bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GCN-LABEL: name: fptoui_s16_to_s32_vv ; GCN-LABEL: name: fptoui_s16_to_s32_vv
; GCN: liveins: $vgpr0 ; GCN: liveins: $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: %3:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec ; GCN: %3:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GCN: %2:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 %3, implicit $mode, implicit $exec ; GCN: %2:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 %3, implicit $mode, implicit $exec
; GCN: $vgpr0 = COPY %2 ; GCN: $vgpr0 = COPY %2
; VI-LABEL: name: fptoui_s16_to_s32_vv
; VI: liveins: $vgpr0
; VI: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; VI: %3:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec
; VI: %2:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 %3, implicit $mode, implicit $exec
; VI: $vgpr0 = COPY %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0 %1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s32) = G_FPTOUI %1 %2:vgpr(s32) = G_FPTOUI %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: fptoui_s16_to_s32_vs name: fptoui_s16_to_s32_vs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; GCN-LABEL: name: fptoui_s16_to_s32_vs ; GCN-LABEL: name: fptoui_s16_to_s32_vs
; GCN: liveins: $sgpr0 ; GCN: liveins: $sgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: %3:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec ; GCN: %3:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GCN: %2:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 %3, implicit $mode, implicit $exec ; GCN: %2:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 %3, implicit $mode, implicit $exec
; GCN: $vgpr0 = COPY %2 ; GCN: $vgpr0 = COPY %2
; VI-LABEL: name: fptoui_s16_to_s32_vs
; VI: liveins: $sgpr0
; VI: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; VI: %3:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec
; VI: %2:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 %3, implicit $mode, implicit $exec
; VI: $vgpr0 = COPY %2
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0 %1:sgpr(s16) = G_TRUNC %0
%2:vgpr(s32) = G_FPTOUI %1 %2:vgpr(s32) = G_FPTOUI %1
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
--- ---
name: fptoui_s16_to_s32_fneg_vv name: fptoui_s16_to_s32_fneg_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GCN-LABEL: name: fptoui_s16_to_s32_fneg_vv ; GCN-LABEL: name: fptoui_s16_to_s32_fneg_vv
; GCN: liveins: $vgpr0 ; GCN: liveins: $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768 ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec ; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
; GCN: %4:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[V_XOR_B32_e32_]], implicit $mode, implicit $exec ; GCN: %4:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[V_XOR_B32_e32_]], implicit $mode, implicit $exec
; GCN: %3:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 %4, implicit $mode, implicit $exec ; GCN: %3:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 %4, implicit $mode, implicit $exec
; GCN: $vgpr0 = COPY %3 ; GCN: $vgpr0 = COPY %3
; VI-LABEL: name: fptoui_s16_to_s32_fneg_vv
; VI: liveins: $vgpr0
; VI: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; VI: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
; VI: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
; VI: %4:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[V_XOR_B32_e32_]], implicit $mode, implicit $exec
; VI: %3:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 %4, implicit $mode, implicit $exec
; VI: $vgpr0 = COPY %3
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0 %1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s16) = G_FNEG %1 %2:vgpr(s16) = G_FNEG %1
%3:vgpr(s32) = G_FPTOUI %2 %3:vgpr(s32) = G_FPTOUI %2
$vgpr0 = COPY %3 $vgpr0 = COPY %3
... ...
--- ---
name: fptoui_s16_to_s1_vv name: fptoui_s16_to_s1_vv
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $vgpr0 liveins: $vgpr0
; GCN-LABEL: name: fptoui_s16_to_s1_vv ; GCN-LABEL: name: fptoui_s16_to_s1_vv
; GCN: liveins: $vgpr0 ; GCN: liveins: $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: %4:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec ; GCN: %4:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GCN: %2:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 %4, implicit $mode, implicit $exec ; GCN: %2:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 %4, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit %2 ; GCN: S_ENDPGM 0, implicit %2
; VI-LABEL: name: fptoui_s16_to_s1_vv
; VI: liveins: $vgpr0
; VI: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; VI: %4:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec
; VI: %2:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 %4, implicit $mode, implicit $exec
; VI: S_ENDPGM 0, implicit %2
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0 %1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s32) = G_FPTOUI %1 %2:vgpr(s32) = G_FPTOUI %1
%3:vgpr(s1) = G_TRUNC %2 %3:vgpr(s1) = G_TRUNC %2
S_ENDPGM 0, implicit %3 S_ENDPGM 0, implicit %3
... ...
--- ---
name: fptoui_s16_to_s1_vs name: fptoui_s16_to_s1_vs
legalized: true legalized: true
regBankSelected: true regBankSelected: true
tracksRegLiveness: true tracksRegLiveness: true
body: | body: |
bb.0: bb.0:
liveins: $sgpr0 liveins: $sgpr0
; GCN-LABEL: name: fptoui_s16_to_s1_vs ; GCN-LABEL: name: fptoui_s16_to_s1_vs
; GCN: liveins: $sgpr0 ; GCN: liveins: $sgpr0
; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0 ; GCN: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; GCN: %4:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec ; GCN: %4:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec
; GCN: %2:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 %4, implicit $mode, implicit $exec ; GCN: %2:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 %4, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit %2 ; GCN: S_ENDPGM 0, implicit %2
; VI-LABEL: name: fptoui_s16_to_s1_vs
; VI: liveins: $sgpr0
; VI: [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
; VI: %4:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[COPY]], implicit $mode, implicit $exec
; VI: %2:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 %4, implicit $mode, implicit $exec
; VI: S_ENDPGM 0, implicit %2
%0:sgpr(s32) = COPY $sgpr0 %0:sgpr(s32) = COPY $sgpr0
%1:sgpr(s16) = G_TRUNC %0 %1:sgpr(s16) = G_TRUNC %0
%2:vgpr(s32) = G_FPTOUI %1 %2:vgpr(s32) = G_FPTOUI %1
%3:vgpr(s1) = G_TRUNC %2 %3:vgpr(s1) = G_TRUNC %2
S_ENDPGM 0, implicit %3 S_ENDPGM 0, implicit %3
... ...
--- ---
Show All 9 Lines bb.0:
; GCN-LABEL: name: fptoui_s16_to_s1_fneg_vv ; GCN-LABEL: name: fptoui_s16_to_s1_fneg_vv
; GCN: liveins: $vgpr0 ; GCN: liveins: $vgpr0
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0 ; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768 ; GCN: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec ; GCN: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
; GCN: %5:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[V_XOR_B32_e32_]], implicit $mode, implicit $exec ; GCN: %5:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[V_XOR_B32_e32_]], implicit $mode, implicit $exec
; GCN: %3:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 %5, implicit $mode, implicit $exec ; GCN: %3:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 %5, implicit $mode, implicit $exec
; GCN: S_ENDPGM 0, implicit %3 ; GCN: S_ENDPGM 0, implicit %3
; VI-LABEL: name: fptoui_s16_to_s1_fneg_vv
; VI: liveins: $vgpr0
; VI: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
; VI: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 32768
; VI: [[V_XOR_B32_e32_:%[0-9]+]]:vgpr_32 = V_XOR_B32_e32 [[S_MOV_B32_]], [[COPY]], implicit $exec
; VI: %5:vgpr_32 = nofpexcept V_CVT_F32_F16_e32 [[V_XOR_B32_e32_]], implicit $mode, implicit $exec
; VI: %3:vgpr_32 = nofpexcept V_CVT_U32_F32_e32 %5, implicit $mode, implicit $exec
; VI: S_ENDPGM 0, implicit %3
%0:vgpr(s32) = COPY $vgpr0 %0:vgpr(s32) = COPY $vgpr0
%1:vgpr(s16) = G_TRUNC %0 %1:vgpr(s16) = G_TRUNC %0
%2:vgpr(s16) = G_FNEG %1 %2:vgpr(s16) = G_FNEG %1
%3:vgpr(s32) = G_FPTOUI %2 %3:vgpr(s32) = G_FPTOUI %2
%4:vgpr(s1) = G_TRUNC %3 %4:vgpr(s1) = G_TRUNC %3
S_ENDPGM 0, implicit %4 S_ENDPGM 0, implicit %4
... ...