[AMDGPU] Add f16 to i1 CodeGen patterns.

[whchung]

Summary

Follow patterns used for f32 and f64 types.

[whchung]

The patterns were found in some MLIR-based applications.

[rampitec]

LGTM

[arsenm]

Should also test globalisel

[whchung]

@arsenm Could you help me understand if my understanding is correct to fulfill your requirement of 'test globalisel'?

• change the followings under llvm/test/CodeGen/AMDGPU/GlobalISel:
  • inst-select-fptosi.mir
  • legalize-fptosi.mir
  • inst-select-fptoui.mir
  • legalize-fptoui.mir
• populate FileCheck macros with update_mir_test_checks.py

[whchung]

Add MIR-level tests.

[arsenm]

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir

117–122 ↗

(On Diff #321496)

This isn't testing a target with f16 instructions

[whchung]

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir

117–122 ↗

(On Diff #321496)

@arsenm Could you help review if https://reviews.llvm.org/D96061 addresses your concerns? Thanks.

[arsenm]

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir

123–126 ↗

(On Diff #321496)

Hmm. It looks like these patterns aren't working. The MIR register banks are also not what I would expect. I think this needs some up-front work in the legalizer/regbankselect to handle properly, and would need end to end IR tests

[whchung]

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir

123–126 ↗

(On Diff #321496)

@arsenm I'll take a look into AMDGPULegalizerInfo and AMDGPURegisterBankInfo. I'm not that well-versed in these aspect so I may come up with questions initially.

For end-to-end IR tests, do you feel any additions to fptosi.f16.ll and fptoui.f16.ll in this patch needed?

[arsenm]

llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-fptoui.mir

123–126 ↗

(On Diff #321496)

Some cases that use the i1 result in a boolean context (e.g. branch or select condition) would be helpful

llvm/lib/Target/AMDGPU/SIInstructions.td

(V_CNDMASK_B32_e64 /*src0mod*/(i32 0), /*src0*/(i32 0),
                        /*src1mod*/(i32 0), /*src1*/(i32 -1), $src), sub1)
 >;
 
 class FPToI1Pat<Instruction Inst, int KOne, ValueType kone_type, ValueType vt, SDPatternOperator fp_to_int> : GCNPat <
   (i1 (fp_to_int (vt (VOP3Mods vt:$src0, i32:$src0_modifiers)))),
   (i1 (Inst 0, (kone_type KOne), $src0_modifiers, $src0, DSTCLAMP.NONE))
 >;
 
+def : FPToI1Pat<V_CMP_EQ_F16_e64, CONST.FP16_ONE, i16, f16, fp_to_uint>;
+def : FPToI1Pat<V_CMP_EQ_F16_e64, CONST.FP16_NEG_ONE, i16, f16, fp_to_sint>;
 def : FPToI1Pat<V_CMP_EQ_F32_e64, CONST.FP32_ONE, i32, f32, fp_to_uint>;
 def : FPToI1Pat<V_CMP_EQ_F32_e64, CONST.FP32_NEG_ONE, i32, f32, fp_to_sint>;
 def : FPToI1Pat<V_CMP_EQ_F64_e64, CONST.FP64_ONE, i64, f64, fp_to_uint>;
 def : FPToI1Pat<V_CMP_EQ_F64_e64, CONST.FP64_NEG_ONE, i64, f64, fp_to_sint>;
 
 // If we need to perform a logical operation on i1 values, we need to
 // use vector comparisons since there is only one SCC register. Vector
 // comparisons may write to a pair of SGPRs or a single SGPR, so treat

llvm/test/CodeGen/AMDGPU/fptosi.f16.ll

define amdgpu_kernel void @fptosi_v2f16_to_v2i64(
     <2 x i64> addrspace(1)* %r,
     <2 x half> addrspace(1)* %a) {
 entry:
   %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
   %r.val = fptosi <2 x half> %a.val to <2 x i64>
   store <2 x i64> %r.val, <2 x i64> addrspace(1)* %r
   ret void
 }
+
+; GCN-LABEL: {{^}}fptosi_f16_to_i1:
+; SI: v_cvt_f32_f16_e32 v{{[0-9+]}}, s{{[0-9]+}}
+; SI: v_cmp_eq_f32_e32 vcc, -1.0, v{{[0-9]+}}
+; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc
+; VI: v_cmp_eq_f16_e64 s{{\[[0-9]+:[0-9]+\]}}, 0xbc00, s{{[0-9]+}}
+; VI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, s[0:1]
+define amdgpu_kernel void @fptosi_f16_to_i1(i1 addrspace(1)* %out, half %in) {
+entry:
+  %conv = fptosi half %in to i1
+  store i1 %conv, i1 addrspace(1)* %out
+  ret void
+}

llvm/test/CodeGen/AMDGPU/fptoui.f16.ll

define amdgpu_kernel void @fptoui_v2f16_to_v2i64(
     <2 x i64> addrspace(1)* %r,
     <2 x half> addrspace(1)* %a) {
 entry:
   %a.val = load <2 x half>, <2 x half> addrspace(1)* %a
   %r.val = fptoui <2 x half> %a.val to <2 x i64>
   store <2 x i64> %r.val, <2 x i64> addrspace(1)* %r
   ret void
 }
+
+; GCN-LABEL: {{^}}fptoui_f16_to_i1:
+; SI: v_cvt_f32_f16_e32 v{{[0-9+]}}, s{{[0-9]+}}
+; SI: v_cmp_eq_f32_e32 vcc, 1.0, v{{[0-9]+}}
+; SI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, vcc
+; VI: v_cmp_eq_f16_e64 s{{\[[0-9]+:[0-9]+\]}}, 1.0, s{{[0-9]+}}
+; VI: v_cndmask_b32_e64 v{{[0-9]+}}, 0, 1, s[0:1]
+define amdgpu_kernel void @fptoui_f16_to_i1(i1 addrspace(1)* %out, half %in) {
+entry:
+  %conv = fptoui half %in to i1
+  store i1 %conv, i1 addrspace(1)* %out
+  ret void
+}