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Differential D95179

[AArch64] Do not fold SP adjustments into pre-increment addr modes if it overflows the redzone.
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Authored by aemerson on Jan 21 2021, 2:58 PM.

Details

Reviewers
ab
eli.friedman
t.p.northover
Commits
rG0146d206317e: [AArch64] Do not fold SP adjustments into pre-increment addr modes if it…
Summary

Instead of outright disabling this completely with the noredzone attribute, we only avoid doing the optimization if there are memory operations between the adjustment and the load/store that the adjustment would be folded into. This avoids the case of something like a stack cookie being corrupted if an exception happens before the pre-increment to the SP occurs.

This also prevents the folding happening if we have a redzone, but the offset being folded is above the redzone amount (128 bytes in this case).

rdar://73269336

Diff Detail

Event Timeline

aemerson created this revision.Jan 21 2021, 2:58 PM
Herald added subscribers: danielkiss, hiraditya, kristof.beyls. · View Herald TranscriptJan 21 2021, 2:58 PM
aemerson requested review of this revision.Jan 21 2021, 2:58 PM
Harbormaster completed remote builds in B86174: Diff 318325.Jan 21 2021, 6:12 PM
aemerson added a comment.Jan 27 2021, 10:31 PM

ping

t.p.northover added a comment.Jan 28 2021, 1:17 AM

Is there a check that this folding doesn't overrun a red-zone if it does exist? If not, fixing that could well lead to a more natural way to solve this (where the bounds being checked are just 0 if there's no red-zone).

aemerson added a comment.Jan 28 2021, 11:17 AM
In D95179#2527478, @t.p.northover wrote:

Is there a check that this folding doesn't overrun a red-zone if it does exist? If not, fixing that could well lead to a more natural way to solve this (where the bounds being checked are just 0 if there's no red-zone).

Yeah, that's a good idea.

aemerson updated this revision to Diff 325509.Feb 22 2021, 11:31 AM
aemerson retitled this revision from [AArch64] Do not fold SP adjustments into pre-increment addr modes with noredzone. to [AArch64] Do not fold SP adjustments into pre-increment addr modes if it overflows the redzone..
aemerson edited the summary of this revision. (Show Details)

Prevent folding in the offset if it's too large, even if we have a red zone.

Harbormaster completed remote builds in B90251: Diff 325509.Feb 22 2021, 12:22 PM
t.p.northover accepted this revision.Feb 24 2021, 6:57 AM

Thanks. LGTM.

This revision is now accepted and ready to land.Feb 24 2021, 6:57 AM
Closed by commit rG0146d206317e: [AArch64] Do not fold SP adjustments into pre-increment addr modes if it… (authored by aemerson). · Explain WhyFeb 24 2021, 9:56 AM
This revision was automatically updated to reflect the committed changes.
aemerson added a commit: rG0146d206317e: [AArch64] Do not fold SP adjustments into pre-increment addr modes if it….

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
8 lines
8 lines
19 lines
test/
CodeGen/
AArch64/
407 lines

Diff 326128

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

Show First 20 Lines • Show All 319 Lines • ▼ Show 20 Lines
static StackOffset getSVEStackSize(const MachineFunction &MF) { static StackOffset getSVEStackSize(const MachineFunction &MF) {
const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>(); const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
return StackOffset::getScalable((int64_t)AFI->getStackSizeSVE()); return StackOffset::getScalable((int64_t)AFI->getStackSizeSVE());
} }
bool AArch64FrameLowering::canUseRedZone(const MachineFunction &MF) const { bool AArch64FrameLowering::canUseRedZone(const MachineFunction &MF) const {
if (!EnableRedZone) if (!EnableRedZone)
return false; return false;
// Don't use the red zone if the function explicitly asks us not to. // Don't use the red zone if the function explicitly asks us not to.
// This is typically used for kernel code. // This is typically used for kernel code.
if (MF.getFunction().hasFnAttribute(Attribute::NoRedZone)) const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
const unsigned RedZoneSize =
Subtarget.getTargetLowering()->getRedZoneSize(MF.getFunction());
if (!RedZoneSize)
return false; return false;
const MachineFrameInfo &MFI = MF.getFrameInfo(); const MachineFrameInfo &MFI = MF.getFrameInfo();
const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>(); const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
uint64_t NumBytes = AFI->getLocalStackSize(); uint64_t NumBytes = AFI->getLocalStackSize();
return !(MFI.hasCalls() || hasFP(MF) || NumBytes > 128 || return !(MFI.hasCalls() || hasFP(MF) || NumBytes > RedZoneSize ||
getSVEStackSize(MF)); getSVEStackSize(MF));
} }
/// hasFP - Return true if the specified function should have a dedicated frame /// hasFP - Return true if the specified function should have a dedicated frame
/// pointer register. /// pointer register.
bool AArch64FrameLowering::hasFP(const MachineFunction &MF) const { bool AArch64FrameLowering::hasFP(const MachineFunction &MF) const {
const MachineFrameInfo &MFI = MF.getFrameInfo(); const MachineFrameInfo &MFI = MF.getFrameInfo();
const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>(); const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
▲ Show 20 Lines • Show All 3,233 Lines • Show Last 20 Lines

llvm/lib/Target/AArch64/AArch64ISelLowering.h

Show All 10 Lines
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#ifndef LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H #ifndef LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
#define LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H #define LLVM_LIB_TARGET_AARCH64_AARCH64ISELLOWERING_H
#include "AArch64.h" #include "AArch64.h"
#include "llvm/CodeGen/CallingConvLower.h" #include "llvm/CodeGen/CallingConvLower.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/SelectionDAG.h" #include "llvm/CodeGen/SelectionDAG.h"
#include "llvm/CodeGen/TargetLowering.h" #include "llvm/CodeGen/TargetLowering.h"
#include "llvm/IR/CallingConv.h" #include "llvm/IR/CallingConv.h"
#include "llvm/IR/Instruction.h" #include "llvm/IR/Instruction.h"
namespace llvm { namespace llvm {
namespace AArch64ISD { namespace AArch64ISD {
▲ Show 20 Lines • Show All 775 Lines • ▼ Show 20 Linespublic:
/// SVE code generation for fixed length vectors does not custom lower /// SVE code generation for fixed length vectors does not custom lower
/// BUILD_VECTOR. This makes BUILD_VECTOR legalisation a source of stores to /// BUILD_VECTOR. This makes BUILD_VECTOR legalisation a source of stores to
/// merge. However, merging them creates a BUILD_VECTOR that is just as /// merge. However, merging them creates a BUILD_VECTOR that is just as
/// illegal as the original, thus leading to an infinite legalisation loop. /// illegal as the original, thus leading to an infinite legalisation loop.
/// NOTE: Once BUILD_VECTOR is legal or can be custom lowered for all legal /// NOTE: Once BUILD_VECTOR is legal or can be custom lowered for all legal
/// vector types this override can be removed. /// vector types this override can be removed.
bool mergeStoresAfterLegalization(EVT VT) const override; bool mergeStoresAfterLegalization(EVT VT) const override;
// If the platform/function should have a redzone, return the size in bytes.
unsigned getRedZoneSize(const Function &F) const {
if (F.hasFnAttribute(Attribute::NoRedZone))
return 0;
return 128;
}
private: private:
/// Keep a pointer to the AArch64Subtarget around so that we can /// Keep a pointer to the AArch64Subtarget around so that we can
/// make the right decision when generating code for different targets. /// make the right decision when generating code for different targets.
const AArch64Subtarget *Subtarget; const AArch64Subtarget *Subtarget;
bool isExtFreeImpl(const Instruction *Ext) const override; bool isExtFreeImpl(const Instruction *Ext) const override;
void addTypeForNEON(MVT VT, MVT PromotedBitwiseVT); void addTypeForNEON(MVT VT, MVT PromotedBitwiseVT);
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llvm/lib/Target/AArch64/AArch64LoadStoreOptimizer.cpp

//===- AArch64LoadStoreOptimizer.cpp - AArch64 load/store opt. pass -------===// //===- AArch64LoadStoreOptimizer.cpp - AArch64 load/store opt. pass -------===//
// //
// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
// See https://llvm.org/LICENSE.txt for license information. // See https://llvm.org/LICENSE.txt for license information.
// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// //
// This file contains a pass that performs load / store related peephole // This file contains a pass that performs load / store related peephole
// optimizations. This pass should be run after register allocation. // optimizations. This pass should be run after register allocation.
// //
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
#include "AArch64InstrInfo.h" #include "AArch64InstrInfo.h"
#include "AArch64MachineFunctionInfo.h"
#include "AArch64Subtarget.h" #include "AArch64Subtarget.h"
#include "MCTargetDesc/AArch64AddressingModes.h" #include "MCTargetDesc/AArch64AddressingModes.h"
#include "llvm/ADT/BitVector.h" #include "llvm/ADT/BitVector.h"
#include "llvm/ADT/SmallVector.h" #include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/Statistic.h" #include "llvm/ADT/Statistic.h"
#include "llvm/ADT/StringRef.h" #include "llvm/ADT/StringRef.h"
#include "llvm/ADT/iterator_range.h" #include "llvm/ADT/iterator_range.h"
#include "llvm/Analysis/AliasAnalysis.h" #include "llvm/Analysis/AliasAnalysis.h"
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} }
MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnBackward( MachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnBackward(
MachineBasicBlock::iterator I, unsigned Limit) { MachineBasicBlock::iterator I, unsigned Limit) {
MachineBasicBlock::iterator B = I->getParent()->begin(); MachineBasicBlock::iterator B = I->getParent()->begin();
MachineBasicBlock::iterator E = I->getParent()->end(); MachineBasicBlock::iterator E = I->getParent()->end();
MachineInstr &MemMI = *I; MachineInstr &MemMI = *I;
MachineBasicBlock::iterator MBBI = I; MachineBasicBlock::iterator MBBI = I;
MachineFunction &MF = *MemMI.getMF();
Register BaseReg = getLdStBaseOp(MemMI).getReg(); Register BaseReg = getLdStBaseOp(MemMI).getReg();
int Offset = getLdStOffsetOp(MemMI).getImm(); int Offset = getLdStOffsetOp(MemMI).getImm();
// If the load/store is the first instruction in the block, there's obviously // If the load/store is the first instruction in the block, there's obviously
// not any matching update. Ditto if the memory offset isn't zero. // not any matching update. Ditto if the memory offset isn't zero.
if (MBBI == B || Offset != 0) if (MBBI == B || Offset != 0)
return E; return E;
Show All 11 LinesMachineBasicBlock::iterator AArch64LoadStoreOpt::findMatchingUpdateInsnBackward(
const bool BaseRegSP = BaseReg == AArch64::SP; const bool BaseRegSP = BaseReg == AArch64::SP;
if (BaseRegSP && needsWinCFI(I->getMF())) { if (BaseRegSP && needsWinCFI(I->getMF())) {
// FIXME: For now, we always block the optimization over SP in windows // FIXME: For now, we always block the optimization over SP in windows
// targets as it requires to adjust the unwind/debug info, messing up // targets as it requires to adjust the unwind/debug info, messing up
// the unwind info can actually cause a miscompile. // the unwind info can actually cause a miscompile.
return E; return E;
} }
const AArch64Subtarget &Subtarget = MF.getSubtarget<AArch64Subtarget>();
unsigned RedZoneSize =
Subtarget.getTargetLowering()->getRedZoneSize(MF.getFunction());
// Track which register units have been modified and used between the first // Track which register units have been modified and used between the first
// insn (inclusive) and the second insn. // insn (inclusive) and the second insn.
ModifiedRegUnits.clear(); ModifiedRegUnits.clear();
UsedRegUnits.clear(); UsedRegUnits.clear();
unsigned Count = 0; unsigned Count = 0;
bool MemAcessBeforeSPPreInc = false;
do { do {
MBBI = prev_nodbg(MBBI, B); MBBI = prev_nodbg(MBBI, B);
MachineInstr &MI = *MBBI; MachineInstr &MI = *MBBI;
// Don't count transient instructions towards the search limit since there // Don't count transient instructions towards the search limit since there
// may be different numbers of them if e.g. debug information is present. // may be different numbers of them if e.g. debug information is present.
if (!MI.isTransient()) if (!MI.isTransient())
++Count; ++Count;
// If we found a match, return it. // If we found a match, return it.
if (isMatchingUpdateInsn(*I, MI, BaseReg, Offset)) if (isMatchingUpdateInsn(*I, MI, BaseReg, Offset)) {
// Check that the update value is within our red zone limit (which may be
// zero).
if (MemAcessBeforeSPPreInc && MBBI->getOperand(2).getImm() > RedZoneSize)
return E;
return MBBI; return MBBI;
}
// Update the status of what the instruction clobbered and used. // Update the status of what the instruction clobbered and used.
LiveRegUnits::accumulateUsedDefed(MI, ModifiedRegUnits, UsedRegUnits, TRI); LiveRegUnits::accumulateUsedDefed(MI, ModifiedRegUnits, UsedRegUnits, TRI);
// Otherwise, if the base register is used or modified, we have no match, so // Otherwise, if the base register is used or modified, we have no match, so
// return early. // return early.
if (!ModifiedRegUnits.available(BaseReg) || if (!ModifiedRegUnits.available(BaseReg) ||
!UsedRegUnits.available(BaseReg)) !UsedRegUnits.available(BaseReg))
return E; return E;
// Keep track if we have a memory access before an SP pre-increment, in this
// case we need to validate later that the update amount respects the red
// zone.
if (BaseRegSP && MBBI->mayLoadOrStore())
MemAcessBeforeSPPreInc = true;
} while (MBBI != B && Count < Limit); } while (MBBI != B && Count < Limit);
return E; return E;
} }
bool AArch64LoadStoreOpt::tryToPromoteLoadFromStore( bool AArch64LoadStoreOpt::tryToPromoteLoadFromStore(
MachineBasicBlock::iterator &MBBI) { MachineBasicBlock::iterator &MBBI) {
MachineInstr &MI = *MBBI; MachineInstr &MI = *MBBI;
// If this is a volatile load, don't mess with it. // If this is a volatile load, don't mess with it.
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llvm/test/CodeGen/AArch64/ldst-nopreidx-sp-redzone.mir

  • This file was added.
# RUN: llc -mtriple=aarch64-apple-darwin -run-pass=aarch64-ldst-opt -verify-machineinstrs -o - %s | FileCheck %s
--- |
target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128"
target triple = "arm64e-apple-ios13.0"
%struct.widget = type { i64, i64, i32, i32, i64, i64, i64, i64, i64, i32, i32, i32, i16, i32, %struct.snork*, %struct.zot, %struct.zot, %struct.zot, %struct.zot, %struct.zot, i64, i64, i64, i32, i64, i32, i32, i32, i8*, %struct.baz, %struct.baz, i64, i64, %struct.snork*, %struct.zot, i32, i32, i32, i32, i32, i32, i32, [32 x i8], i64, i64, %struct.wombat, i32, i64, i64, i64, i64 }
%struct.baz = type { [4 x i32] }
%struct.snork = type { i32, i32, [1 x %struct.spam] }
%struct.spam = type { %struct.baz, i32, i32 }
%struct.zot = type { i64, i64 }
%struct.wombat = type { [2 x i32] }
%struct.wombat.0 = type { [200 x i32] }
@__stack_chk_guard = external global i8*
; Function Attrs: noredzone ssp
define hidden void @with_noredzone_80bytes() #0 {
bb:
%StackGuardSlot = alloca i8*, align 8
%0 = call i8* @llvm.stackguard()
call void @llvm.stackprotector(i8* %0, i8** %StackGuardSlot)
%tmp = alloca %struct.widget, align 16
%tmp1 = alloca %struct.wombat.0*, align 8
%tmp2 = alloca %struct.wombat.0*, align 8
%tmp3 = alloca %struct.wombat.0*, align 8
%tmp4 = alloca %struct.wombat.0*, align 8
store %struct.wombat.0* null, %struct.wombat.0** %tmp3, align 8
store %struct.wombat.0* null, %struct.wombat.0** %tmp4, align 8
ret void
}
define hidden void @with_redzone_480bytes() #2 {
bb:
%StackGuardSlot = alloca i8*, align 8
%0 = call i8* @llvm.stackguard()
call void @llvm.stackprotector(i8* %0, i8** %StackGuardSlot)
%tmp = alloca %struct.widget, align 16
%tmp1 = alloca %struct.wombat.0*, align 8
%tmp2 = alloca %struct.wombat.0*, align 8
%tmp3 = alloca %struct.wombat.0*, align 8
%tmp4 = alloca %struct.wombat.0*, align 8
store %struct.wombat.0* null, %struct.wombat.0** %tmp3, align 8
store %struct.wombat.0* null, %struct.wombat.0** %tmp4, align 8
ret void
}
define hidden void @with_noredzone_no_mem_between() #0 {
bb:
%StackGuardSlot = alloca i8*, align 8
%0 = call i8* @llvm.stackguard()
call void @llvm.stackprotector(i8* %0, i8** %StackGuardSlot)
%tmp = alloca %struct.widget, align 16
%tmp1 = alloca %struct.wombat.0*, align 8
%tmp2 = alloca %struct.wombat.0*, align 8
%tmp3 = alloca %struct.wombat.0*, align 8
%tmp4 = alloca %struct.wombat.0*, align 8
store %struct.wombat.0* null, %struct.wombat.0** %tmp3, align 8
store %struct.wombat.0* null, %struct.wombat.0** %tmp4, align 8
ret void
}
; Function Attrs: nofree nosync nounwind willreturn
declare i8* @llvm.stackguard() #1
; Function Attrs: nofree nosync nounwind willreturn
declare void @llvm.stackprotector(i8*, i8**) #1
attributes #0 = { noredzone ssp "frame-pointer"="non-leaf" }
attributes #1 = { nofree nosync nounwind willreturn }
attributes #2 = { ssp "frame-pointer"="non-leaf" }
...
# Check that we don't try to combine the SUB with the STP using pre-index addressing
# if the function does not have redzone enabled.
# CHECK-LABEL: name: with_noredzone_80bytes
# CHECK-NOT: STPXpre $xzr, $xzr
---
name: with_noredzone_80bytes
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
hasWinCFI: false
registers: []
liveins: []
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 512
offsetAdjustment: 0
maxAlignment: 16
adjustsStack: true
hasCalls: true
stackProtector: '%stack.0.StackGuardSlot'
maxCallFrameSize: 0
cvBytesOfCalleeSavedRegisters: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 480
savePoint: ''
restorePoint: ''
fixedStack: []
stack:
- { id: 0, name: StackGuardSlot, type: default, offset: -40, size: 8,
alignment: 8, stack-id: default, callee-saved-register: '', callee-saved-restored: true,
local-offset: -8, debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' }
- { id: 1, name: tmp, type: default, offset: -480, size: 440, alignment: 16,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
local-offset: -448, debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' }
- { id: 2, name: tmp1, type: default, offset: -488, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
local-offset: -456, debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' }
- { id: 3, name: tmp2, type: default, offset: -496, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
local-offset: -464, debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' }
- { id: 4, name: tmp3, type: default, offset: -504, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
local-offset: -472, debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' }
- { id: 5, name: tmp4, type: default, offset: -512, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
local-offset: -480, debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' }
- { id: 6, name: '', type: spill-slot, offset: -8, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '$lr', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 7, name: '', type: spill-slot, offset: -16, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '$fp', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 8, name: '', type: spill-slot, offset: -24, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '$x27', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 9, name: '', type: spill-slot, offset: -32, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '$x28', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites: []
debugValueSubstitutions: []
constants: []
machineFunctionInfo:
hasRedZone: false
body: |
bb.0.bb:
successors: %bb.1(0x7ffff800), %bb.2(0x00000800)
liveins: $x27, $x28, $lr
early-clobber $sp = frame-setup STPXpre killed $x28, killed $x27, $sp, -4 :: (store 8 into %stack.9), (store 8 into %stack.8)
frame-setup STPXi killed $fp, killed $lr, $sp, 2 :: (store 8 into %stack.7), (store 8 into %stack.6)
$fp = frame-setup ADDXri $sp, 16, 0
$sp = frame-setup SUBXri $sp, 80, 0
frame-setup CFI_INSTRUCTION def_cfa $w29, 16
frame-setup CFI_INSTRUCTION offset $w30, -8
frame-setup CFI_INSTRUCTION offset $w29, -16
frame-setup CFI_INSTRUCTION offset $w27, -24
frame-setup CFI_INSTRUCTION offset $w28, -32
$x8 = ADRP target-flags(aarch64-page, aarch64-got) @__stack_chk_guard
$x8 = LDRXui killed $x8, target-flags(aarch64-pageoff, aarch64-got, aarch64-nc) @__stack_chk_guard
$x8 = LDRXui killed $x8, 0 :: (dereferenceable invariant load 8 from @__stack_chk_guard)
STURXi killed renamable $x8, $fp, -24 :: (volatile store 8 into %stack.0.StackGuardSlot)
STRXui $xzr, $sp, 1 :: (store 8 into %ir.tmp3)
STRXui $xzr, $sp, 0 :: (store 8 into %ir.tmp4)
renamable $x8 = LDURXi $fp, -24 :: (volatile load 8 from %stack.0.StackGuardSlot)
$x9 = ADRP target-flags(aarch64-page, aarch64-got) @__stack_chk_guard
$x9 = LDRXui killed $x9, target-flags(aarch64-pageoff, aarch64-got, aarch64-nc) @__stack_chk_guard
$x9 = LDRXui killed $x9, 0 :: (dereferenceable invariant load 8 from @__stack_chk_guard)
$xzr = SUBSXrs killed renamable $x9, killed renamable $x8, 0, implicit-def $nzcv, implicit-def $nzcv
Bcc 1, %bb.2, implicit $nzcv
bb.1.bb:
$sp = frame-destroy ADDXri $sp, 480, 0
$fp, $lr = frame-destroy LDPXi $sp, 2 :: (load 8 from %stack.7), (load 8 from %stack.6)
early-clobber $sp, $x28, $x27 = frame-destroy LDPXpost $sp, 4 :: (load 8 from %stack.9), (load 8 from %stack.8)
RET undef $lr
bb.2.bb:
BL &__stack_chk_fail, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
...
# Check we don't try to fold a 480 byte offset, even if we have a 128 byte redzone.
# CHECK-LABEL: name: with_redzone_480bytes
# CHECK-NOT: STPXpre $xzr, $xzr
---
name: with_redzone_480bytes
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
hasWinCFI: false
registers: []
liveins: []
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 512
offsetAdjustment: 0
maxAlignment: 16
adjustsStack: true
hasCalls: true
stackProtector: '%stack.0.StackGuardSlot'
maxCallFrameSize: 0
cvBytesOfCalleeSavedRegisters: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 480
savePoint: ''
restorePoint: ''
fixedStack: []
stack:
- { id: 0, name: StackGuardSlot, type: default, offset: -40, size: 8,
alignment: 8, stack-id: default, callee-saved-register: '', callee-saved-restored: true,
local-offset: -8, debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' }
- { id: 1, name: tmp, type: default, offset: -480, size: 440, alignment: 16,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
local-offset: -448, debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' }
- { id: 2, name: tmp1, type: default, offset: -488, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
local-offset: -456, debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' }
- { id: 3, name: tmp2, type: default, offset: -496, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
local-offset: -464, debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' }
- { id: 4, name: tmp3, type: default, offset: -504, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
local-offset: -472, debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' }
- { id: 5, name: tmp4, type: default, offset: -512, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
local-offset: -480, debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' }
- { id: 6, name: '', type: spill-slot, offset: -8, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '$lr', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 7, name: '', type: spill-slot, offset: -16, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '$fp', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 8, name: '', type: spill-slot, offset: -24, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '$x27', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 9, name: '', type: spill-slot, offset: -32, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '$x28', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites: []
debugValueSubstitutions: []
constants: []
body: |
bb.0.bb:
successors: %bb.1(0x7ffff800), %bb.2(0x00000800)
liveins: $x27, $x28, $lr
early-clobber $sp = frame-setup STPXpre killed $x28, killed $x27, $sp, -4 :: (store 8 into %stack.9), (store 8 into %stack.8)
frame-setup STPXi killed $fp, killed $lr, $sp, 2 :: (store 8 into %stack.7), (store 8 into %stack.6)
$fp = frame-setup ADDXri $sp, 16, 0
$sp = frame-setup SUBXri $sp, 480, 0
frame-setup CFI_INSTRUCTION def_cfa $w29, 16
frame-setup CFI_INSTRUCTION offset $w30, -8
frame-setup CFI_INSTRUCTION offset $w29, -16
frame-setup CFI_INSTRUCTION offset $w27, -24
frame-setup CFI_INSTRUCTION offset $w28, -32
$x8 = ADRP target-flags(aarch64-page, aarch64-got) @__stack_chk_guard
$x8 = LDRXui killed $x8, target-flags(aarch64-pageoff, aarch64-got, aarch64-nc) @__stack_chk_guard
$x8 = LDRXui killed $x8, 0 :: (dereferenceable invariant load 8 from @__stack_chk_guard)
STURXi killed renamable $x8, $fp, -24 :: (volatile store 8 into %stack.0.StackGuardSlot)
STRXui $xzr, $sp, 1 :: (store 8 into %ir.tmp3)
STRXui $xzr, $sp, 0 :: (store 8 into %ir.tmp4)
renamable $x8 = LDURXi $fp, -24 :: (volatile load 8 from %stack.0.StackGuardSlot)
$x9 = ADRP target-flags(aarch64-page, aarch64-got) @__stack_chk_guard
$x9 = LDRXui killed $x9, target-flags(aarch64-pageoff, aarch64-got, aarch64-nc) @__stack_chk_guard
$x9 = LDRXui killed $x9, 0 :: (dereferenceable invariant load 8 from @__stack_chk_guard)
$xzr = SUBSXrs killed renamable $x9, killed renamable $x8, 0, implicit-def $nzcv, implicit-def $nzcv
Bcc 1, %bb.2, implicit $nzcv
bb.1.bb:
$sp = frame-destroy ADDXri $sp, 480, 0
$fp, $lr = frame-destroy LDPXi $sp, 2 :: (load 8 from %stack.7), (load 8 from %stack.6)
early-clobber $sp, $x28, $x27 = frame-destroy LDPXpost $sp, 4 :: (load 8 from %stack.9), (load 8 from %stack.8)
RET undef $lr
bb.2.bb:
BL &__stack_chk_fail, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
...
# Check we still do the opt if there are no mem ops between.
# CHECK-LABEL: name: with_noredzone_no_mem_between
# CHECK: STPXpre $xzr, $xzr
---
name: with_noredzone_no_mem_between
alignment: 4
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
hasWinCFI: false
registers: []
liveins: []
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 512
offsetAdjustment: 0
maxAlignment: 16
adjustsStack: true
hasCalls: true
stackProtector: '%stack.0.StackGuardSlot'
maxCallFrameSize: 0
cvBytesOfCalleeSavedRegisters: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 480
savePoint: ''
restorePoint: ''
fixedStack: []
stack:
- { id: 0, name: StackGuardSlot, type: default, offset: -40, size: 8,
alignment: 8, stack-id: default, callee-saved-register: '', callee-saved-restored: true,
local-offset: -8, debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' }
- { id: 1, name: tmp, type: default, offset: -480, size: 440, alignment: 16,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
local-offset: -448, debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' }
- { id: 2, name: tmp1, type: default, offset: -488, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
local-offset: -456, debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' }
- { id: 3, name: tmp2, type: default, offset: -496, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
local-offset: -464, debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' }
- { id: 4, name: tmp3, type: default, offset: -504, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
local-offset: -472, debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' }
- { id: 5, name: tmp4, type: default, offset: -512, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
local-offset: -480, debug-info-variable: '', debug-info-expression: '',
debug-info-location: '' }
- { id: 6, name: '', type: spill-slot, offset: -8, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '$lr', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 7, name: '', type: spill-slot, offset: -16, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '$fp', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 8, name: '', type: spill-slot, offset: -24, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '$x27', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 9, name: '', type: spill-slot, offset: -32, size: 8, alignment: 8,
stack-id: default, callee-saved-register: '$x28', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites: []
debugValueSubstitutions: []
constants: []
machineFunctionInfo:
hasRedZone: false
body: |
bb.0.bb:
successors: %bb.1(0x7ffff800), %bb.2(0x00000800)
liveins: $x27, $x28, $lr
early-clobber $sp = frame-setup STPXpre killed $x28, killed $x27, $sp, -4 :: (store 8 into %stack.9), (store 8 into %stack.8)
frame-setup STPXi killed $fp, killed $lr, $sp, 2 :: (store 8 into %stack.7), (store 8 into %stack.6)
$fp = frame-setup ADDXri $sp, 16, 0
$sp = frame-setup SUBXri $sp, 480, 0
frame-setup CFI_INSTRUCTION def_cfa $w29, 16
frame-setup CFI_INSTRUCTION offset $w30, -8
frame-setup CFI_INSTRUCTION offset $w29, -16
frame-setup CFI_INSTRUCTION offset $w27, -24
frame-setup CFI_INSTRUCTION offset $w28, -32
$x8 = ADRP target-flags(aarch64-page, aarch64-got) @__stack_chk_guard
STRXui $xzr, $sp, 1 :: (store 8 into %ir.tmp3)
STRXui $xzr, $sp, 0 :: (store 8 into %ir.tmp4)
renamable $x8 = LDURXi $fp, -24 :: (volatile load 8 from %stack.0.StackGuardSlot)
$x9 = ADRP target-flags(aarch64-page, aarch64-got) @__stack_chk_guard
$x9 = LDRXui killed $x9, target-flags(aarch64-pageoff, aarch64-got, aarch64-nc) @__stack_chk_guard
$x9 = LDRXui killed $x9, 0 :: (dereferenceable invariant load 8 from @__stack_chk_guard)
$xzr = SUBSXrs killed renamable $x9, killed renamable $x8, 0, implicit-def $nzcv, implicit-def $nzcv
Bcc 1, %bb.2, implicit $nzcv
bb.1.bb:
$sp = frame-destroy ADDXri $sp, 480, 0
$fp, $lr = frame-destroy LDPXi $sp, 2 :: (load 8 from %stack.7), (load 8 from %stack.6)
early-clobber $sp, $x28, $x27 = frame-destroy LDPXpost $sp, 4 :: (load 8 from %stack.9), (load 8 from %stack.8)
RET undef $lr
bb.2.bb:
BL &__stack_chk_fail, csr_darwin_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
...