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Differential D94694

[RISCV] Add scalable-vector integer extension patterns
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Authored by frasercrmck on Jan 14 2021, 8:09 AM.

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Reviewers
craig.topper
evandro
rogfer01
HsiangKai
Commits
rGc81ea9429f8d: [RISCV] Add scalable-vector integer extension patterns

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Event Timeline

frasercrmck created this revision.Jan 14 2021, 8:09 AM
Herald added subscribers: NickHung, luismarques, apazos and 23 others. · View Herald TranscriptJan 14 2021, 8:09 AM
frasercrmck requested review of this revision.Jan 14 2021, 8:09 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 14 2021, 8:09 AM
Herald added subscribers: llvm-commits, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B85176: Diff 316668.Jan 14 2021, 9:55 AM
frasercrmck updated this revision to Diff 316994.Jan 15 2021, 9:18 AM
  • fix up bad type mangling in tests (e.g. nx4i8 -> nxv4i8)
Harbormaster completed remote builds in B85368: Diff 316994.Jan 15 2021, 10:45 AM
craig.topper added inline comments.Jan 15 2021, 12:06 PM
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
316

Should we handle any extend as well? Not sure how to test that with scalable vectors though

frasercrmck updated this revision to Diff 317319.Jan 18 2021, 3:38 AM
  • rebase on main
Harbormaster completed remote builds in B85579: Diff 317319.Jan 18 2021, 4:11 AM
frasercrmck added inline comments.Jan 18 2021, 7:18 AM
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
316

We probably should do any extend, yes. I've been looking around the codebase and couldn't really find an "in" to be able to test it in vanilla llvm. I don't think that should stop us, though. Do we have a preference for mapping it to sext or zext?

frasercrmck updated this revision to Diff 317356.Jan 18 2021, 7:45 AM

add pats for anyext: treat like zext for now

Harbormaster completed remote builds in B85598: Diff 317356.Jan 18 2021, 8:32 AM
craig.topper accepted this revision.Jan 18 2021, 11:29 PM

LGTM

This revision is now accepted and ready to land.Jan 18 2021, 11:29 PM
Closed by commit rGc81ea9429f8d: [RISCV] Add scalable-vector integer extension patterns (authored by frasercrmck). · Explain WhyJan 19 2021, 1:36 AM
This revision was automatically updated to reflect the committed changes.
frasercrmck added a commit: rGc81ea9429f8d: [RISCV] Add scalable-vector integer extension patterns.

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
19 lines
test/
CodeGen/
RISCV/
rvv/
619 lines
619 lines

Diff 317319

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Show First 20 Lines • Show All 269 Lines • ▼ Show 20 Lines
multiclass VPatFPSetCCSDNode_VV_VF_FV<CondCode cc, multiclass VPatFPSetCCSDNode_VV_VF_FV<CondCode cc,
string inst_name, string inst_name,
string swapped_op_inst_name> { string swapped_op_inst_name> {
defm : VPatFPSetCCSDNode_VV<cc, inst_name>; defm : VPatFPSetCCSDNode_VV<cc, inst_name>;
defm : VPatFPSetCCSDNode_VF<cc, inst_name>; defm : VPatFPSetCCSDNode_VF<cc, inst_name>;
defm : VPatFPSetCCSDNode_FV<cc, swapped_op_inst_name>; defm : VPatFPSetCCSDNode_FV<cc, swapped_op_inst_name>;
} }
multiclass VPatExtendSDNode_V<SDNode op, string inst_name, string suffix,
list <VTypeInfoToFraction> fraction_list> {
foreach vtiTofti = fraction_list in {
defvar vti = vtiTofti.Vti;
defvar fti = vtiTofti.Fti;
def : Pat<(vti.Vector (op (fti.Vector fti.RegClass:$rs2))),
(!cast<Instruction>(inst_name#"_"#suffix#"_"#vti.LMul.MX)
fti.RegClass:$rs2, VLMax, vti.SEW)>;
}
}
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Patterns. // Patterns.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let Predicates = [HasStdExtV] in { let Predicates = [HasStdExtV] in {
// 7.4. Vector Unit-Stride Instructions // 7.4. Vector Unit-Stride Instructions
defm "" : VPatUSLoadStoreSDNodes<GPR>; defm "" : VPatUSLoadStoreSDNodes<GPR>;
Show All 10 Lines def : Pat<(sub (vti.Vector (SplatPat XLenVT:$rs2)),
(!cast<Instruction>("PseudoVRSUB_VX_"# vti.LMul.MX) (!cast<Instruction>("PseudoVRSUB_VX_"# vti.LMul.MX)
vti.RegClass:$rs1, GPR:$rs2, VLMax, vti.SEW)>; vti.RegClass:$rs1, GPR:$rs2, VLMax, vti.SEW)>;
def : Pat<(sub (vti.Vector (SplatPat_simm5 XLenVT:$rs2)), def : Pat<(sub (vti.Vector (SplatPat_simm5 XLenVT:$rs2)),
(vti.Vector vti.RegClass:$rs1)), (vti.Vector vti.RegClass:$rs1)),
(!cast<Instruction>("PseudoVRSUB_VI_"# vti.LMul.MX) (!cast<Instruction>("PseudoVRSUB_VI_"# vti.LMul.MX)
vti.RegClass:$rs1, simm5:$rs2, VLMax, vti.SEW)>; vti.RegClass:$rs1, simm5:$rs2, VLMax, vti.SEW)>;
} }
// 12.3. Vector Integer Extension
defm "" : VPatExtendSDNode_V<zext, "PseudoVZEXT", "VF2", AllFractionableVF2IntVectors>;
craig.topperUnsubmitted
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Should we handle any extend as well? Not sure how to test that with scalable vectors though

craig.topper: Should we handle any extend as well? Not sure how to test that with scalable vectors though
frasercrmckAuthorUnsubmitted
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ReplyInline Actions

We probably should do any extend, yes. I've been looking around the codebase and couldn't really find an "in" to be able to test it in vanilla llvm. I don't think that should stop us, though. Do we have a preference for mapping it to sext or zext?

frasercrmck: We probably should do any extend, yes. I've been looking around the codebase and couldn't…
defm "" : VPatExtendSDNode_V<sext, "PseudoVSEXT", "VF2", AllFractionableVF2IntVectors>;
defm "" : VPatExtendSDNode_V<zext, "PseudoVZEXT", "VF4", AllFractionableVF4IntVectors>;
defm "" : VPatExtendSDNode_V<sext, "PseudoVSEXT", "VF4", AllFractionableVF4IntVectors>;
defm "" : VPatExtendSDNode_V<zext, "PseudoVZEXT", "VF8", AllFractionableVF8IntVectors>;
defm "" : VPatExtendSDNode_V<sext, "PseudoVSEXT", "VF8", AllFractionableVF8IntVectors>;
// 12.5. Vector Bitwise Logical Instructions // 12.5. Vector Bitwise Logical Instructions
defm "" : VPatBinarySDNode_VV_VX_VI<and, "PseudoVAND">; defm "" : VPatBinarySDNode_VV_VX_VI<and, "PseudoVAND">;
defm "" : VPatBinarySDNode_VV_VX_VI<or, "PseudoVOR">; defm "" : VPatBinarySDNode_VV_VX_VI<or, "PseudoVOR">;
defm "" : VPatBinarySDNode_VV_VX_VI<xor, "PseudoVXOR">; defm "" : VPatBinarySDNode_VV_VX_VI<xor, "PseudoVXOR">;
// 12.6. Vector Single-Width Bit Shift Instructions // 12.6. Vector Single-Width Bit Shift Instructions
defm "" : VPatBinarySDNode_VV_VX_VI<shl, "PseudoVSLL", uimm5>; defm "" : VPatBinarySDNode_VV_VX_VI<shl, "PseudoVSLL", uimm5>;
defm "" : VPatBinarySDNode_VV_VX_VI<srl, "PseudoVSRL", uimm5>; defm "" : VPatBinarySDNode_VV_VX_VI<srl, "PseudoVSRL", uimm5>;
▲ Show 20 Lines • Show All 198 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv32.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x i16> @vsext_nxv1i8_nxv1i16(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vsext_nxv1i8_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vsext.vf2 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = sext <vscale x 1 x i8> %va to <vscale x 1 x i16>
ret <vscale x 1 x i16> %evec
}
define <vscale x 1 x i16> @vzext_nxv1i8_nxv1i16(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vzext_nxv1i8_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vzext.vf2 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = zext <vscale x 1 x i8> %va to <vscale x 1 x i16>
ret <vscale x 1 x i16> %evec
}
define <vscale x 1 x i32> @vsext_nxv1i8_nxv1i32(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vsext_nxv1i8_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vsext.vf4 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = sext <vscale x 1 x i8> %va to <vscale x 1 x i32>
ret <vscale x 1 x i32> %evec
}
define <vscale x 1 x i32> @vzext_nxv1i8_nxv1i32(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vzext_nxv1i8_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vzext.vf4 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = zext <vscale x 1 x i8> %va to <vscale x 1 x i32>
ret <vscale x 1 x i32> %evec
}
define <vscale x 1 x i64> @vsext_nxv1i8_nxv1i64(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vsext_nxv1i8_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vsext.vf8 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = sext <vscale x 1 x i8> %va to <vscale x 1 x i64>
ret <vscale x 1 x i64> %evec
}
define <vscale x 1 x i64> @vzext_nxv1i8_nxv1i64(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vzext_nxv1i8_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vzext.vf8 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = zext <vscale x 1 x i8> %va to <vscale x 1 x i64>
ret <vscale x 1 x i64> %evec
}
define <vscale x 2 x i16> @vsext_nxv2i8_nxv2i16(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vsext_nxv2i8_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vsext.vf2 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = sext <vscale x 2 x i8> %va to <vscale x 2 x i16>
ret <vscale x 2 x i16> %evec
}
define <vscale x 2 x i16> @vzext_nxv2i8_nxv2i16(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vzext_nxv2i8_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vzext.vf2 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = zext <vscale x 2 x i8> %va to <vscale x 2 x i16>
ret <vscale x 2 x i16> %evec
}
define <vscale x 2 x i32> @vsext_nxv2i8_nxv2i32(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vsext_nxv2i8_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vsext.vf4 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = sext <vscale x 2 x i8> %va to <vscale x 2 x i32>
ret <vscale x 2 x i32> %evec
}
define <vscale x 2 x i32> @vzext_nxv2i8_nxv2i32(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vzext_nxv2i8_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vzext.vf4 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = zext <vscale x 2 x i8> %va to <vscale x 2 x i32>
ret <vscale x 2 x i32> %evec
}
define <vscale x 2 x i64> @vsext_nxv2i8_nxv2i64(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vsext_nxv2i8_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vsext.vf8 v26, v16
; CHECK-NEXT: vmv2r.v v16, v26
; CHECK-NEXT: ret
%evec = sext <vscale x 2 x i8> %va to <vscale x 2 x i64>
ret <vscale x 2 x i64> %evec
}
define <vscale x 2 x i64> @vzext_nxv2i8_nxv2i64(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vzext_nxv2i8_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vzext.vf8 v26, v16
; CHECK-NEXT: vmv2r.v v16, v26
; CHECK-NEXT: ret
%evec = zext <vscale x 2 x i8> %va to <vscale x 2 x i64>
ret <vscale x 2 x i64> %evec
}
define <vscale x 4 x i16> @vsext_nxv4i8_nxv4i16(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vsext_nxv4i8_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vsext.vf2 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = sext <vscale x 4 x i8> %va to <vscale x 4 x i16>
ret <vscale x 4 x i16> %evec
}
define <vscale x 4 x i16> @vzext_nxv4i8_nxv4i16(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vzext_nxv4i8_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vzext.vf2 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = zext <vscale x 4 x i8> %va to <vscale x 4 x i16>
ret <vscale x 4 x i16> %evec
}
define <vscale x 4 x i32> @vsext_nxv4i8_nxv4i32(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vsext_nxv4i8_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
; CHECK-NEXT: vsext.vf4 v26, v16
; CHECK-NEXT: vmv2r.v v16, v26
; CHECK-NEXT: ret
%evec = sext <vscale x 4 x i8> %va to <vscale x 4 x i32>
ret <vscale x 4 x i32> %evec
}
define <vscale x 4 x i32> @vzext_nxv4i8_nxv4i32(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vzext_nxv4i8_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
; CHECK-NEXT: vzext.vf4 v26, v16
; CHECK-NEXT: vmv2r.v v16, v26
; CHECK-NEXT: ret
%evec = zext <vscale x 4 x i8> %va to <vscale x 4 x i32>
ret <vscale x 4 x i32> %evec
}
define <vscale x 4 x i64> @vsext_nxv4i8_nxv4i64(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vsext_nxv4i8_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vsext.vf8 v28, v16
; CHECK-NEXT: vmv4r.v v16, v28
; CHECK-NEXT: ret
%evec = sext <vscale x 4 x i8> %va to <vscale x 4 x i64>
ret <vscale x 4 x i64> %evec
}
define <vscale x 4 x i64> @vzext_nxv4i8_nxv4i64(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vzext_nxv4i8_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vzext.vf8 v28, v16
; CHECK-NEXT: vmv4r.v v16, v28
; CHECK-NEXT: ret
%evec = zext <vscale x 4 x i8> %va to <vscale x 4 x i64>
ret <vscale x 4 x i64> %evec
}
define <vscale x 8 x i16> @vsext_nxv8i8_nxv8i16(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vsext_nxv8i8_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vsext.vf2 v26, v16
; CHECK-NEXT: vmv2r.v v16, v26
; CHECK-NEXT: ret
%evec = sext <vscale x 8 x i8> %va to <vscale x 8 x i16>
ret <vscale x 8 x i16> %evec
}
define <vscale x 8 x i16> @vzext_nxv8i8_nxv8i16(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vzext_nxv8i8_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vzext.vf2 v26, v16
; CHECK-NEXT: vmv2r.v v16, v26
; CHECK-NEXT: ret
%evec = zext <vscale x 8 x i8> %va to <vscale x 8 x i16>
ret <vscale x 8 x i16> %evec
}
define <vscale x 8 x i32> @vsext_nxv8i8_nxv8i32(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vsext_nxv8i8_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vsext.vf4 v28, v16
; CHECK-NEXT: vmv4r.v v16, v28
; CHECK-NEXT: ret
%evec = sext <vscale x 8 x i8> %va to <vscale x 8 x i32>
ret <vscale x 8 x i32> %evec
}
define <vscale x 8 x i32> @vzext_nxv8i8_nxv8i32(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vzext_nxv8i8_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vzext.vf4 v28, v16
; CHECK-NEXT: vmv4r.v v16, v28
; CHECK-NEXT: ret
%evec = zext <vscale x 8 x i8> %va to <vscale x 8 x i32>
ret <vscale x 8 x i32> %evec
}
define <vscale x 8 x i64> @vsext_nxv8i8_nxv8i64(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vsext_nxv8i8_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vsext.vf8 v8, v16
; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: ret
%evec = sext <vscale x 8 x i8> %va to <vscale x 8 x i64>
ret <vscale x 8 x i64> %evec
}
define <vscale x 8 x i64> @vzext_nxv8i8_nxv8i64(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vzext_nxv8i8_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vzext.vf8 v8, v16
; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: ret
%evec = zext <vscale x 8 x i8> %va to <vscale x 8 x i64>
ret <vscale x 8 x i64> %evec
}
define <vscale x 16 x i16> @vsext_nxv16i8_nxv16i16(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vsext_nxv16i8_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vsext.vf2 v28, v16
; CHECK-NEXT: vmv4r.v v16, v28
; CHECK-NEXT: ret
%evec = sext <vscale x 16 x i8> %va to <vscale x 16 x i16>
ret <vscale x 16 x i16> %evec
}
define <vscale x 16 x i16> @vzext_nxv16i8_nxv16i16(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vzext_nxv16i8_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vzext.vf2 v28, v16
; CHECK-NEXT: vmv4r.v v16, v28
; CHECK-NEXT: ret
%evec = zext <vscale x 16 x i8> %va to <vscale x 16 x i16>
ret <vscale x 16 x i16> %evec
}
define <vscale x 16 x i32> @vsext_nxv16i8_nxv16i32(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vsext_nxv16i8_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
; CHECK-NEXT: vsext.vf4 v8, v16
; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: ret
%evec = sext <vscale x 16 x i8> %va to <vscale x 16 x i32>
ret <vscale x 16 x i32> %evec
}
define <vscale x 16 x i32> @vzext_nxv16i8_nxv16i32(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vzext_nxv16i8_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
; CHECK-NEXT: vzext.vf4 v8, v16
; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: ret
%evec = zext <vscale x 16 x i8> %va to <vscale x 16 x i32>
ret <vscale x 16 x i32> %evec
}
define <vscale x 32 x i16> @vsext_nxv32i8_nxv32i16(<vscale x 32 x i8> %va) {
; CHECK-LABEL: vsext_nxv32i8_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vsext.vf2 v8, v16
; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: ret
%evec = sext <vscale x 32 x i8> %va to <vscale x 32 x i16>
ret <vscale x 32 x i16> %evec
}
define <vscale x 32 x i16> @vzext_nxv32i8_nxv32i16(<vscale x 32 x i8> %va) {
; CHECK-LABEL: vzext_nxv32i8_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vzext.vf2 v8, v16
; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: ret
%evec = zext <vscale x 32 x i8> %va to <vscale x 32 x i16>
ret <vscale x 32 x i16> %evec
}
define <vscale x 1 x i32> @vsext_nxv1i16_nxv1i32(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vsext_nxv1i16_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vsext.vf2 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = sext <vscale x 1 x i16> %va to <vscale x 1 x i32>
ret <vscale x 1 x i32> %evec
}
define <vscale x 1 x i32> @vzext_nxv1i16_nxv1i32(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vzext_nxv1i16_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vzext.vf2 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = zext <vscale x 1 x i16> %va to <vscale x 1 x i32>
ret <vscale x 1 x i32> %evec
}
define <vscale x 1 x i64> @vsext_nxv1i16_nxv1i64(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vsext_nxv1i16_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vsext.vf4 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = sext <vscale x 1 x i16> %va to <vscale x 1 x i64>
ret <vscale x 1 x i64> %evec
}
define <vscale x 1 x i64> @vzext_nxv1i16_nxv1i64(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vzext_nxv1i16_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vzext.vf4 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = zext <vscale x 1 x i16> %va to <vscale x 1 x i64>
ret <vscale x 1 x i64> %evec
}
define <vscale x 2 x i32> @vsext_nxv2i16_nxv2i32(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vsext_nxv2i16_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vsext.vf2 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = sext <vscale x 2 x i16> %va to <vscale x 2 x i32>
ret <vscale x 2 x i32> %evec
}
define <vscale x 2 x i32> @vzext_nxv2i16_nxv2i32(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vzext_nxv2i16_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vzext.vf2 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = zext <vscale x 2 x i16> %va to <vscale x 2 x i32>
ret <vscale x 2 x i32> %evec
}
define <vscale x 2 x i64> @vsext_nxv2i16_nxv2i64(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vsext_nxv2i16_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vsext.vf4 v26, v16
; CHECK-NEXT: vmv2r.v v16, v26
; CHECK-NEXT: ret
%evec = sext <vscale x 2 x i16> %va to <vscale x 2 x i64>
ret <vscale x 2 x i64> %evec
}
define <vscale x 2 x i64> @vzext_nxv2i16_nxv2i64(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vzext_nxv2i16_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vzext.vf4 v26, v16
; CHECK-NEXT: vmv2r.v v16, v26
; CHECK-NEXT: ret
%evec = zext <vscale x 2 x i16> %va to <vscale x 2 x i64>
ret <vscale x 2 x i64> %evec
}
define <vscale x 4 x i32> @vsext_nxv4i16_nxv4i32(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vsext_nxv4i16_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
; CHECK-NEXT: vsext.vf2 v26, v16
; CHECK-NEXT: vmv2r.v v16, v26
; CHECK-NEXT: ret
%evec = sext <vscale x 4 x i16> %va to <vscale x 4 x i32>
ret <vscale x 4 x i32> %evec
}
define <vscale x 4 x i32> @vzext_nxv4i16_nxv4i32(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vzext_nxv4i16_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
; CHECK-NEXT: vzext.vf2 v26, v16
; CHECK-NEXT: vmv2r.v v16, v26
; CHECK-NEXT: ret
%evec = zext <vscale x 4 x i16> %va to <vscale x 4 x i32>
ret <vscale x 4 x i32> %evec
}
define <vscale x 4 x i64> @vsext_nxv4i16_nxv4i64(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vsext_nxv4i16_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vsext.vf4 v28, v16
; CHECK-NEXT: vmv4r.v v16, v28
; CHECK-NEXT: ret
%evec = sext <vscale x 4 x i16> %va to <vscale x 4 x i64>
ret <vscale x 4 x i64> %evec
}
define <vscale x 4 x i64> @vzext_nxv4i16_nxv4i64(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vzext_nxv4i16_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vzext.vf4 v28, v16
; CHECK-NEXT: vmv4r.v v16, v28
; CHECK-NEXT: ret
%evec = zext <vscale x 4 x i16> %va to <vscale x 4 x i64>
ret <vscale x 4 x i64> %evec
}
define <vscale x 8 x i32> @vsext_nxv8i16_nxv8i32(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vsext_nxv8i16_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vsext.vf2 v28, v16
; CHECK-NEXT: vmv4r.v v16, v28
; CHECK-NEXT: ret
%evec = sext <vscale x 8 x i16> %va to <vscale x 8 x i32>
ret <vscale x 8 x i32> %evec
}
define <vscale x 8 x i32> @vzext_nxv8i16_nxv8i32(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vzext_nxv8i16_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vzext.vf2 v28, v16
; CHECK-NEXT: vmv4r.v v16, v28
; CHECK-NEXT: ret
%evec = zext <vscale x 8 x i16> %va to <vscale x 8 x i32>
ret <vscale x 8 x i32> %evec
}
define <vscale x 8 x i64> @vsext_nxv8i16_nxv8i64(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vsext_nxv8i16_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vsext.vf4 v8, v16
; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: ret
%evec = sext <vscale x 8 x i16> %va to <vscale x 8 x i64>
ret <vscale x 8 x i64> %evec
}
define <vscale x 8 x i64> @vzext_nxv8i16_nxv8i64(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vzext_nxv8i16_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vzext.vf4 v8, v16
; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: ret
%evec = zext <vscale x 8 x i16> %va to <vscale x 8 x i64>
ret <vscale x 8 x i64> %evec
}
define <vscale x 16 x i32> @vsext_nxv16i16_nxv16i32(<vscale x 16 x i16> %va) {
; CHECK-LABEL: vsext_nxv16i16_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
; CHECK-NEXT: vsext.vf2 v8, v16
; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: ret
%evec = sext <vscale x 16 x i16> %va to <vscale x 16 x i32>
ret <vscale x 16 x i32> %evec
}
define <vscale x 16 x i32> @vzext_nxv16i16_nxv16i32(<vscale x 16 x i16> %va) {
; CHECK-LABEL: vzext_nxv16i16_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
; CHECK-NEXT: vzext.vf2 v8, v16
; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: ret
%evec = zext <vscale x 16 x i16> %va to <vscale x 16 x i32>
ret <vscale x 16 x i32> %evec
}
define <vscale x 1 x i64> @vsext_nxv1i32_nxv1i64(<vscale x 1 x i32> %va) {
; CHECK-LABEL: vsext_nxv1i32_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vsext.vf2 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
ret <vscale x 1 x i64> %evec
}
define <vscale x 1 x i64> @vzext_nxv1i32_nxv1i64(<vscale x 1 x i32> %va) {
; CHECK-LABEL: vzext_nxv1i32_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vzext.vf2 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
ret <vscale x 1 x i64> %evec
}
define <vscale x 2 x i64> @vsext_nxv2i32_nxv2i64(<vscale x 2 x i32> %va) {
; CHECK-LABEL: vsext_nxv2i32_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vsext.vf2 v26, v16
; CHECK-NEXT: vmv2r.v v16, v26
; CHECK-NEXT: ret
%evec = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
ret <vscale x 2 x i64> %evec
}
define <vscale x 2 x i64> @vzext_nxv2i32_nxv2i64(<vscale x 2 x i32> %va) {
; CHECK-LABEL: vzext_nxv2i32_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vzext.vf2 v26, v16
; CHECK-NEXT: vmv2r.v v16, v26
; CHECK-NEXT: ret
%evec = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
ret <vscale x 2 x i64> %evec
}
define <vscale x 4 x i64> @vsext_nxv4i32_nxv4i64(<vscale x 4 x i32> %va) {
; CHECK-LABEL: vsext_nxv4i32_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vsext.vf2 v28, v16
; CHECK-NEXT: vmv4r.v v16, v28
; CHECK-NEXT: ret
%evec = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
ret <vscale x 4 x i64> %evec
}
define <vscale x 4 x i64> @vzext_nxv4i32_nxv4i64(<vscale x 4 x i32> %va) {
; CHECK-LABEL: vzext_nxv4i32_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vzext.vf2 v28, v16
; CHECK-NEXT: vmv4r.v v16, v28
; CHECK-NEXT: ret
%evec = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
ret <vscale x 4 x i64> %evec
}
define <vscale x 8 x i64> @vsext_nxv8i32_nxv8i64(<vscale x 8 x i32> %va) {
; CHECK-LABEL: vsext_nxv8i32_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vsext.vf2 v8, v16
; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: ret
%evec = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
ret <vscale x 8 x i64> %evec
}
define <vscale x 8 x i64> @vzext_nxv8i32_nxv8i64(<vscale x 8 x i32> %va) {
; CHECK-LABEL: vzext_nxv8i32_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vzext.vf2 v8, v16
; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: ret
%evec = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
ret <vscale x 8 x i64> %evec
}

llvm/test/CodeGen/RISCV/rvv/vexts-sdnode-rv64.ll

  • This file was added.
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x i16> @vsext_nxv1i8_nxv1i16(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vsext_nxv1i8_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vsext.vf2 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = sext <vscale x 1 x i8> %va to <vscale x 1 x i16>
ret <vscale x 1 x i16> %evec
}
define <vscale x 1 x i16> @vzext_nxv1i8_nxv1i16(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vzext_nxv1i8_nxv1i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf4,ta,mu
; CHECK-NEXT: vzext.vf2 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = zext <vscale x 1 x i8> %va to <vscale x 1 x i16>
ret <vscale x 1 x i16> %evec
}
define <vscale x 1 x i32> @vsext_nxv1i8_nxv1i32(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vsext_nxv1i8_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vsext.vf4 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = sext <vscale x 1 x i8> %va to <vscale x 1 x i32>
ret <vscale x 1 x i32> %evec
}
define <vscale x 1 x i32> @vzext_nxv1i8_nxv1i32(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vzext_nxv1i8_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vzext.vf4 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = zext <vscale x 1 x i8> %va to <vscale x 1 x i32>
ret <vscale x 1 x i32> %evec
}
define <vscale x 1 x i64> @vsext_nxv1i8_nxv1i64(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vsext_nxv1i8_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vsext.vf8 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = sext <vscale x 1 x i8> %va to <vscale x 1 x i64>
ret <vscale x 1 x i64> %evec
}
define <vscale x 1 x i64> @vzext_nxv1i8_nxv1i64(<vscale x 1 x i8> %va) {
; CHECK-LABEL: vzext_nxv1i8_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vzext.vf8 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = zext <vscale x 1 x i8> %va to <vscale x 1 x i64>
ret <vscale x 1 x i64> %evec
}
define <vscale x 2 x i16> @vsext_nxv2i8_nxv2i16(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vsext_nxv2i8_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vsext.vf2 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = sext <vscale x 2 x i8> %va to <vscale x 2 x i16>
ret <vscale x 2 x i16> %evec
}
define <vscale x 2 x i16> @vzext_nxv2i8_nxv2i16(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vzext_nxv2i8_nxv2i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,mf2,ta,mu
; CHECK-NEXT: vzext.vf2 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = zext <vscale x 2 x i8> %va to <vscale x 2 x i16>
ret <vscale x 2 x i16> %evec
}
define <vscale x 2 x i32> @vsext_nxv2i8_nxv2i32(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vsext_nxv2i8_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vsext.vf4 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = sext <vscale x 2 x i8> %va to <vscale x 2 x i32>
ret <vscale x 2 x i32> %evec
}
define <vscale x 2 x i32> @vzext_nxv2i8_nxv2i32(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vzext_nxv2i8_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vzext.vf4 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = zext <vscale x 2 x i8> %va to <vscale x 2 x i32>
ret <vscale x 2 x i32> %evec
}
define <vscale x 2 x i64> @vsext_nxv2i8_nxv2i64(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vsext_nxv2i8_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vsext.vf8 v26, v16
; CHECK-NEXT: vmv2r.v v16, v26
; CHECK-NEXT: ret
%evec = sext <vscale x 2 x i8> %va to <vscale x 2 x i64>
ret <vscale x 2 x i64> %evec
}
define <vscale x 2 x i64> @vzext_nxv2i8_nxv2i64(<vscale x 2 x i8> %va) {
; CHECK-LABEL: vzext_nxv2i8_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vzext.vf8 v26, v16
; CHECK-NEXT: vmv2r.v v16, v26
; CHECK-NEXT: ret
%evec = zext <vscale x 2 x i8> %va to <vscale x 2 x i64>
ret <vscale x 2 x i64> %evec
}
define <vscale x 4 x i16> @vsext_nxv4i8_nxv4i16(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vsext_nxv4i8_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vsext.vf2 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = sext <vscale x 4 x i8> %va to <vscale x 4 x i16>
ret <vscale x 4 x i16> %evec
}
define <vscale x 4 x i16> @vzext_nxv4i8_nxv4i16(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vzext_nxv4i8_nxv4i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m1,ta,mu
; CHECK-NEXT: vzext.vf2 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = zext <vscale x 4 x i8> %va to <vscale x 4 x i16>
ret <vscale x 4 x i16> %evec
}
define <vscale x 4 x i32> @vsext_nxv4i8_nxv4i32(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vsext_nxv4i8_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
; CHECK-NEXT: vsext.vf4 v26, v16
; CHECK-NEXT: vmv2r.v v16, v26
; CHECK-NEXT: ret
%evec = sext <vscale x 4 x i8> %va to <vscale x 4 x i32>
ret <vscale x 4 x i32> %evec
}
define <vscale x 4 x i32> @vzext_nxv4i8_nxv4i32(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vzext_nxv4i8_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
; CHECK-NEXT: vzext.vf4 v26, v16
; CHECK-NEXT: vmv2r.v v16, v26
; CHECK-NEXT: ret
%evec = zext <vscale x 4 x i8> %va to <vscale x 4 x i32>
ret <vscale x 4 x i32> %evec
}
define <vscale x 4 x i64> @vsext_nxv4i8_nxv4i64(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vsext_nxv4i8_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vsext.vf8 v28, v16
; CHECK-NEXT: vmv4r.v v16, v28
; CHECK-NEXT: ret
%evec = sext <vscale x 4 x i8> %va to <vscale x 4 x i64>
ret <vscale x 4 x i64> %evec
}
define <vscale x 4 x i64> @vzext_nxv4i8_nxv4i64(<vscale x 4 x i8> %va) {
; CHECK-LABEL: vzext_nxv4i8_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vzext.vf8 v28, v16
; CHECK-NEXT: vmv4r.v v16, v28
; CHECK-NEXT: ret
%evec = zext <vscale x 4 x i8> %va to <vscale x 4 x i64>
ret <vscale x 4 x i64> %evec
}
define <vscale x 8 x i16> @vsext_nxv8i8_nxv8i16(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vsext_nxv8i8_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vsext.vf2 v26, v16
; CHECK-NEXT: vmv2r.v v16, v26
; CHECK-NEXT: ret
%evec = sext <vscale x 8 x i8> %va to <vscale x 8 x i16>
ret <vscale x 8 x i16> %evec
}
define <vscale x 8 x i16> @vzext_nxv8i8_nxv8i16(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vzext_nxv8i8_nxv8i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m2,ta,mu
; CHECK-NEXT: vzext.vf2 v26, v16
; CHECK-NEXT: vmv2r.v v16, v26
; CHECK-NEXT: ret
%evec = zext <vscale x 8 x i8> %va to <vscale x 8 x i16>
ret <vscale x 8 x i16> %evec
}
define <vscale x 8 x i32> @vsext_nxv8i8_nxv8i32(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vsext_nxv8i8_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vsext.vf4 v28, v16
; CHECK-NEXT: vmv4r.v v16, v28
; CHECK-NEXT: ret
%evec = sext <vscale x 8 x i8> %va to <vscale x 8 x i32>
ret <vscale x 8 x i32> %evec
}
define <vscale x 8 x i32> @vzext_nxv8i8_nxv8i32(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vzext_nxv8i8_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vzext.vf4 v28, v16
; CHECK-NEXT: vmv4r.v v16, v28
; CHECK-NEXT: ret
%evec = zext <vscale x 8 x i8> %va to <vscale x 8 x i32>
ret <vscale x 8 x i32> %evec
}
define <vscale x 8 x i64> @vsext_nxv8i8_nxv8i64(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vsext_nxv8i8_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vsext.vf8 v8, v16
; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: ret
%evec = sext <vscale x 8 x i8> %va to <vscale x 8 x i64>
ret <vscale x 8 x i64> %evec
}
define <vscale x 8 x i64> @vzext_nxv8i8_nxv8i64(<vscale x 8 x i8> %va) {
; CHECK-LABEL: vzext_nxv8i8_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vzext.vf8 v8, v16
; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: ret
%evec = zext <vscale x 8 x i8> %va to <vscale x 8 x i64>
ret <vscale x 8 x i64> %evec
}
define <vscale x 16 x i16> @vsext_nxv16i8_nxv16i16(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vsext_nxv16i8_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vsext.vf2 v28, v16
; CHECK-NEXT: vmv4r.v v16, v28
; CHECK-NEXT: ret
%evec = sext <vscale x 16 x i8> %va to <vscale x 16 x i16>
ret <vscale x 16 x i16> %evec
}
define <vscale x 16 x i16> @vzext_nxv16i8_nxv16i16(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vzext_nxv16i8_nxv16i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m4,ta,mu
; CHECK-NEXT: vzext.vf2 v28, v16
; CHECK-NEXT: vmv4r.v v16, v28
; CHECK-NEXT: ret
%evec = zext <vscale x 16 x i8> %va to <vscale x 16 x i16>
ret <vscale x 16 x i16> %evec
}
define <vscale x 16 x i32> @vsext_nxv16i8_nxv16i32(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vsext_nxv16i8_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
; CHECK-NEXT: vsext.vf4 v8, v16
; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: ret
%evec = sext <vscale x 16 x i8> %va to <vscale x 16 x i32>
ret <vscale x 16 x i32> %evec
}
define <vscale x 16 x i32> @vzext_nxv16i8_nxv16i32(<vscale x 16 x i8> %va) {
; CHECK-LABEL: vzext_nxv16i8_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
; CHECK-NEXT: vzext.vf4 v8, v16
; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: ret
%evec = zext <vscale x 16 x i8> %va to <vscale x 16 x i32>
ret <vscale x 16 x i32> %evec
}
define <vscale x 32 x i16> @vsext_nxv32i8_nxv32i16(<vscale x 32 x i8> %va) {
; CHECK-LABEL: vsext_nxv32i8_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vsext.vf2 v8, v16
; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: ret
%evec = sext <vscale x 32 x i8> %va to <vscale x 32 x i16>
ret <vscale x 32 x i16> %evec
}
define <vscale x 32 x i16> @vzext_nxv32i8_nxv32i16(<vscale x 32 x i8> %va) {
; CHECK-LABEL: vzext_nxv32i8_nxv32i16:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e16,m8,ta,mu
; CHECK-NEXT: vzext.vf2 v8, v16
; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: ret
%evec = zext <vscale x 32 x i8> %va to <vscale x 32 x i16>
ret <vscale x 32 x i16> %evec
}
define <vscale x 1 x i32> @vsext_nxv1i16_nxv1i32(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vsext_nxv1i16_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vsext.vf2 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = sext <vscale x 1 x i16> %va to <vscale x 1 x i32>
ret <vscale x 1 x i32> %evec
}
define <vscale x 1 x i32> @vzext_nxv1i16_nxv1i32(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vzext_nxv1i16_nxv1i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,mf2,ta,mu
; CHECK-NEXT: vzext.vf2 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = zext <vscale x 1 x i16> %va to <vscale x 1 x i32>
ret <vscale x 1 x i32> %evec
}
define <vscale x 1 x i64> @vsext_nxv1i16_nxv1i64(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vsext_nxv1i16_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vsext.vf4 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = sext <vscale x 1 x i16> %va to <vscale x 1 x i64>
ret <vscale x 1 x i64> %evec
}
define <vscale x 1 x i64> @vzext_nxv1i16_nxv1i64(<vscale x 1 x i16> %va) {
; CHECK-LABEL: vzext_nxv1i16_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vzext.vf4 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = zext <vscale x 1 x i16> %va to <vscale x 1 x i64>
ret <vscale x 1 x i64> %evec
}
define <vscale x 2 x i32> @vsext_nxv2i16_nxv2i32(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vsext_nxv2i16_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vsext.vf2 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = sext <vscale x 2 x i16> %va to <vscale x 2 x i32>
ret <vscale x 2 x i32> %evec
}
define <vscale x 2 x i32> @vzext_nxv2i16_nxv2i32(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vzext_nxv2i16_nxv2i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m1,ta,mu
; CHECK-NEXT: vzext.vf2 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = zext <vscale x 2 x i16> %va to <vscale x 2 x i32>
ret <vscale x 2 x i32> %evec
}
define <vscale x 2 x i64> @vsext_nxv2i16_nxv2i64(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vsext_nxv2i16_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vsext.vf4 v26, v16
; CHECK-NEXT: vmv2r.v v16, v26
; CHECK-NEXT: ret
%evec = sext <vscale x 2 x i16> %va to <vscale x 2 x i64>
ret <vscale x 2 x i64> %evec
}
define <vscale x 2 x i64> @vzext_nxv2i16_nxv2i64(<vscale x 2 x i16> %va) {
; CHECK-LABEL: vzext_nxv2i16_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vzext.vf4 v26, v16
; CHECK-NEXT: vmv2r.v v16, v26
; CHECK-NEXT: ret
%evec = zext <vscale x 2 x i16> %va to <vscale x 2 x i64>
ret <vscale x 2 x i64> %evec
}
define <vscale x 4 x i32> @vsext_nxv4i16_nxv4i32(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vsext_nxv4i16_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
; CHECK-NEXT: vsext.vf2 v26, v16
; CHECK-NEXT: vmv2r.v v16, v26
; CHECK-NEXT: ret
%evec = sext <vscale x 4 x i16> %va to <vscale x 4 x i32>
ret <vscale x 4 x i32> %evec
}
define <vscale x 4 x i32> @vzext_nxv4i16_nxv4i32(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vzext_nxv4i16_nxv4i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m2,ta,mu
; CHECK-NEXT: vzext.vf2 v26, v16
; CHECK-NEXT: vmv2r.v v16, v26
; CHECK-NEXT: ret
%evec = zext <vscale x 4 x i16> %va to <vscale x 4 x i32>
ret <vscale x 4 x i32> %evec
}
define <vscale x 4 x i64> @vsext_nxv4i16_nxv4i64(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vsext_nxv4i16_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vsext.vf4 v28, v16
; CHECK-NEXT: vmv4r.v v16, v28
; CHECK-NEXT: ret
%evec = sext <vscale x 4 x i16> %va to <vscale x 4 x i64>
ret <vscale x 4 x i64> %evec
}
define <vscale x 4 x i64> @vzext_nxv4i16_nxv4i64(<vscale x 4 x i16> %va) {
; CHECK-LABEL: vzext_nxv4i16_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vzext.vf4 v28, v16
; CHECK-NEXT: vmv4r.v v16, v28
; CHECK-NEXT: ret
%evec = zext <vscale x 4 x i16> %va to <vscale x 4 x i64>
ret <vscale x 4 x i64> %evec
}
define <vscale x 8 x i32> @vsext_nxv8i16_nxv8i32(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vsext_nxv8i16_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vsext.vf2 v28, v16
; CHECK-NEXT: vmv4r.v v16, v28
; CHECK-NEXT: ret
%evec = sext <vscale x 8 x i16> %va to <vscale x 8 x i32>
ret <vscale x 8 x i32> %evec
}
define <vscale x 8 x i32> @vzext_nxv8i16_nxv8i32(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vzext_nxv8i16_nxv8i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m4,ta,mu
; CHECK-NEXT: vzext.vf2 v28, v16
; CHECK-NEXT: vmv4r.v v16, v28
; CHECK-NEXT: ret
%evec = zext <vscale x 8 x i16> %va to <vscale x 8 x i32>
ret <vscale x 8 x i32> %evec
}
define <vscale x 8 x i64> @vsext_nxv8i16_nxv8i64(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vsext_nxv8i16_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vsext.vf4 v8, v16
; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: ret
%evec = sext <vscale x 8 x i16> %va to <vscale x 8 x i64>
ret <vscale x 8 x i64> %evec
}
define <vscale x 8 x i64> @vzext_nxv8i16_nxv8i64(<vscale x 8 x i16> %va) {
; CHECK-LABEL: vzext_nxv8i16_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vzext.vf4 v8, v16
; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: ret
%evec = zext <vscale x 8 x i16> %va to <vscale x 8 x i64>
ret <vscale x 8 x i64> %evec
}
define <vscale x 16 x i32> @vsext_nxv16i16_nxv16i32(<vscale x 16 x i16> %va) {
; CHECK-LABEL: vsext_nxv16i16_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
; CHECK-NEXT: vsext.vf2 v8, v16
; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: ret
%evec = sext <vscale x 16 x i16> %va to <vscale x 16 x i32>
ret <vscale x 16 x i32> %evec
}
define <vscale x 16 x i32> @vzext_nxv16i16_nxv16i32(<vscale x 16 x i16> %va) {
; CHECK-LABEL: vzext_nxv16i16_nxv16i32:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e32,m8,ta,mu
; CHECK-NEXT: vzext.vf2 v8, v16
; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: ret
%evec = zext <vscale x 16 x i16> %va to <vscale x 16 x i32>
ret <vscale x 16 x i32> %evec
}
define <vscale x 1 x i64> @vsext_nxv1i32_nxv1i64(<vscale x 1 x i32> %va) {
; CHECK-LABEL: vsext_nxv1i32_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vsext.vf2 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = sext <vscale x 1 x i32> %va to <vscale x 1 x i64>
ret <vscale x 1 x i64> %evec
}
define <vscale x 1 x i64> @vzext_nxv1i32_nxv1i64(<vscale x 1 x i32> %va) {
; CHECK-LABEL: vzext_nxv1i32_nxv1i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m1,ta,mu
; CHECK-NEXT: vzext.vf2 v25, v16
; CHECK-NEXT: vmv1r.v v16, v25
; CHECK-NEXT: ret
%evec = zext <vscale x 1 x i32> %va to <vscale x 1 x i64>
ret <vscale x 1 x i64> %evec
}
define <vscale x 2 x i64> @vsext_nxv2i32_nxv2i64(<vscale x 2 x i32> %va) {
; CHECK-LABEL: vsext_nxv2i32_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vsext.vf2 v26, v16
; CHECK-NEXT: vmv2r.v v16, v26
; CHECK-NEXT: ret
%evec = sext <vscale x 2 x i32> %va to <vscale x 2 x i64>
ret <vscale x 2 x i64> %evec
}
define <vscale x 2 x i64> @vzext_nxv2i32_nxv2i64(<vscale x 2 x i32> %va) {
; CHECK-LABEL: vzext_nxv2i32_nxv2i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m2,ta,mu
; CHECK-NEXT: vzext.vf2 v26, v16
; CHECK-NEXT: vmv2r.v v16, v26
; CHECK-NEXT: ret
%evec = zext <vscale x 2 x i32> %va to <vscale x 2 x i64>
ret <vscale x 2 x i64> %evec
}
define <vscale x 4 x i64> @vsext_nxv4i32_nxv4i64(<vscale x 4 x i32> %va) {
; CHECK-LABEL: vsext_nxv4i32_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vsext.vf2 v28, v16
; CHECK-NEXT: vmv4r.v v16, v28
; CHECK-NEXT: ret
%evec = sext <vscale x 4 x i32> %va to <vscale x 4 x i64>
ret <vscale x 4 x i64> %evec
}
define <vscale x 4 x i64> @vzext_nxv4i32_nxv4i64(<vscale x 4 x i32> %va) {
; CHECK-LABEL: vzext_nxv4i32_nxv4i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m4,ta,mu
; CHECK-NEXT: vzext.vf2 v28, v16
; CHECK-NEXT: vmv4r.v v16, v28
; CHECK-NEXT: ret
%evec = zext <vscale x 4 x i32> %va to <vscale x 4 x i64>
ret <vscale x 4 x i64> %evec
}
define <vscale x 8 x i64> @vsext_nxv8i32_nxv8i64(<vscale x 8 x i32> %va) {
; CHECK-LABEL: vsext_nxv8i32_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vsext.vf2 v8, v16
; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: ret
%evec = sext <vscale x 8 x i32> %va to <vscale x 8 x i64>
ret <vscale x 8 x i64> %evec
}
define <vscale x 8 x i64> @vzext_nxv8i32_nxv8i64(<vscale x 8 x i32> %va) {
; CHECK-LABEL: vzext_nxv8i32_nxv8i64:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetvli a0, zero, e64,m8,ta,mu
; CHECK-NEXT: vzext.vf2 v8, v16
; CHECK-NEXT: vmv8r.v v16, v8
; CHECK-NEXT: ret
%evec = zext <vscale x 8 x i32> %va to <vscale x 8 x i64>
ret <vscale x 8 x i64> %evec
}