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Differential D94535

[RISCV] Optimize Branch Comparisons
ClosedPublic

Authored by lenary on Jan 12 2021, 11:22 AM.

Details

Reviewers
luismarques
craig.topper
mundaym
asb
Commits
rG141e45b99ca0: [RISCV] Optimize Branch Comparisons
Summary

I noticed in D94450 that there were quite a few places where we generate
the sequence:

xN <- comparison ...
xN <- xor xN, 1
bnez xN, symbol

Given we know the XOR will be used by BRCOND, which only looks at the lowest
bit, I think we can remove the XOR and just invert the branch condition in
these cases?

The case mostly seems to come up in floating point tests, where there is often
more logic to combine the results of multiple SETCCs, rather than a single
(BRCOND (SETCC ...) ...).

Diff Detail

Event Timeline

lenary created this revision.Jan 12 2021, 11:22 AM
Herald added subscribers: frasercrmck, NickHung, evandro and 24 others. · View Herald TranscriptJan 12 2021, 11:22 AM
lenary requested review of this revision.Jan 12 2021, 11:22 AM
Herald added a project: Restricted Project. · View Herald TranscriptJan 12 2021, 11:22 AM
Herald added subscribers: llvm-commits, MaskRay. · View Herald Transcript
jrtc27 added inline comments.Jan 12 2021, 11:44 AM
llvm/lib/Target/RISCV/RISCVInstrInfo.td
969

Needs to be plural now

972

Hmm, it's a shame not is an alias for (xor $arg, -1).

Harbormaster completed remote builds in B84884: Diff 316171.Jan 12 2021, 11:58 AM
lenary mentioned this in D94546: [RISCV] Optimize select_cc after fp compare expansion.Jan 12 2021, 12:52 PM
lenary updated this revision to Diff 316236.Jan 12 2021, 2:11 PM
  • Add comments in line with review feedback.
lenary marked 2 inline comments as done.Jan 12 2021, 2:11 PM
lenary added inline comments.
llvm/lib/Target/RISCV/RISCVInstrInfo.td
972

Yeah, this importantly is boolean not, rather than bitwise not.

Harbormaster completed remote builds in B84920: Diff 316236.Jan 12 2021, 2:51 PM
craig.topper accepted this revision.Jan 14 2021, 1:42 PM

LGTM

This revision is now accepted and ready to land.Jan 14 2021, 1:42 PM
Closed by commit rG141e45b99ca0: [RISCV] Optimize Branch Comparisons (authored by lenary). · Explain WhyJan 15 2021, 3:29 AM
This revision was automatically updated to reflect the committed changes.
lenary added a commit: rG141e45b99ca0: [RISCV] Optimize Branch Comparisons.

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
2 lines
test/
CodeGen/
RISCV/
36 lines
36 lines
36 lines

Diff 316171

llvm/lib/Target/RISCV/RISCVInstrInfo.td

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// Condition codes that don't have matching RISC-V branch instructions, but // Condition codes that don't have matching RISC-V branch instructions, but
// are trivially supported by swapping the two input operands // are trivially supported by swapping the two input operands
def : BccSwapPat<setgt, BLT>; def : BccSwapPat<setgt, BLT>;
def : BccSwapPat<setle, BGE>; def : BccSwapPat<setle, BGE>;
def : BccSwapPat<setugt, BLTU>; def : BccSwapPat<setugt, BLTU>;
def : BccSwapPat<setule, BGEU>; def : BccSwapPat<setule, BGEU>;
// An extra pattern is needed for a brcond without a setcc (i.e. where the // An extra pattern is needed for a brcond without a setcc (i.e. where the
jrtc27Unsubmitted
Done
ReplyInline Actions

Needs to be plural now

jrtc27: Needs to be plural now
// condition was calculated elsewhere). // condition was calculated elsewhere).
def : Pat<(brcond GPR:$cond, bb:$imm12), (BNE GPR:$cond, X0, bb:$imm12)>; def : Pat<(brcond GPR:$cond, bb:$imm12), (BNE GPR:$cond, X0, bb:$imm12)>;
def : Pat<(brcond (XLenVT (xor GPR:$cond, 1)), bb:$imm12),
jrtc27Unsubmitted
Not Done
ReplyInline Actions

Hmm, it's a shame not is an alias for (xor $arg, -1).

jrtc27: Hmm, it's a shame `not` is an alias for `(xor $arg, -1)`.
lenaryAuthorUnsubmitted
Done
ReplyInline Actions

Yeah, this importantly is boolean not, rather than bitwise not.

lenary: Yeah, this importantly is boolean not, rather than bitwise not.
(BEQ GPR:$cond, X0, bb:$imm12)>;
let isBarrier = 1, isBranch = 1, isTerminator = 1 in let isBarrier = 1, isBranch = 1, isTerminator = 1 in
def PseudoBR : Pseudo<(outs), (ins simm21_lsb0_jal:$imm20), [(br bb:$imm20)]>, def PseudoBR : Pseudo<(outs), (ins simm21_lsb0_jal:$imm20), [(br bb:$imm20)]>,
PseudoInstExpansion<(JAL X0, simm21_lsb0_jal:$imm20)>; PseudoInstExpansion<(JAL X0, simm21_lsb0_jal:$imm20)>;
let isBarrier = 1, isBranch = 1, isIndirectBranch = 1, isTerminator = 1 in let isBarrier = 1, isBranch = 1, isIndirectBranch = 1, isTerminator = 1 in
def PseudoBRIND : Pseudo<(outs), (ins GPR:$rs1, simm12:$imm12), []>, def PseudoBRIND : Pseudo<(outs), (ins GPR:$rs1, simm12:$imm12), []>,
PseudoInstExpansion<(JALR X0, GPR:$rs1, simm12:$imm12)>; PseudoInstExpansion<(JALR X0, GPR:$rs1, simm12:$imm12)>;
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llvm/test/CodeGen/RISCV/double-br-fcmp.ll

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; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a2, 0(sp) ; RV32IFD-NEXT: sw a2, 0(sp)
; RV32IFD-NEXT: sw a3, 4(sp) ; RV32IFD-NEXT: sw a3, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp) ; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft1, 0(sp) ; RV32IFD-NEXT: fld ft1, 0(sp)
; RV32IFD-NEXT: feq.d a0, ft1, ft0 ; RV32IFD-NEXT: feq.d a0, ft1, ft0
; RV32IFD-NEXT: xori a0, a0, 1 ; RV32IFD-NEXT: bnez a0, .LBB2_2
; RV32IFD-NEXT: beqz a0, .LBB2_2
; RV32IFD-NEXT: # %bb.1: # %if.else ; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB2_2: # %if.then ; RV32IFD-NEXT: .LBB2_2: # %if.then
; RV32IFD-NEXT: call abort@plt ; RV32IFD-NEXT: call abort@plt
; ;
; RV64IFD-LABEL: br_fcmp_oeq_alt: ; RV64IFD-LABEL: br_fcmp_oeq_alt:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d.x ft0, a1 ; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0 ; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: feq.d a0, ft1, ft0 ; RV64IFD-NEXT: feq.d a0, ft1, ft0
; RV64IFD-NEXT: xori a0, a0, 1 ; RV64IFD-NEXT: bnez a0, .LBB2_2
; RV64IFD-NEXT: beqz a0, .LBB2_2
; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB2_2: # %if.then ; RV64IFD-NEXT: .LBB2_2: # %if.then
; RV64IFD-NEXT: call abort@plt ; RV64IFD-NEXT: call abort@plt
%1 = fcmp oeq double %a, %b %1 = fcmp oeq double %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
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; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a2, 0(sp) ; RV32IFD-NEXT: sw a2, 0(sp)
; RV32IFD-NEXT: sw a3, 4(sp) ; RV32IFD-NEXT: sw a3, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp) ; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft1, 0(sp) ; RV32IFD-NEXT: fld ft1, 0(sp)
; RV32IFD-NEXT: fle.d a0, ft1, ft0 ; RV32IFD-NEXT: fle.d a0, ft1, ft0
; RV32IFD-NEXT: xori a0, a0, 1 ; RV32IFD-NEXT: beqz a0, .LBB10_2
; RV32IFD-NEXT: bnez a0, .LBB10_2
; RV32IFD-NEXT: # %bb.1: # %if.else ; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB10_2: # %if.then ; RV32IFD-NEXT: .LBB10_2: # %if.then
; RV32IFD-NEXT: call abort@plt ; RV32IFD-NEXT: call abort@plt
; ;
; RV64IFD-LABEL: br_fcmp_ugt: ; RV64IFD-LABEL: br_fcmp_ugt:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d.x ft0, a1 ; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0 ; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: fle.d a0, ft1, ft0 ; RV64IFD-NEXT: fle.d a0, ft1, ft0
; RV64IFD-NEXT: xori a0, a0, 1 ; RV64IFD-NEXT: beqz a0, .LBB10_2
; RV64IFD-NEXT: bnez a0, .LBB10_2
; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB10_2: # %if.then ; RV64IFD-NEXT: .LBB10_2: # %if.then
; RV64IFD-NEXT: call abort@plt ; RV64IFD-NEXT: call abort@plt
%1 = fcmp ugt double %a, %b %1 = fcmp ugt double %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
Show All 11 Lines
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a2, 0(sp) ; RV32IFD-NEXT: sw a2, 0(sp)
; RV32IFD-NEXT: sw a3, 4(sp) ; RV32IFD-NEXT: sw a3, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp) ; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft1, 0(sp) ; RV32IFD-NEXT: fld ft1, 0(sp)
; RV32IFD-NEXT: flt.d a0, ft1, ft0 ; RV32IFD-NEXT: flt.d a0, ft1, ft0
; RV32IFD-NEXT: xori a0, a0, 1 ; RV32IFD-NEXT: beqz a0, .LBB11_2
; RV32IFD-NEXT: bnez a0, .LBB11_2
; RV32IFD-NEXT: # %bb.1: # %if.else ; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB11_2: # %if.then ; RV32IFD-NEXT: .LBB11_2: # %if.then
; RV32IFD-NEXT: call abort@plt ; RV32IFD-NEXT: call abort@plt
; ;
; RV64IFD-LABEL: br_fcmp_uge: ; RV64IFD-LABEL: br_fcmp_uge:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d.x ft0, a1 ; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0 ; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: flt.d a0, ft1, ft0 ; RV64IFD-NEXT: flt.d a0, ft1, ft0
; RV64IFD-NEXT: xori a0, a0, 1 ; RV64IFD-NEXT: beqz a0, .LBB11_2
; RV64IFD-NEXT: bnez a0, .LBB11_2
; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB11_2: # %if.then ; RV64IFD-NEXT: .LBB11_2: # %if.then
; RV64IFD-NEXT: call abort@plt ; RV64IFD-NEXT: call abort@plt
%1 = fcmp uge double %a, %b %1 = fcmp uge double %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
Show All 11 Lines
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp) ; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: sw a2, 0(sp) ; RV32IFD-NEXT: sw a2, 0(sp)
; RV32IFD-NEXT: sw a3, 4(sp) ; RV32IFD-NEXT: sw a3, 4(sp)
; RV32IFD-NEXT: fld ft1, 0(sp) ; RV32IFD-NEXT: fld ft1, 0(sp)
; RV32IFD-NEXT: fle.d a0, ft1, ft0 ; RV32IFD-NEXT: fle.d a0, ft1, ft0
; RV32IFD-NEXT: xori a0, a0, 1 ; RV32IFD-NEXT: beqz a0, .LBB12_2
; RV32IFD-NEXT: bnez a0, .LBB12_2
; RV32IFD-NEXT: # %bb.1: # %if.else ; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB12_2: # %if.then ; RV32IFD-NEXT: .LBB12_2: # %if.then
; RV32IFD-NEXT: call abort@plt ; RV32IFD-NEXT: call abort@plt
; ;
; RV64IFD-LABEL: br_fcmp_ult: ; RV64IFD-LABEL: br_fcmp_ult:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fmv.d.x ft1, a1 ; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: fle.d a0, ft1, ft0 ; RV64IFD-NEXT: fle.d a0, ft1, ft0
; RV64IFD-NEXT: xori a0, a0, 1 ; RV64IFD-NEXT: beqz a0, .LBB12_2
; RV64IFD-NEXT: bnez a0, .LBB12_2
; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB12_2: # %if.then ; RV64IFD-NEXT: .LBB12_2: # %if.then
; RV64IFD-NEXT: call abort@plt ; RV64IFD-NEXT: call abort@plt
%1 = fcmp ult double %a, %b %1 = fcmp ult double %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
Show All 11 Lines
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp) ; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: sw a2, 0(sp) ; RV32IFD-NEXT: sw a2, 0(sp)
; RV32IFD-NEXT: sw a3, 4(sp) ; RV32IFD-NEXT: sw a3, 4(sp)
; RV32IFD-NEXT: fld ft1, 0(sp) ; RV32IFD-NEXT: fld ft1, 0(sp)
; RV32IFD-NEXT: flt.d a0, ft1, ft0 ; RV32IFD-NEXT: flt.d a0, ft1, ft0
; RV32IFD-NEXT: xori a0, a0, 1 ; RV32IFD-NEXT: beqz a0, .LBB13_2
; RV32IFD-NEXT: bnez a0, .LBB13_2
; RV32IFD-NEXT: # %bb.1: # %if.else ; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB13_2: # %if.then ; RV32IFD-NEXT: .LBB13_2: # %if.then
; RV32IFD-NEXT: call abort@plt ; RV32IFD-NEXT: call abort@plt
; ;
; RV64IFD-LABEL: br_fcmp_ule: ; RV64IFD-LABEL: br_fcmp_ule:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d.x ft0, a0 ; RV64IFD-NEXT: fmv.d.x ft0, a0
; RV64IFD-NEXT: fmv.d.x ft1, a1 ; RV64IFD-NEXT: fmv.d.x ft1, a1
; RV64IFD-NEXT: flt.d a0, ft1, ft0 ; RV64IFD-NEXT: flt.d a0, ft1, ft0
; RV64IFD-NEXT: xori a0, a0, 1 ; RV64IFD-NEXT: beqz a0, .LBB13_2
; RV64IFD-NEXT: bnez a0, .LBB13_2
; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB13_2: # %if.then ; RV64IFD-NEXT: .LBB13_2: # %if.then
; RV64IFD-NEXT: call abort@plt ; RV64IFD-NEXT: call abort@plt
%1 = fcmp ule double %a, %b %1 = fcmp ule double %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
Show All 11 Lines
; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IFD-NEXT: sw a2, 0(sp) ; RV32IFD-NEXT: sw a2, 0(sp)
; RV32IFD-NEXT: sw a3, 4(sp) ; RV32IFD-NEXT: sw a3, 4(sp)
; RV32IFD-NEXT: fld ft0, 0(sp) ; RV32IFD-NEXT: fld ft0, 0(sp)
; RV32IFD-NEXT: sw a0, 0(sp) ; RV32IFD-NEXT: sw a0, 0(sp)
; RV32IFD-NEXT: sw a1, 4(sp) ; RV32IFD-NEXT: sw a1, 4(sp)
; RV32IFD-NEXT: fld ft1, 0(sp) ; RV32IFD-NEXT: fld ft1, 0(sp)
; RV32IFD-NEXT: feq.d a0, ft1, ft0 ; RV32IFD-NEXT: feq.d a0, ft1, ft0
; RV32IFD-NEXT: xori a0, a0, 1 ; RV32IFD-NEXT: beqz a0, .LBB14_2
; RV32IFD-NEXT: bnez a0, .LBB14_2
; RV32IFD-NEXT: # %bb.1: # %if.else ; RV32IFD-NEXT: # %bb.1: # %if.else
; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: addi sp, sp, 16
; RV32IFD-NEXT: ret ; RV32IFD-NEXT: ret
; RV32IFD-NEXT: .LBB14_2: # %if.then ; RV32IFD-NEXT: .LBB14_2: # %if.then
; RV32IFD-NEXT: call abort@plt ; RV32IFD-NEXT: call abort@plt
; ;
; RV64IFD-LABEL: br_fcmp_une: ; RV64IFD-LABEL: br_fcmp_une:
; RV64IFD: # %bb.0: ; RV64IFD: # %bb.0:
; RV64IFD-NEXT: addi sp, sp, -16 ; RV64IFD-NEXT: addi sp, sp, -16
; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IFD-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IFD-NEXT: fmv.d.x ft0, a1 ; RV64IFD-NEXT: fmv.d.x ft0, a1
; RV64IFD-NEXT: fmv.d.x ft1, a0 ; RV64IFD-NEXT: fmv.d.x ft1, a0
; RV64IFD-NEXT: feq.d a0, ft1, ft0 ; RV64IFD-NEXT: feq.d a0, ft1, ft0
; RV64IFD-NEXT: xori a0, a0, 1 ; RV64IFD-NEXT: beqz a0, .LBB14_2
; RV64IFD-NEXT: bnez a0, .LBB14_2
; RV64IFD-NEXT: # %bb.1: # %if.else ; RV64IFD-NEXT: # %bb.1: # %if.else
; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IFD-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IFD-NEXT: addi sp, sp, 16 ; RV64IFD-NEXT: addi sp, sp, 16
; RV64IFD-NEXT: ret ; RV64IFD-NEXT: ret
; RV64IFD-NEXT: .LBB14_2: # %if.then ; RV64IFD-NEXT: .LBB14_2: # %if.then
; RV64IFD-NEXT: call abort@plt ; RV64IFD-NEXT: call abort@plt
%1 = fcmp une double %a, %b %1 = fcmp une double %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
▲ Show 20 Lines • Show All 91 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/float-br-fcmp.ll

Show First 20 Lines • Show All 87 Lines • ▼ Show 20 Lines
define void @br_fcmp_oeq_alt(float %a, float %b) nounwind { define void @br_fcmp_oeq_alt(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_oeq_alt: ; RV32IF-LABEL: br_fcmp_oeq_alt:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.w.x ft0, a1 ; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: fmv.w.x ft1, a0 ; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: feq.s a0, ft1, ft0 ; RV32IF-NEXT: feq.s a0, ft1, ft0
; RV32IF-NEXT: xori a0, a0, 1 ; RV32IF-NEXT: bnez a0, .LBB2_2
; RV32IF-NEXT: beqz a0, .LBB2_2
; RV32IF-NEXT: # %bb.1: # %if.else ; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB2_2: # %if.then ; RV32IF-NEXT: .LBB2_2: # %if.then
; RV32IF-NEXT: call abort@plt ; RV32IF-NEXT: call abort@plt
; ;
; RV64IF-LABEL: br_fcmp_oeq_alt: ; RV64IF-LABEL: br_fcmp_oeq_alt:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: fmv.w.x ft0, a1 ; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: fmv.w.x ft1, a0 ; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: feq.s a0, ft1, ft0 ; RV64IF-NEXT: feq.s a0, ft1, ft0
; RV64IF-NEXT: xori a0, a0, 1 ; RV64IF-NEXT: bnez a0, .LBB2_2
; RV64IF-NEXT: beqz a0, .LBB2_2
; RV64IF-NEXT: # %bb.1: # %if.else ; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB2_2: # %if.then ; RV64IF-NEXT: .LBB2_2: # %if.then
; RV64IF-NEXT: call abort@plt ; RV64IF-NEXT: call abort@plt
%1 = fcmp oeq float %a, %b %1 = fcmp oeq float %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
▲ Show 20 Lines • Show All 294 Lines • ▼ Show 20 Lines
define void @br_fcmp_ugt(float %a, float %b) nounwind { define void @br_fcmp_ugt(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_ugt: ; RV32IF-LABEL: br_fcmp_ugt:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.w.x ft0, a1 ; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: fmv.w.x ft1, a0 ; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: fle.s a0, ft1, ft0 ; RV32IF-NEXT: fle.s a0, ft1, ft0
; RV32IF-NEXT: xori a0, a0, 1 ; RV32IF-NEXT: beqz a0, .LBB10_2
; RV32IF-NEXT: bnez a0, .LBB10_2
; RV32IF-NEXT: # %bb.1: # %if.else ; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB10_2: # %if.then ; RV32IF-NEXT: .LBB10_2: # %if.then
; RV32IF-NEXT: call abort@plt ; RV32IF-NEXT: call abort@plt
; ;
; RV64IF-LABEL: br_fcmp_ugt: ; RV64IF-LABEL: br_fcmp_ugt:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: fmv.w.x ft0, a1 ; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: fmv.w.x ft1, a0 ; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: fle.s a0, ft1, ft0 ; RV64IF-NEXT: fle.s a0, ft1, ft0
; RV64IF-NEXT: xori a0, a0, 1 ; RV64IF-NEXT: beqz a0, .LBB10_2
; RV64IF-NEXT: bnez a0, .LBB10_2
; RV64IF-NEXT: # %bb.1: # %if.else ; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB10_2: # %if.then ; RV64IF-NEXT: .LBB10_2: # %if.then
; RV64IF-NEXT: call abort@plt ; RV64IF-NEXT: call abort@plt
%1 = fcmp ugt float %a, %b %1 = fcmp ugt float %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_uge(float %a, float %b) nounwind { define void @br_fcmp_uge(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_uge: ; RV32IF-LABEL: br_fcmp_uge:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.w.x ft0, a1 ; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: fmv.w.x ft1, a0 ; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: flt.s a0, ft1, ft0 ; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: xori a0, a0, 1 ; RV32IF-NEXT: beqz a0, .LBB11_2
; RV32IF-NEXT: bnez a0, .LBB11_2
; RV32IF-NEXT: # %bb.1: # %if.else ; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB11_2: # %if.then ; RV32IF-NEXT: .LBB11_2: # %if.then
; RV32IF-NEXT: call abort@plt ; RV32IF-NEXT: call abort@plt
; ;
; RV64IF-LABEL: br_fcmp_uge: ; RV64IF-LABEL: br_fcmp_uge:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: fmv.w.x ft0, a1 ; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: fmv.w.x ft1, a0 ; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: flt.s a0, ft1, ft0 ; RV64IF-NEXT: flt.s a0, ft1, ft0
; RV64IF-NEXT: xori a0, a0, 1 ; RV64IF-NEXT: beqz a0, .LBB11_2
; RV64IF-NEXT: bnez a0, .LBB11_2
; RV64IF-NEXT: # %bb.1: # %if.else ; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB11_2: # %if.then ; RV64IF-NEXT: .LBB11_2: # %if.then
; RV64IF-NEXT: call abort@plt ; RV64IF-NEXT: call abort@plt
%1 = fcmp uge float %a, %b %1 = fcmp uge float %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_ult(float %a, float %b) nounwind { define void @br_fcmp_ult(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_ult: ; RV32IF-LABEL: br_fcmp_ult:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fmv.w.x ft1, a1 ; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: fle.s a0, ft1, ft0 ; RV32IF-NEXT: fle.s a0, ft1, ft0
; RV32IF-NEXT: xori a0, a0, 1 ; RV32IF-NEXT: beqz a0, .LBB12_2
; RV32IF-NEXT: bnez a0, .LBB12_2
; RV32IF-NEXT: # %bb.1: # %if.else ; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB12_2: # %if.then ; RV32IF-NEXT: .LBB12_2: # %if.then
; RV32IF-NEXT: call abort@plt ; RV32IF-NEXT: call abort@plt
; ;
; RV64IF-LABEL: br_fcmp_ult: ; RV64IF-LABEL: br_fcmp_ult:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fmv.w.x ft1, a1 ; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: fle.s a0, ft1, ft0 ; RV64IF-NEXT: fle.s a0, ft1, ft0
; RV64IF-NEXT: xori a0, a0, 1 ; RV64IF-NEXT: beqz a0, .LBB12_2
; RV64IF-NEXT: bnez a0, .LBB12_2
; RV64IF-NEXT: # %bb.1: # %if.else ; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB12_2: # %if.then ; RV64IF-NEXT: .LBB12_2: # %if.then
; RV64IF-NEXT: call abort@plt ; RV64IF-NEXT: call abort@plt
%1 = fcmp ult float %a, %b %1 = fcmp ult float %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_ule(float %a, float %b) nounwind { define void @br_fcmp_ule(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_ule: ; RV32IF-LABEL: br_fcmp_ule:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.w.x ft0, a0 ; RV32IF-NEXT: fmv.w.x ft0, a0
; RV32IF-NEXT: fmv.w.x ft1, a1 ; RV32IF-NEXT: fmv.w.x ft1, a1
; RV32IF-NEXT: flt.s a0, ft1, ft0 ; RV32IF-NEXT: flt.s a0, ft1, ft0
; RV32IF-NEXT: xori a0, a0, 1 ; RV32IF-NEXT: beqz a0, .LBB13_2
; RV32IF-NEXT: bnez a0, .LBB13_2
; RV32IF-NEXT: # %bb.1: # %if.else ; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB13_2: # %if.then ; RV32IF-NEXT: .LBB13_2: # %if.then
; RV32IF-NEXT: call abort@plt ; RV32IF-NEXT: call abort@plt
; ;
; RV64IF-LABEL: br_fcmp_ule: ; RV64IF-LABEL: br_fcmp_ule:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: fmv.w.x ft0, a0 ; RV64IF-NEXT: fmv.w.x ft0, a0
; RV64IF-NEXT: fmv.w.x ft1, a1 ; RV64IF-NEXT: fmv.w.x ft1, a1
; RV64IF-NEXT: flt.s a0, ft1, ft0 ; RV64IF-NEXT: flt.s a0, ft1, ft0
; RV64IF-NEXT: xori a0, a0, 1 ; RV64IF-NEXT: beqz a0, .LBB13_2
; RV64IF-NEXT: bnez a0, .LBB13_2
; RV64IF-NEXT: # %bb.1: # %if.else ; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB13_2: # %if.then ; RV64IF-NEXT: .LBB13_2: # %if.then
; RV64IF-NEXT: call abort@plt ; RV64IF-NEXT: call abort@plt
%1 = fcmp ule float %a, %b %1 = fcmp ule float %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_une(float %a, float %b) nounwind { define void @br_fcmp_une(float %a, float %b) nounwind {
; RV32IF-LABEL: br_fcmp_une: ; RV32IF-LABEL: br_fcmp_une:
; RV32IF: # %bb.0: ; RV32IF: # %bb.0:
; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: addi sp, sp, -16
; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IF-NEXT: fmv.w.x ft0, a1 ; RV32IF-NEXT: fmv.w.x ft0, a1
; RV32IF-NEXT: fmv.w.x ft1, a0 ; RV32IF-NEXT: fmv.w.x ft1, a0
; RV32IF-NEXT: feq.s a0, ft1, ft0 ; RV32IF-NEXT: feq.s a0, ft1, ft0
; RV32IF-NEXT: xori a0, a0, 1 ; RV32IF-NEXT: beqz a0, .LBB14_2
; RV32IF-NEXT: bnez a0, .LBB14_2
; RV32IF-NEXT: # %bb.1: # %if.else ; RV32IF-NEXT: # %bb.1: # %if.else
; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: addi sp, sp, 16
; RV32IF-NEXT: ret ; RV32IF-NEXT: ret
; RV32IF-NEXT: .LBB14_2: # %if.then ; RV32IF-NEXT: .LBB14_2: # %if.then
; RV32IF-NEXT: call abort@plt ; RV32IF-NEXT: call abort@plt
; ;
; RV64IF-LABEL: br_fcmp_une: ; RV64IF-LABEL: br_fcmp_une:
; RV64IF: # %bb.0: ; RV64IF: # %bb.0:
; RV64IF-NEXT: addi sp, sp, -16 ; RV64IF-NEXT: addi sp, sp, -16
; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IF-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IF-NEXT: fmv.w.x ft0, a1 ; RV64IF-NEXT: fmv.w.x ft0, a1
; RV64IF-NEXT: fmv.w.x ft1, a0 ; RV64IF-NEXT: fmv.w.x ft1, a0
; RV64IF-NEXT: feq.s a0, ft1, ft0 ; RV64IF-NEXT: feq.s a0, ft1, ft0
; RV64IF-NEXT: xori a0, a0, 1 ; RV64IF-NEXT: beqz a0, .LBB14_2
; RV64IF-NEXT: bnez a0, .LBB14_2
; RV64IF-NEXT: # %bb.1: # %if.else ; RV64IF-NEXT: # %bb.1: # %if.else
; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IF-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IF-NEXT: addi sp, sp, 16 ; RV64IF-NEXT: addi sp, sp, 16
; RV64IF-NEXT: ret ; RV64IF-NEXT: ret
; RV64IF-NEXT: .LBB14_2: # %if.then ; RV64IF-NEXT: .LBB14_2: # %if.then
; RV64IF-NEXT: call abort@plt ; RV64IF-NEXT: call abort@plt
%1 = fcmp une float %a, %b %1 = fcmp une float %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
▲ Show 20 Lines • Show All 168 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/half-br-fcmp.ll

Show First 20 Lines • Show All 81 Lines • ▼ Show 20 Lines
; DAGCombiner::visitXOR converting the legal setoeq to setune, which requires ; DAGCombiner::visitXOR converting the legal setoeq to setune, which requires
; expansion. ; expansion.
define void @br_fcmp_oeq_alt(half %a, half %b) nounwind { define void @br_fcmp_oeq_alt(half %a, half %b) nounwind {
; RV32IZFH-LABEL: br_fcmp_oeq_alt: ; RV32IZFH-LABEL: br_fcmp_oeq_alt:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: feq.h a0, fa0, fa1 ; RV32IZFH-NEXT: feq.h a0, fa0, fa1
; RV32IZFH-NEXT: xori a0, a0, 1 ; RV32IZFH-NEXT: bnez a0, .LBB2_2
; RV32IZFH-NEXT: beqz a0, .LBB2_2
; RV32IZFH-NEXT: # %bb.1: # %if.else ; RV32IZFH-NEXT: # %bb.1: # %if.else
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; RV32IZFH-NEXT: .LBB2_2: # %if.then ; RV32IZFH-NEXT: .LBB2_2: # %if.then
; RV32IZFH-NEXT: call abort@plt ; RV32IZFH-NEXT: call abort@plt
; ;
; RV64IZFH-LABEL: br_fcmp_oeq_alt: ; RV64IZFH-LABEL: br_fcmp_oeq_alt:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: feq.h a0, fa0, fa1 ; RV64IZFH-NEXT: feq.h a0, fa0, fa1
; RV64IZFH-NEXT: xori a0, a0, 1 ; RV64IZFH-NEXT: bnez a0, .LBB2_2
; RV64IZFH-NEXT: beqz a0, .LBB2_2
; RV64IZFH-NEXT: # %bb.1: # %if.else ; RV64IZFH-NEXT: # %bb.1: # %if.else
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; RV64IZFH-NEXT: .LBB2_2: # %if.then ; RV64IZFH-NEXT: .LBB2_2: # %if.then
; RV64IZFH-NEXT: call abort@plt ; RV64IZFH-NEXT: call abort@plt
%1 = fcmp oeq half %a, %b %1 = fcmp oeq half %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
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} }
define void @br_fcmp_ugt(half %a, half %b) nounwind { define void @br_fcmp_ugt(half %a, half %b) nounwind {
; RV32IZFH-LABEL: br_fcmp_ugt: ; RV32IZFH-LABEL: br_fcmp_ugt:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fle.h a0, fa0, fa1 ; RV32IZFH-NEXT: fle.h a0, fa0, fa1
; RV32IZFH-NEXT: xori a0, a0, 1 ; RV32IZFH-NEXT: beqz a0, .LBB10_2
; RV32IZFH-NEXT: bnez a0, .LBB10_2
; RV32IZFH-NEXT: # %bb.1: # %if.else ; RV32IZFH-NEXT: # %bb.1: # %if.else
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; RV32IZFH-NEXT: .LBB10_2: # %if.then ; RV32IZFH-NEXT: .LBB10_2: # %if.then
; RV32IZFH-NEXT: call abort@plt ; RV32IZFH-NEXT: call abort@plt
; ;
; RV64IZFH-LABEL: br_fcmp_ugt: ; RV64IZFH-LABEL: br_fcmp_ugt:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: fle.h a0, fa0, fa1 ; RV64IZFH-NEXT: fle.h a0, fa0, fa1
; RV64IZFH-NEXT: xori a0, a0, 1 ; RV64IZFH-NEXT: beqz a0, .LBB10_2
; RV64IZFH-NEXT: bnez a0, .LBB10_2
; RV64IZFH-NEXT: # %bb.1: # %if.else ; RV64IZFH-NEXT: # %bb.1: # %if.else
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; RV64IZFH-NEXT: .LBB10_2: # %if.then ; RV64IZFH-NEXT: .LBB10_2: # %if.then
; RV64IZFH-NEXT: call abort@plt ; RV64IZFH-NEXT: call abort@plt
%1 = fcmp ugt half %a, %b %1 = fcmp ugt half %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_uge(half %a, half %b) nounwind { define void @br_fcmp_uge(half %a, half %b) nounwind {
; RV32IZFH-LABEL: br_fcmp_uge: ; RV32IZFH-LABEL: br_fcmp_uge:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: flt.h a0, fa0, fa1 ; RV32IZFH-NEXT: flt.h a0, fa0, fa1
; RV32IZFH-NEXT: xori a0, a0, 1 ; RV32IZFH-NEXT: beqz a0, .LBB11_2
; RV32IZFH-NEXT: bnez a0, .LBB11_2
; RV32IZFH-NEXT: # %bb.1: # %if.else ; RV32IZFH-NEXT: # %bb.1: # %if.else
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; RV32IZFH-NEXT: .LBB11_2: # %if.then ; RV32IZFH-NEXT: .LBB11_2: # %if.then
; RV32IZFH-NEXT: call abort@plt ; RV32IZFH-NEXT: call abort@plt
; ;
; RV64IZFH-LABEL: br_fcmp_uge: ; RV64IZFH-LABEL: br_fcmp_uge:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: flt.h a0, fa0, fa1 ; RV64IZFH-NEXT: flt.h a0, fa0, fa1
; RV64IZFH-NEXT: xori a0, a0, 1 ; RV64IZFH-NEXT: beqz a0, .LBB11_2
; RV64IZFH-NEXT: bnez a0, .LBB11_2
; RV64IZFH-NEXT: # %bb.1: # %if.else ; RV64IZFH-NEXT: # %bb.1: # %if.else
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; RV64IZFH-NEXT: .LBB11_2: # %if.then ; RV64IZFH-NEXT: .LBB11_2: # %if.then
; RV64IZFH-NEXT: call abort@plt ; RV64IZFH-NEXT: call abort@plt
%1 = fcmp uge half %a, %b %1 = fcmp uge half %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_ult(half %a, half %b) nounwind { define void @br_fcmp_ult(half %a, half %b) nounwind {
; RV32IZFH-LABEL: br_fcmp_ult: ; RV32IZFH-LABEL: br_fcmp_ult:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: fle.h a0, fa1, fa0 ; RV32IZFH-NEXT: fle.h a0, fa1, fa0
; RV32IZFH-NEXT: xori a0, a0, 1 ; RV32IZFH-NEXT: beqz a0, .LBB12_2
; RV32IZFH-NEXT: bnez a0, .LBB12_2
; RV32IZFH-NEXT: # %bb.1: # %if.else ; RV32IZFH-NEXT: # %bb.1: # %if.else
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; RV32IZFH-NEXT: .LBB12_2: # %if.then ; RV32IZFH-NEXT: .LBB12_2: # %if.then
; RV32IZFH-NEXT: call abort@plt ; RV32IZFH-NEXT: call abort@plt
; ;
; RV64IZFH-LABEL: br_fcmp_ult: ; RV64IZFH-LABEL: br_fcmp_ult:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: fle.h a0, fa1, fa0 ; RV64IZFH-NEXT: fle.h a0, fa1, fa0
; RV64IZFH-NEXT: xori a0, a0, 1 ; RV64IZFH-NEXT: beqz a0, .LBB12_2
; RV64IZFH-NEXT: bnez a0, .LBB12_2
; RV64IZFH-NEXT: # %bb.1: # %if.else ; RV64IZFH-NEXT: # %bb.1: # %if.else
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; RV64IZFH-NEXT: .LBB12_2: # %if.then ; RV64IZFH-NEXT: .LBB12_2: # %if.then
; RV64IZFH-NEXT: call abort@plt ; RV64IZFH-NEXT: call abort@plt
%1 = fcmp ult half %a, %b %1 = fcmp ult half %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_ule(half %a, half %b) nounwind { define void @br_fcmp_ule(half %a, half %b) nounwind {
; RV32IZFH-LABEL: br_fcmp_ule: ; RV32IZFH-LABEL: br_fcmp_ule:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: flt.h a0, fa1, fa0 ; RV32IZFH-NEXT: flt.h a0, fa1, fa0
; RV32IZFH-NEXT: xori a0, a0, 1 ; RV32IZFH-NEXT: beqz a0, .LBB13_2
; RV32IZFH-NEXT: bnez a0, .LBB13_2
; RV32IZFH-NEXT: # %bb.1: # %if.else ; RV32IZFH-NEXT: # %bb.1: # %if.else
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; RV32IZFH-NEXT: .LBB13_2: # %if.then ; RV32IZFH-NEXT: .LBB13_2: # %if.then
; RV32IZFH-NEXT: call abort@plt ; RV32IZFH-NEXT: call abort@plt
; ;
; RV64IZFH-LABEL: br_fcmp_ule: ; RV64IZFH-LABEL: br_fcmp_ule:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: flt.h a0, fa1, fa0 ; RV64IZFH-NEXT: flt.h a0, fa1, fa0
; RV64IZFH-NEXT: xori a0, a0, 1 ; RV64IZFH-NEXT: beqz a0, .LBB13_2
; RV64IZFH-NEXT: bnez a0, .LBB13_2
; RV64IZFH-NEXT: # %bb.1: # %if.else ; RV64IZFH-NEXT: # %bb.1: # %if.else
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; RV64IZFH-NEXT: .LBB13_2: # %if.then ; RV64IZFH-NEXT: .LBB13_2: # %if.then
; RV64IZFH-NEXT: call abort@plt ; RV64IZFH-NEXT: call abort@plt
%1 = fcmp ule half %a, %b %1 = fcmp ule half %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
if.else: if.else:
ret void ret void
if.then: if.then:
tail call void @abort() tail call void @abort()
unreachable unreachable
} }
define void @br_fcmp_une(half %a, half %b) nounwind { define void @br_fcmp_une(half %a, half %b) nounwind {
; RV32IZFH-LABEL: br_fcmp_une: ; RV32IZFH-LABEL: br_fcmp_une:
; RV32IZFH: # %bb.0: ; RV32IZFH: # %bb.0:
; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: addi sp, sp, -16
; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
; RV32IZFH-NEXT: feq.h a0, fa0, fa1 ; RV32IZFH-NEXT: feq.h a0, fa0, fa1
; RV32IZFH-NEXT: xori a0, a0, 1 ; RV32IZFH-NEXT: beqz a0, .LBB14_2
; RV32IZFH-NEXT: bnez a0, .LBB14_2
; RV32IZFH-NEXT: # %bb.1: # %if.else ; RV32IZFH-NEXT: # %bb.1: # %if.else
; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload
; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: addi sp, sp, 16
; RV32IZFH-NEXT: ret ; RV32IZFH-NEXT: ret
; RV32IZFH-NEXT: .LBB14_2: # %if.then ; RV32IZFH-NEXT: .LBB14_2: # %if.then
; RV32IZFH-NEXT: call abort@plt ; RV32IZFH-NEXT: call abort@plt
; ;
; RV64IZFH-LABEL: br_fcmp_une: ; RV64IZFH-LABEL: br_fcmp_une:
; RV64IZFH: # %bb.0: ; RV64IZFH: # %bb.0:
; RV64IZFH-NEXT: addi sp, sp, -16 ; RV64IZFH-NEXT: addi sp, sp, -16
; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill ; RV64IZFH-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
; RV64IZFH-NEXT: feq.h a0, fa0, fa1 ; RV64IZFH-NEXT: feq.h a0, fa0, fa1
; RV64IZFH-NEXT: xori a0, a0, 1 ; RV64IZFH-NEXT: beqz a0, .LBB14_2
; RV64IZFH-NEXT: bnez a0, .LBB14_2
; RV64IZFH-NEXT: # %bb.1: # %if.else ; RV64IZFH-NEXT: # %bb.1: # %if.else
; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload ; RV64IZFH-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; RV64IZFH-NEXT: addi sp, sp, 16 ; RV64IZFH-NEXT: addi sp, sp, 16
; RV64IZFH-NEXT: ret ; RV64IZFH-NEXT: ret
; RV64IZFH-NEXT: .LBB14_2: # %if.then ; RV64IZFH-NEXT: .LBB14_2: # %if.then
; RV64IZFH-NEXT: call abort@plt ; RV64IZFH-NEXT: call abort@plt
%1 = fcmp une half %a, %b %1 = fcmp une half %a, %b
br i1 %1, label %if.then, label %if.else br i1 %1, label %if.then, label %if.else
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