[MachineSink] SinkIntoLoop: analyse stores and aliases in between

[SjoerdMeijer]

Summary

This depends on D93694, and extends the SinkIntoLoop analysis to be less conservative. I.e., it was assuming we couldn't move across a store with isSafeToMove(AA, DontMoveAcrossStore), but now we do actually analyse that by querying HasStoreBetween(). Thus, the SinkIntoLoop part now starts reusing the infrastructure already available in MachineSink, which was the motivation of D93694. Function HasStoreBetween() doesn't analyse the From and To blocks, and now we also perform alias analysis of the instructions in these blocks to see if sinking is legal (which also reuses bits and pieces from MachineSink).

[SjoerdMeijer]

Rebased after D93694, and this now shows changes in the tests that were added there. New tests have been added to check alias analysis, and some other minor modifications.

Summarising:

• this now performs alias analysis of all instructions/blocks between the from and to location when an instruction is sunk.
• and isSafeToMove is less conservative because now we actually analyse hasStoreBetween rather than assuming this is the case.

[SjoerdMeijer]

Restored a FIXME comment.

[SjoerdMeijer]

llvm/lib/CodeGen/MachineSink.cpp

1213

I have removed this, because otherwise it is extremely difficult to actually let this do and sink something. Thus, in this patch we address the analysis/correctness part of the transformation, and in the follow up I will address here the profitability question.

[dmgreen]

llvm/lib/CodeGen/MachineSink.cpp

382

branches. (Store instructions can still have defs, as in for post-inc's)

387

Why remove this call to isSafeToMove? Don't we need to check for stores/exceptions/unmodelled side effects/etc?

1229

If it's sinking into a loop, does it not have to check all the instructions in the loop for aliasing?

llvm/test/CodeGen/AArch64/loop-sink.mir

1051–1052

Some of these look very expensive to avoid a stack reload. Is the reload not cheaper, even if it is in the loop?

[SjoerdMeijer]

llvm/lib/CodeGen/MachineSink.cpp

382

Will clarify this comment a bit.

387

This has not been deleted but, it has been moved to line 1290 and is now part of MachineSinking::IsSafeToMove(). The reason is that we need to have found the sink block and loop in order analyse DontMoveAcrossStore.

1229

Yeah, good point! I was assuming/using single block loops, but not all loops confirm to that standard. ;-)
This should indeed check all loop blocks/instructions.

llvm/test/CodeGen/AArch64/loop-sink.mir

1051–1052

Yep, that might very well be the case. But this is about building up the framework to support loop sinking which requires quite a bit of surgery: after this analysis/correctness patch, we indeed need to work on the cost-model/profitability (your remark), we may need options to force or limit the number of sinks, and then we need to enable this by default. Thus, quite a few steps to go, and cost analysis will be next after this patch.

[dmgreen]

llvm/lib/CodeGen/MachineSink.cpp

387

Oh yeah. There it is. My Ctrl+f failed me.

llvm/test/CodeGen/AArch64/loop-sink.mir

1051–1052

Do you have the cost part yet? It's difficult to see if this will be a good thing to do without the complete picture. I guess having the code to do it shouldn't hurt in any case.

Naively it would seem to trade one stack reload in the loop for a sunk instruction and the possibly the stack reload of it's arguments. And this appears to be AArch64 - a system with a lot of registers and comparatively cheap stack reloads. On v6m it would be much more likely to come up with the limited amount of registers available. Without being careful it has a high chance of making things worse, not better!

[SjoerdMeijer]

Thanks for reviewing!
Find replies inlined to your comments/questions. I am now addressing the issue that all blocks in the loop should be analysed as remarked previously.

llvm/test/CodeGen/AArch64/loop-sink.mir

1051–1052

It's difficult to see if this will be a good thing to do without the complete picture.

I think the complete picture does not exist. Or, there are many complete pictures, thus I don't think I can meaningfully sketch this or claim to have provided this. The general picture is that we have aggressive hoisting as a canonicalisation transformation, but that's the only mode that we have, and there's nothing in between, please see also my commit message rG48ecba350ed6 of the groundwork of this. This has links to discussions on the llvm dev mailing list, where this has been discussed several times and highlighted as a generic LLVM issue. This is adding the framework to at least be able to support this.

Do you have the cost part yet?

Nope, not yet. My motivating example is in D92488, which has actually been massively reduced. I think there's low hanging fruit here where we can easily do better.

Naively it would seem to trade one stack reload in the loop for a sunk instruction and the possibly the stack reload of it's arguments. And this appears to be AArch64 - a system with a lot of registers and comparatively cheap stack reloads. On v6m it would be much more likely to come up with the limited amount of registers available. Without being careful it has a high chance of making things worse, not better!

Yep, sure, this needs careful tuning, like most other things. This is what we should do next.

[SjoerdMeijer]

Analyse all blocks/instructions in the loop, not only the sink block, and a multi loops, multi-block loop test case cant_sink_multi_block_loop_with_call for that.

[shchenz]

hasStoreBetween is a little time consuming, so it is better to do some compiling time testing also.

llvm/lib/CodeGen/MachineSink.cpp

449

Will it cause something wrong if we don't clear the cache here?

I guess the cached data here should not impact the following sinking from the loop preheader to the loop body.
Till now, all the sinkings are from the same depth loop or from a bigger depth loop to a smaller depth loop.

1224

I guess we only need to call hasStoreBetween for load instructions?

1232

This is a little strange, if we check there are no alias instructions in the whole loop to I, do we still need the above hasStoreBetween check? I is from the loop preheader, SinkTo is a block in the loop, hasStoreBetween is also checking alias for load/store instructions.

[SjoerdMeijer]

Thanks for looking!

In D94308#2538202, @shchenz wrote:

hasStoreBetween is a little time consuming, so it is better to do some compiling time testing also.

This is really where I think/hope the caching of the result is going to help, so that essentially the analysis is done once, and the rest are lookups. And since we run the loop sinking as a second second, I hope it's almost free.
But I said "hope" a few times, and it's a good suggestion to check this, which I will do! Also, you made a good point about clearing this cache, see inline.

llvm/lib/CodeGen/MachineSink.cpp

449

Good point. I haven't seen it doing anything wrong, I didn't try very hard though, but I put it there because I saw the preheader block being modified in the first sinking step. Loop sinking as a second step, then tries to sink instructions from that modified preheader block, so I thought about just clearing it just to be sure. But now thinking about it more, I don't think this can cause problems, so after verifying this I will remove this clearing of the cache.

1224

Yep, will change that.

1232

Agreed that this has become messy. I.e., it's doing more work than necessary.
We need to analyse all instructions in preheader block, which is what we do in 1).
Then, we need to analyse all blocks/instructions in the loop, which is what we do in 3).
I think we can now indeed get rid of 2), which would be useful for more generic cases but here in our case the preheader is directly dominating the loop blocks so don't need to analyse a path in between that.

[SjoerdMeijer]

This addresses the code review comments: removes the hasStoreBetween call which is unnecessary, and some other minor changes.

Will now to see if this has any effect on compile times.

[SjoerdMeijer]

Re: compile times, I haven't found anything concerning. It's all within the noise.

I found I have one thing to fix though.

[SjoerdMeijer]

• This has been tested on the llvm test-suite for correctness and compile times, and both look good.
• This fixes an issue related to loop-invariant checks, the HasLoopPHIUse check. It was incorrectly sinking instruction when they were not loop-invariant, i.e. when they had phi uses. This was an existing check, but I missed this when I moved this from MachineLICM to MachineSink. This is now a helper in MachineLoop, and used in both passes.
• I have improved the MIR tests, especially the alias tests.

[dmgreen]

llvm/lib/CodeGen/MachineSink.cpp

1094

I happened to notice betweeen -> between

1197

Can this set the HasStoreCache for the block if it hasn't seen all the instructions in it yet?

[SjoerdMeijer]

llvm/lib/CodeGen/MachineSink.cpp

1197

Thanks Dave. I am investigating a miscompilation that I noticed for the llvm test suite. Will address your remark once I have a fix, and include it in the new revision for that.

[SjoerdMeijer]

This fixes a miscompilation for x86 which was related to eflags setting instructions. This check was already present in MachineSink, which I can now "borrow" for the loop-sinking. This now passes a the llvm test suite on x86 and on aarch64, and also a bootstrap.

[SjoerdMeijer]

Fixed typo.

I will look into this separately:

Can this set the HasStoreCache for the block if it hasn't seen all the instructions in it yet?

I have uploaded D96485 to control compile-times.

Like I said, this passes my testing. So, what do you think, good to go?
Please note this is still disabled by default.

Next step:

• the interesting bit: cost-model to decide when to sink.

[SjoerdMeijer]

Friendly ping. Are we happy with this?

I appreciate that test X86/loop-sink.mir is a bit large which I added in the latest revisions, but this has been reduced from a llvm-suite miscompilation and I couldn't reduce it further within a reasonable amount of time. I thought one larger tests wouldn't be bad, actually saw some benefits.
The alternative is that I remove it. The added check is a corner case for X86, and it's an existing check that I am reusing so it is check that is covered. Just for completeness it's this check that I refactored into HasInstrSideEffects:

// If the instruction to move defines a dead physical register which is live
// when leaving the basic block, don't move it because it could turn into a
// "zombie" define of that preg. E.g., EFLAGS. (<rdar://problem/8030636>)
static bool HasInstrSideEffects(MachineInstr &MI, MachineBasicBlock *SinkTo) {

[samparker]

The X86 test is indeed large! Considering that it's just an unrolled loop with the same sequence repeated MANY times, could you not just delete 3/4 of the loop and update the indvar accordingly?

[SjoerdMeijer]

Hmmmm, I have tried quite a few things, didn't see this particular check triggering, but will give it another try then.

[dmgreen]

I will look into this separately:

Can this set the HasStoreCache for the block if it hasn't seen all the instructions in it yet?

hasStoreBetween is called by SinkInstruction, and we can't break the existing code even if the rest is currently not enabled by default.

llvm/lib/CodeGen/MachineSink.cpp

1205

This doesn't seem to have anything to do with side effects. I'm surprised there isn't more needed for clobbering physical registers. Because we are sinking into the start of a block, we only need to check the live-in, not any other instructions along the way?

llvm/include/llvm/CodeGen/MachineLoopInfo.h

public:
   /// cannot find a terminating instruction with location information,
   /// it returns an unknown location.
   DebugLoc getStartLoc() const;
 
   /// Returns true if the instruction is loop invariant.
   /// I.e., all virtual register operands are defined outside of the loop,
   /// physical registers aren't accessed explicitly, and there are no side
   /// effects that aren't captured by the operands or other flags.
-  bool isLoopInvariant(MachineInstr &I) const;
+  bool isLoopInvariant(MachineInstr &MI) const;
+
+  /// Return true if the specified instruction is used by a phi node.
+  bool hasLoopPHIUse(const MachineInstr *MI) const;
 
   void dump() const;
 
 private:
   friend class LoopInfoBase<MachineBasicBlock, MachineLoop>;
 
   explicit MachineLoop(MachineBasicBlock *MBB)
     : LoopBase<MachineBasicBlock, MachineLoop>(MBB) {}

llvm/lib/CodeGen/MachineLICM.cpp

void ProcessMI(MachineInstr *MI, BitVector &PhysRegDefs,
                    SmallVectorImpl<CandidateInfo> &Candidates);
 
     void AddToLiveIns(MCRegister Reg);
 
     bool IsLICMCandidate(MachineInstr &I);
 
     bool IsLoopInvariantInst(MachineInstr &I);
 
-    bool HasLoopPHIUse(const MachineInstr *MI) const;
-
     bool HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
                                Register Reg) const;
 
     bool IsCheapInstruction(MachineInstr &MI) const;
 
     bool CanCauseHighRegPressure(const DenseMap<unsigned, int> &Cost,
                                  bool Cheap);
 

 bool MachineLICMBase::IsLoopInvariantInst(MachineInstr &I) {
   if (!IsLICMCandidate(I)) {
     LLVM_DEBUG(dbgs() << "LICM: Instruction not a LICM candidate\n");
     return false;
   }
   return CurLoop->isLoopInvariant(I);
 }
 
-/// Return true if the specified instruction is used by a phi node and hoisting
-/// it could cause a copy to be inserted.
-bool MachineLICMBase::HasLoopPHIUse(const MachineInstr *MI) const {
-  SmallVector<const MachineInstr*, 8> Work(1, MI);
-  do {
-    MI = Work.pop_back_val();
-    for (const MachineOperand &MO : MI->operands()) {
-      if (!MO.isReg() || !MO.isDef())
-        continue;
-      Register Reg = MO.getReg();
-      if (!Register::isVirtualRegister(Reg))
-        continue;
-      for (MachineInstr &UseMI : MRI->use_instructions(Reg)) {
-        // A PHI may cause a copy to be inserted.
-        if (UseMI.isPHI()) {
-          // A PHI inside the loop causes a copy because the live range of Reg is
-          // extended across the PHI.
-          if (CurLoop->contains(&UseMI))
-            return true;
-          // A PHI in an exit block can cause a copy to be inserted if the PHI
-          // has multiple predecessors in the loop with different values.
-          // For now, approximate by rejecting all exit blocks.
-          if (isExitBlock(UseMI.getParent()))
-            return true;
-          continue;
-        }
-        // Look past copies as well.
-        if (UseMI.isCopy() && CurLoop->contains(&UseMI))
-          Work.push_back(&UseMI);
-      }
-    }
-  } while (!Work.empty());
-  return false;
-}
-
 /// Compute operand latency between a def of 'Reg' and an use in the current
 /// loop, return true if the target considered it high.
 bool MachineLICMBase::HasHighOperandLatency(MachineInstr &MI, unsigned DefIdx,
                                             Register Reg) const {
   if (MRI->use_nodbg_empty(Reg))
     return false;
 
   for (MachineInstr &UseMI : MRI->use_nodbg_instructions(Reg)) {
bool MachineLICMBase::IsProfitableToHoist(MachineInstr &MI) {
   //
   // - When hoisting the last use of a value in the loop, that value no longer
   //   needs to be live in the loop. This lowers register pressure in the loop.
 
   if (HoistConstStores &&  isCopyFeedingInvariantStore(MI, MRI, TRI))
     return true;
 
   bool CheapInstr = IsCheapInstruction(MI);
-  bool CreatesCopy = HasLoopPHIUse(&MI);
+  bool CreatesCopy = CurLoop->hasLoopPHIUse(&MI);
 
   // Don't hoist a cheap instruction if it would create a copy in the loop.
   if (CheapInstr && CreatesCopy) {
     LLVM_DEBUG(dbgs() << "Won't hoist cheap instr with loop PHI use: " << MI);
     return false;
   }
 
   // Rematerializable instructions should always be hoisted since the register

llvm/lib/CodeGen/MachineLoopInfo.cpp

if (S == HB)
       continue;
     MachineLoop *T = getLoopFor(S);
     if (T && T->getHeader() == S)
       return nullptr;
   }
   return Preheader;
 }
 
-bool MachineLoop::isLoopInvariant(MachineInstr &I) const {
-  MachineFunction *MF = I.getParent()->getParent();
+bool MachineLoop::isLoopInvariant(MachineInstr &MI) const {
+  MachineFunction *MF = MI.getParent()->getParent();
   MachineRegisterInfo *MRI = &MF->getRegInfo();
   const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
 
   // The instruction is loop invariant if all of its operands are.
-  for (const MachineOperand &MO : I.operands()) {
+  for (const MachineOperand &MO : MI.operands()) {
     if (!MO.isReg())
       continue;
 
     Register Reg = MO.getReg();
     if (Reg == 0) continue;
 
     // An instruction that uses or defines a physical register can't e.g. be
     // hoisted, so mark this as not invariant.
     if (Register::isPhysicalRegister(Reg)) {
       if (MO.isUse()) {
         // If the physreg has no defs anywhere, it's just an ambient register
         // and we can freely move its uses. Alternatively, if it's allocatable,
         // it could get allocated to something with a def during allocation.
         // However, if the physreg is known to always be caller saved/restored
         // then this use is safe to hoist.
         if (!MRI->isConstantPhysReg(Reg) &&
-            !(TRI->isCallerPreservedPhysReg(Reg.asMCReg(), *I.getMF())))
+            !(TRI->isCallerPreservedPhysReg(Reg.asMCReg(), *MI.getMF())))
           return false;
         // Otherwise it's safe to move.
         continue;
       } else if (!MO.isDead()) {
         // A def that isn't dead can't be moved.
         return false;
       } else if (getHeader()->isLiveIn(Reg)) {
         // If the reg is live into the loop, we can't hoist an instruction
for (const MachineOperand &MO : MI.operands()) {
     if (contains(MRI->getVRegDef(Reg)))
       return false;
   }
 
   // If we got this far, the instruction is loop invariant!
   return true;
 }
 
+/// Return true if the specified instruction is used by a phi node and hoisting
+/// it could cause a copy to be inserted.
+bool MachineLoop::hasLoopPHIUse(const MachineInstr *MI) const {
+  const MachineFunction *MF = MI->getParent()->getParent();
+  const MachineRegisterInfo *MRI = &MF->getRegInfo();
+  SmallVector<MachineBasicBlock *> ExitBlocks;
+  getExitBlocks (ExitBlocks);
+  SmallVector<const MachineInstr*, 8> Work(1, MI);
+  do {
+    MI = Work.pop_back_val();
+    for (const MachineOperand &MO : MI->operands()) {
+      if (!MO.isReg() || !MO.isDef())
+        continue;
+      Register Reg = MO.getReg();
+      if (!Register::isVirtualRegister(Reg))
+        continue;
+      for (MachineInstr &UseMI : MRI->use_instructions(Reg)) {
+        // A PHI may cause a copy to be inserted.
+        if (UseMI.isPHI()) {
+          // A PHI inside the loop causes a copy because the live range of Reg is
+          // extended across the PHI.
+          if (contains(&UseMI))
+            return true;
+          // A PHI in an exit block can cause a copy to be inserted if the PHI
+          // has multiple predecessors in the loop with different values.
+          // For now, approximate by rejecting all exit blocks.
+          if (is_contained(ExitBlocks, UseMI.getParent()))
+            return true;
+          continue;
+        }
+        // Look past copies as well.
+        if (UseMI.isCopy() && contains(&UseMI))
+          Work.push_back(&UseMI);
+      }
+    }
+  } while (!Work.empty());
+  return false;
+}
+
 #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
 LLVM_DUMP_METHOD void MachineLoop::dump() const {
   print(dbgs());
 }
 #endif

llvm/lib/CodeGen/MachineSink.cpp

private:
     bool ProcessBlock(MachineBasicBlock &MBB);
     void ProcessDbgInst(MachineInstr &MI);
     bool isWorthBreakingCriticalEdge(MachineInstr &MI,
                                      MachineBasicBlock *From,
                                      MachineBasicBlock *To);
 
     bool hasStoreBetween(MachineBasicBlock *From, MachineBasicBlock *To,
                          MachineInstr &MI);
+    void AddRegsToClearKillFlags(MachineInstr &MI);
 
     /// Postpone the splitting of the given critical
     /// edge (\p From, \p To).
     ///
     /// We do not split the edges on the fly. Indeed, this invalidates
     /// the dominance information and thus triggers a lot of updates
     /// of that information underneath.
     /// Instead, we postpone all the splits after each iteration of
bool AllUsesDominatedByBlock(Register Reg, MachineBasicBlock *MBB,
                                  MachineBasicBlock *DefMBB, bool &BreakPHIEdge,
                                  bool &LocalUse) const;
     MachineBasicBlock *FindSuccToSinkTo(MachineInstr &MI, MachineBasicBlock *MBB,
                bool &BreakPHIEdge, AllSuccsCache &AllSuccessors);
 
     void FindLoopSinkCandidates(MachineLoop *L, MachineBasicBlock *BB,
                                 SmallVectorImpl<MachineInstr *> &Candidates);
     bool SinkIntoLoop(MachineLoop *L, MachineInstr &I);
+    bool IsSafeToMove(MachineLoop *L, MachineInstr &I,
+                      MachineBasicBlock *SinkTo);
+    bool AreAliased(MachineInstr &First, MachineInstr &Second,
+                    MachineBasicBlock *From, MachineBasicBlock *To,
+                    DenseSet<MachineBasicBlock *> HandledDomBlocks,
+                    bool &SawStore, bool &HasAliasedStore) ;
 
     bool isProfitableToSinkTo(Register Reg, MachineInstr &MI,
                               MachineBasicBlock *MBB,
                               MachineBasicBlock *SuccToSinkTo,
                               AllSuccsCache &AllSuccessors);
 
     bool PerformTrivialForwardCoalescing(MachineInstr &MI,
                                          MachineBasicBlock *MBB);
for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
     // Check that it dominates.
     if (!DT->dominates(MBB, UseBlock))
       return false;
   }
 
   return true;
 }
 
-/// Return true if this machine instruction loads from global offset table or
-/// constant pool.
-static bool mayLoadFromGOTOrConstantPool(MachineInstr &MI) {
-  assert(MI.mayLoad() && "Expected MI that loads!");
-
-  // If we lost memory operands, conservatively assume that the instruction
-  // reads from everything..
-  if (MI.memoperands_empty())
-    return true;
-
-  for (MachineMemOperand *MemOp : MI.memoperands())
-    if (const PseudoSourceValue *PSV = MemOp->getPseudoValue())
-      if (PSV->isGOT() || PSV->isConstantPool())
-        return true;
-
-  return false;
-}
-
 void MachineSinking::FindLoopSinkCandidates(MachineLoop *L, MachineBasicBlock *BB,
     SmallVectorImpl<MachineInstr *> &Candidates) {
   for (auto &MI : *BB) {
     LLVM_DEBUG(dbgs() << "LoopSink: Analysing candidate: " << MI);
     if (!TII->shouldSink(MI)) {
       LLVM_DEBUG(dbgs() << "LoopSink: Instruction not a candidate for this "
                            "target\n");
       continue;
     }
-    if (!L->isLoopInvariant(MI)) {
+    // If physical registers are used, then this is marked as not loop
+    // invariant. This can be the case if the preheader is the entry block, and
+    // when there are copy instructions of function arguments that are passed
+    // through registers.
+    if (!L->isLoopInvariant(MI) || L->hasLoopPHIUse(&MI)) {
       LLVM_DEBUG(dbgs() << "LoopSink: Instruction is not loop invariant\n");
       continue;
     }
-    bool DontMoveAcrossStore = true;
-    if (!MI.isSafeToMove(AA, DontMoveAcrossStore)) {
-      LLVM_DEBUG(dbgs() << "LoopSink: Instruction not safe to move.\n");
-      continue;
-    }
-    if (MI.mayLoad() && !mayLoadFromGOTOrConstantPool(MI)) {
-      LLVM_DEBUG(dbgs() << "LoopSink: Dont sink GOT or constant pool loads\n");
-      continue;
-    }
     if (MI.isConvergent())
       continue;
 
+    // Skip instruction that don't produce values, like branches and certain
+    // store instructions (that e.g. don't post-increment).
     const MachineOperand &MO = MI.getOperand(0);
-    if (!MO.isReg() || !MO.getReg() || !MO.isDef())
+    if (!MO.isReg() || !MO.getReg() || !MO.isDef()) {
+      LLVM_DEBUG(dbgs() << "LoopSink: Instruction does not define a value.\n");
       continue;
-    if (!MRI->hasOneDef(MO.getReg()))
+    }
+    if (!MRI->hasOneDef(MO.getReg())) {
+      LLVM_DEBUG(dbgs() << "LoopSink: Instruction does not have 1 def.\n");
       continue;
+    }
 
     LLVM_DEBUG(dbgs() << "LoopSink: Instruction added as candidate.\n");
     Candidates.push_back(&MI);
   }
 }
 
 bool MachineSinking::runOnMachineFunction(MachineFunction &MF) {
   if (skipFunction(MF.getFunction()))
for (auto &Pair : ToSplit) {
         LLVM_DEBUG(dbgs() << " *** Not legal to break critical edge\n");
     }
     // If this iteration over the code changed anything, keep iterating.
     if (!MadeChange) break;
     EverMadeChange = true;
   }
 
   if (SinkInstsIntoLoop) {
     SmallVector<MachineLoop *, 8> Loops(LI->begin(), LI->end());
     for (auto *L : Loops) {
       MachineBasicBlock *Preheader = LI->findLoopPreheader(L);
       if (!Preheader) {
         LLVM_DEBUG(dbgs() << "LoopSink: Can't find preheader\n");
         continue;
       }
       SmallVector<MachineInstr *, 8> Candidates;
       FindLoopSinkCandidates(L, Preheader, Candidates);
 
       // Walk the candidates in reverse order so that we start with the use
       // of a def-use chain, if there is any.
       for (auto It = Candidates.rbegin(); It != Candidates.rend(); ++It) {
         MachineInstr *I = *It;
+
+        // TODO: This is conservative because we bail as soon as we find one
+        // instruction that cannot be sunk. Better is to do this per def-use
+        // chain, so we try a next chain if one fails.
         if (!SinkIntoLoop(L, *I))
           break;
+
         EverMadeChange = true;
         ++NumLoopSunk;
       }
     }
   }
 
   HasStoreCache.clear();
   StoreInstrCache.clear();
for (SmallVectorImpl<MachineInstr *>::iterator DBI = DbgValuesToSink.begin(),
     MachineInstr *NewDbgMI = DbgMI->getMF()->CloneMachineInstr(*DBI);
     SuccToSinkTo.insert(InsertPos, NewDbgMI);
 
     if (!attemptDebugCopyProp(MI, *DbgMI))
       DbgMI->setDebugValueUndef();
   }
 }
 
-/// hasStoreBetween - check if there is store betweeen straight line blocks From
+/// hasStoreBetween - check if there is store between straight line blocks From
 /// and To.
 bool MachineSinking::hasStoreBetween(MachineBasicBlock *From,
                                      MachineBasicBlock *To, MachineInstr &MI) {
   // Make sure From and To are in straight line which means From dominates To
   // and To post dominates From.
   if (!DT->dominates(From, To) || !PDT->dominates(To, From))
     return true;
 
if (PDT->dominates(To, BB)) {
           else if(DomBB != BB && DT->dominates(BB, DomBB))
             HasStoreCache[std::make_pair(From, DomBB)] = true;
         }
         HasStoreCache[BlockPair] = true;
         return true;
       }
 
       for (MachineInstr &I : *BB) {
-        // Treat as alias conservatively for a call or an ordered memory
-        // operation.
-        if (I.isCall() || I.hasOrderedMemoryRef()) {
-          for (auto *DomBB : HandledDomBlocks) {
-            if (DomBB != BB && DT->dominates(DomBB, BB))
-              HasStoreCache[std::make_pair(DomBB, To)] = true;
-            else if(DomBB != BB && DT->dominates(BB, DomBB))
-              HasStoreCache[std::make_pair(From, DomBB)] = true;
-          }
-          HasStoreCache[BlockPair] = true;
-          return true;
-        }
+        bool Aliased = AreAliased(I, MI, From, To, HandledBlocks, SawStore,
+                                  HasAliasedStore);
+        if (Aliased && (I.isCall() || I.hasOrderedMemoryRef()))
+          return true;
+      }
+    }
+  }
+  // If there is no store at all, cache the result.
+  if (!SawStore)
+    HasStoreCache[BlockPair] = false;
+  return HasAliasedStore;
+}
+
+bool MachineSinking::AreAliased(MachineInstr &First, MachineInstr &Second,
+    MachineBasicBlock *From, MachineBasicBlock *To,
+    DenseSet<MachineBasicBlock *> HandledDomBlocks, bool &SawStore,
+    bool &HasAliasedStore) {
+  MachineBasicBlock *BB = First.getParent();
+  auto BlockPair = std::make_pair(From, To);
+
+  if (First.isCall() || Second.hasOrderedMemoryRef()) {
 
-        if (I.mayStore()) {
-          SawStore = true;
-          // We still have chance to sink MI if all stores between are not
-          // aliased to MI.
-          // Cache all store instructions, so that we don't need to go through
-          // all From reachable blocks for next load instruction.
-          if (I.mayAlias(AA, MI, false))
-            HasAliasedStore = true;
-          StoreInstrCache[BlockPair].push_back(&I);
-        }
-      }
-    }
+  if (First.mayStore()) {
+    if (First.mayAlias(AA, Second, false))
+    StoreInstrCache[BlockPair].push_back(&First);
   }
+
   // If there is no store at all, cache the result.
   if (!SawStore)
     HasStoreCache[BlockPair] = false;
   return HasAliasedStore;
 }
 
+
+// If the instruction to move defines a dead physical register which is live
+// when leaving the basic block, don't move it because it could turn into a
+// "zombie" define of that preg. E.g., EFLAGS. (<rdar://problem/8030636>)
+static bool HasInstrSideEffects(MachineInstr &MI, MachineBasicBlock *SinkTo) {
+  for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
+    const MachineOperand &MO = MI.getOperand(I);
+    if (!MO.isReg()) continue;
+    Register Reg = MO.getReg();
+    if (Reg == 0 || !Register::isPhysicalRegister(Reg))
+      continue;
+    if (SinkTo->isLiveIn(Reg))
+      return true;
+  }
+  return false;
+}
+
+// Conservatively, clear any kill flags, since it's possible that they are no
+// longer correct.
+// Note that we have to clear the kill flags for any register this instruction
+// uses as we may sink over another instruction which currently kills the
+// used registers.
+void MachineSinking::AddRegsToClearKillFlags(MachineInstr &MI) {
+  for (MachineOperand &MO : MI.operands())
+    if (MO.isReg() && MO.isUse())
+      RegsToClearKillFlags.set(MO.getReg());
+}
+
+bool MachineSinking::IsSafeToMove(MachineLoop *L, MachineInstr &MI,
+                                  MachineBasicBlock *SinkTo) {
+  if (LI->getLoopFor(SinkTo) != L)
+    return false;
+
+  if (HasInstrSideEffects(MI, SinkTo)) {
+    LLVM_DEBUG(dbgs() << "LoopSink:   Instr has side-effects.\n");
+    return false;
+  }
+
+  auto End = MI.getParent()->instr_end();
+  auto It = MI.getIterator();
+
+  // 1) First, analyse all instruction from the current instruction I to the end
+  // of its block.
+  bool HasAliasedStore = false;
+  bool SawStore = false;
+  ++It;
+  for ( ; It != End; ++It) {
+    if (AreAliased(*It, MI, MI.getParent(), SinkTo, {}, SawStore,
+                   HasAliasedStore)) {
+      LLVM_DEBUG(dbgs() << "LoopSink:   Alias pair found!\n");
+      return false;
+    }
+  }
+
+  // This isSafeToMove check is not doing any alias analysis, but checks
+  // different instruction types, side-effects, etc. It uses 'SawStore' that is
+  // set in 1) which analyses the block of the sink instruction, and in 2) alias
+  // analysis of the loop blocks is performed.
+  SawStore = false;
+  if (!MI.isSafeToMove(AA, SawStore)) {
+    LLVM_DEBUG(dbgs() << "LoopSink:   Not safe to move!\n");
+    return false;
+  }
+
+  // 2) Next, check all instructions in the loop to see if there are aliases.
+  for (auto *BB : L->blocks()) {
+    for (auto &CurMI : *BB) {
+      if (AreAliased(CurMI, MI, MI.getParent(), SinkTo, {}, SawStore,
+                     HasAliasedStore)) {
+        LLVM_DEBUG(dbgs() << "LoopSink:   Alias found in loop: " << CurMI);
+        return false;
+      }
+    }
+  }
+  LLVM_DEBUG(dbgs() << "LoopSink:   Instruction not aliased, safe to move!\n");
+  return true;
+}
+
 /// Sink instructions into loops if profitable. This especially tries to prevent
 /// register spills caused by register pressure if there is little to no
 /// overhead moving instructions into loops.
 bool MachineSinking::SinkIntoLoop(MachineLoop *L, MachineInstr &I) {
   LLVM_DEBUG(dbgs() << "LoopSink: Finding sink block for: " << I);
   MachineBasicBlock *Preheader = L->getLoopPreheader();
   assert(Preheader && "Loop sink needs a preheader block");
   MachineBasicBlock *SinkBlock = nullptr;
   bool CanSink = true;
   const MachineOperand &MO = I.getOperand(0);
 
   for (MachineInstr &MI : MRI->use_instructions(MO.getReg())) {
     LLVM_DEBUG(dbgs() << "LoopSink:   Analysing use: " << MI);
     if (!L->contains(&MI)) {
       LLVM_DEBUG(dbgs() << "LoopSink:   Use not in loop, can't sink.\n");
       CanSink = false;
       break;
     }
 
     // FIXME: Come up with a proper cost model that estimates whether sinking
     // the instruction (and thus possibly executing it on every loop
     // iteration) is more expensive than a register.
-    // For now assumes that copies are cheap and thus almost always worth it.
-    if (!MI.isCopy()) {
-      LLVM_DEBUG(dbgs() << "LoopSink:   Use is not a copy\n");
-      CanSink = false;
-      break;
-    }
+
     if (!SinkBlock) {
       SinkBlock = MI.getParent();
       LLVM_DEBUG(dbgs() << "LoopSink:   Setting sink block to: "
                         << printMBBReference(*SinkBlock) << "\n");
       continue;
     }
     SinkBlock = DT->findNearestCommonDominator(SinkBlock, MI.getParent());
     if (!SinkBlock) {
bool MachineSinking::SinkIntoLoop(MachineLoop *L, MachineInstr &I) {
   if (!SinkBlock) {
     LLVM_DEBUG(dbgs() << "LoopSink: Not sinking, can't find sink block.\n");
     return false;
   }
   if (SinkBlock == Preheader) {
     LLVM_DEBUG(dbgs() << "LoopSink: Not sinking, sink block is the preheader\n");
     return false;
   }
+  if (!IsSafeToMove(L, I, SinkBlock)) {
+    LLVM_DEBUG(dbgs() << "LoopSink: Not safe to move\n");
+    return false;
+  }
 
   LLVM_DEBUG(dbgs() << "LoopSink: Sinking instruction!\n");
   SinkBlock->splice(SinkBlock->getFirstNonPHI(), Preheader, I);
 
   // The instruction is moved from its basic block, so do not retain the
   // debug information.
   assert(!I.isDebugInstr() && "Should not sink debug inst");
   I.setDebugLoc(DebugLoc());
+
+  AddRegsToClearKillFlags(I);
   return true;
 }
 
 /// SinkInstruction - Determine whether it is safe to sink the specified machine
 /// instruction out of its current block into a successor.
 bool MachineSinking::SinkInstruction(MachineInstr &MI, bool &SawStore,
                                      AllSuccsCache &AllSuccessors) {
   // Don't sink instructions that the target prefers not to sink.
bool MachineSinking::SinkInstruction(MachineInstr &MI, bool &SawStore,
   MachineBasicBlock *ParentBlock = MI.getParent();
   MachineBasicBlock *SuccToSinkTo =
       FindSuccToSinkTo(MI, ParentBlock, BreakPHIEdge, AllSuccessors);
 
   // If there are no outputs, it must have side-effects.
   if (!SuccToSinkTo)
     return false;
 
-  // If the instruction to move defines a dead physical register which is live
-  // when leaving the basic block, don't move it because it could turn into a
-  // "zombie" define of that preg. E.g., EFLAGS. (<rdar://problem/8030636>)
-  for (unsigned I = 0, E = MI.getNumOperands(); I != E; ++I) {
-    const MachineOperand &MO = MI.getOperand(I);
-    if (!MO.isReg()) continue;
-    Register Reg = MO.getReg();
-    if (Reg == 0 || !Register::isPhysicalRegister(Reg))
-      continue;
-    if (SuccToSinkTo->isLiveIn(Reg))
-      return false;
-  }
+  if (HasInstrSideEffects(MI, SuccToSinkTo))
 
   LLVM_DEBUG(dbgs() << "Sink instr " << MI << "\tinto block " << *SuccToSinkTo);
 
   // If the block has multiple predecessors, this is a critical edge.
   // Decide if we can sink along it or need to break the edge.
   if (SuccToSinkTo->pred_size() > 1) {
     // We cannot sink a load across a critical edge - there may be stores in
     // other code paths.
bool MachineSinking::SinkInstruction(MachineInstr &MI, bool &SawStore,
 
   // After sinking, some debug users may not be dominated any more. If possible,
   // copy-propagate their operands. As it's expensive, don't do this if there's
   // no debuginfo in the program.
   if (MI.getMF()->getFunction().getSubprogram() && MI.isCopy())
     SalvageUnsunkDebugUsersOfCopy(MI, SuccToSinkTo);
 
   performSink(MI, *SuccToSinkTo, InsertPos, DbgUsersToSink);
-
-  // Conservatively, clear any kill flags, since it's possible that they are no
-  // longer correct.
-  // Note that we have to clear the kill flags for any register this instruction
-  // uses as we may sink over another instruction which currently kills the
-  // used registers.
-  for (MachineOperand &MO : MI.operands()) {
-    if (MO.isReg() && MO.isUse())
-      RegsToClearKillFlags.set(MO.getReg()); // Remember to clear kill flags.
-  }
-
+  AddRegsToClearKillFlags(MI);
   return true;
 }
 
 void MachineSinking::SalvageUnsunkDebugUsersOfCopy(
     MachineInstr &MI, MachineBasicBlock *TargetBlock) {
   assert(MI.isCopy());
   assert(MI.getOperand(1).isReg());
 

llvm/test/CodeGen/AArch64/loop-sink.mir

 # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-# RUN: llc -mtriple aarch64 -run-pass=machine-sink  -sink-insts-to-avoid-spills %s -o - 2>&1 | FileCheck %s
+# RUN: llc -mtriple aarch64 -run-pass=machine-sink  -sink-insts-to-avoid-spills -verify-machineinstrs %s -o - 2>&1 | FileCheck %s
+
 --- |
   target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128"
   target triple = "aarch64"
 
   @A = external dso_local global [100 x i32], align 4
   %struct.A = type { i32, i32, i32, i32, i32, i32 }
+  @G = external dso_local local_unnamed_addr global i32, align 4
 
   define void @cant_sink_adds_call_in_block(i8* nocapture readonly %input, %struct.A* %a) {
     %1 = getelementptr inbounds %struct.A, %struct.A* %a, i64 0, i32 1
     %2 = getelementptr inbounds %struct.A, %struct.A* %a, i64 0, i32 2
     %3 = getelementptr inbounds %struct.A, %struct.A* %a, i64 0, i32 3
     %4 = getelementptr inbounds %struct.A, %struct.A* %a, i64 0, i32 4
     %5 = getelementptr inbounds %struct.A, %struct.A* %a, i64 0, i32 5
     %scevgep = getelementptr i8, i8* %input, i64 1
for.body:                                         ; preds = %for.body, %for.body.preheader
     %lsr.iv = phi i32 [ %n, %for.body.preheader ], [ %lsr.iv.next, %for.body ]
     %sum.065 = phi i32 [ %div, %for.body ], [ %n, %for.body.preheader ]
     %div = sdiv i32 %sum.065, %sum.065
     %lsr.iv.next = add i32 %lsr.iv, -1
     %exitcond.not = icmp eq i32 %lsr.iv.next, 0
     br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
   }
 
-  define i32 @use_is_not_a_copy(i32 %n) {
+  define i32 @do_sink_use_is_not_a_copy(i32 %n) {
   entry:
     %cmp63 = icmp sgt i32 %n, 0
     br i1 %cmp63, label %for.body.preheader, label %for.cond.cleanup
 
   for.body.preheader:                               ; preds = %entry
     %0 = load i32, i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0), align 4
     br label %for.body
 
   for.cond.cleanup:                                 ; preds = %for.body, %entry
     %sum.0.lcssa = phi i32 [ %n, %entry ], [ %div, %for.body ]
     ret i32 %sum.0.lcssa
 
   for.body:                                         ; preds = %for.body, %for.body.preheader
     %lsr.iv = phi i32 [ %n, %for.body.preheader ], [ %lsr.iv.next, %for.body ]
     %sum.065 = phi i32 [ %div, %for.body ], [ %n, %for.body.preheader ]
     %div = sdiv i32 %sum.065, %0
     %lsr.iv.next = add i32 %lsr.iv, -1
     %exitcond.not = icmp eq i32 %lsr.iv.next, 0
     br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
   }
 
-  define dso_local void @sink_add(i32* noalias nocapture readonly %read, i32* noalias nocapture %write, i32 %n) local_unnamed_addr #0 {
+  define dso_local void @cant_sink_load_add_chain_loop_phi_use(i32* noalias nocapture readonly %read, i32* noalias nocapture %write, i32 %n) local_unnamed_addr #0 {
   entry:
     %0 = load i32, i32* %read, align 4, !tbaa !6
     %cmp10 = icmp sgt i32 %n, 0
     br i1 %cmp10, label %for.body.preheader, label %for.cond.cleanup
 
   for.body.preheader:                               ; preds = %entry
     %1 = add i32 %0, 42
     br label %for.body
for.body:                                         ; preds = %for.body.preheader, %for.body
     %sum.011 = phi i32 [ %div, %for.body ], [ %n, %for.body.preheader ]
     %div = sdiv i32 %sum.011, %lsr.iv1
     %lsr.iv.next = add i32 %lsr.iv, -1
     %lsr.iv.next2 = add i32 %lsr.iv1, 1
     %exitcond.not = icmp eq i32 %lsr.iv.next, 0
     br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
   }
 
-  define dso_local void @store_after_add(i32* noalias nocapture readonly %read, i32* noalias nocapture %write, i32* nocapture %store, i32 %n) local_unnamed_addr #0 {
+  define dso_local void @cant_sink_multi_block_loop_with_call(i32* noalias nocapture %read, i32* noalias nocapture %write, i32* nocapture readnone %store, i32 %n) local_unnamed_addr #0 {
   entry:
-    %0 = load i32, i32* %read, align 4, !tbaa !6
-    %cmp10 = icmp sgt i32 %n, 0
-    br i1 %cmp10, label %for.body.preheader, label %for.cond.cleanup
+    %0 = load i32, i32* %read, align 4
+    store i32 %n, i32* %read, align 4
+    %cmp12 = icmp sgt i32 %n, 0
+    br i1 %cmp12, label %for.body.lr.ph, label %for.cond.cleanup
+
+  for.body.lr.ph:                                   ; preds = %entry
+    %1 = load i32, i32* @G, align 4
+    %2 = icmp eq i32 %1, 0
+    br i1 %2, label %for.body.us.preheader, label %for.body.preheader
+
+  for.body.preheader:                               ; preds = %for.body.lr.ph
+    %3 = add i32 %0, 42
+    br label %for.body
+
+  for.body.us.preheader:                            ; preds = %for.body.lr.ph
+    %4 = add i32 %n, -1
+    %5 = add i32 %0, 42
+    br label %for.body.us
+
+  for.body.us:                                      ; preds = %for.body.us.preheader, %for.inc.us.for.body.us_crit_edge
+    %lsr.iv2 = phi i32 [ %5, %for.body.us.preheader ], [ %lsr.iv.next3, %for.inc.us.for.body.us_crit_edge ]
+    %lsr.iv = phi i32 [ %4, %for.body.us.preheader ], [ %lsr.iv.next, %for.inc.us.for.body.us_crit_edge ]
+    %6 = phi i32 [ %.pre, %for.inc.us.for.body.us_crit_edge ], [ 0, %for.body.us.preheader ]
+    %sum.013.us = phi i32 [ %sum.1.us, %for.inc.us.for.body.us_crit_edge ], [ %n, %for.body.us.preheader ]
+    %tobool.not.us = icmp eq i32 %6, 0
+    br i1 %tobool.not.us, label %if.else.us, label %if.then.us
+
+  if.then.us:                                       ; preds = %for.body.us
+    %div.us = sdiv i32 %sum.013.us, %lsr.iv2
+    br label %for.inc.us
+
+  if.else.us:                                       ; preds = %for.body.us
+    tail call void @H() #2
+    br label %for.inc.us
+
+  for.inc.us:                                       ; preds = %if.else.us, %if.then.us
+    %sum.1.us = phi i32 [ %div.us, %if.then.us ], [ %sum.013.us, %if.else.us ]
+    %exitcond.not = icmp eq i32 %lsr.iv, 0
+    br i1 %exitcond.not, label %for.cond.cleanup, label %for.inc.us.for.body.us_crit_edge, !llvm.loop !10
+
+  for.inc.us.for.body.us_crit_edge:                 ; preds = %for.inc.us
+    %.pre = load i32, i32* @G, align 4
+    %lsr.iv.next = add i32 %lsr.iv, -1
+    %lsr.iv.next3 = add i32 %lsr.iv2, 1
+    br label %for.body.us
+
+  for.cond.cleanup:                                 ; preds = %for.body, %for.inc.us, %entry
+    %sum.0.lcssa = phi i32 [ %n, %entry ], [ %sum.1.us, %for.inc.us ], [ %div, %for.body ]
+    store i32 %sum.0.lcssa, i32* %write, align 4, !tbaa !6
+    ret void
+
+  for.body:                                         ; preds = %for.body.preheader, %for.body
+    %lsr.iv6 = phi i32 [ %3, %for.body.preheader ], [ %lsr.iv.next7, %for.body ]
+    %lsr.iv4 = phi i32 [ %n, %for.body.preheader ], [ %lsr.iv.next5, %for.body ]
+    %sum.013 = phi i32 [ %div, %for.body ], [ %n, %for.body.preheader ]
+    %div = sdiv i32 %sum.013, %lsr.iv6
+    %lsr.iv.next5 = add i32 %lsr.iv4, -1
+    %lsr.iv.next7 = add i32 %lsr.iv6, 1
+    %exitcond17.not = icmp eq i32 %lsr.iv.next5, 0
+    br i1 %exitcond17.not, label %for.cond.cleanup, label %for.body
+  }
+
+  define dso_local void @do_sink_load_add(float* noalias nocapture readonly %read, float* noalias nocapture %write, float* nocapture readnone %store, i32 %n) local_unnamed_addr #0 {
+  entry:
+    %0 = load float, float* %read, align 4, !tbaa !6
+    %add = fadd fast float %0, 4.200000e+01
+    %cmp8 = icmp sgt i32 %n, 0
+    br i1 %cmp8, label %for.body.preheader, label %for.cond.cleanup
 
   for.body.preheader:                               ; preds = %entry
-    %1 = add i32 %0, 42
-    store i32 43, i32* %store, align 4, !tbaa !6
     br label %for.body
 
   for.cond.cleanup:                                 ; preds = %for.body, %entry
-    %sum.0.lcssa = phi i32 [ %n, %entry ], [ %div, %for.body ]
-    store i32 %sum.0.lcssa, i32* %write, align 4, !tbaa !6
+    %sum.0.lcssa = phi float [ 0.000000e+00, %entry ], [ %add1, %for.body ]
+    store float %sum.0.lcssa, float* %write, align 4
     ret void
 
   for.body:                                         ; preds = %for.body.preheader, %for.body
-    %lsr.iv1 = phi i32 [ %1, %for.body.preheader ], [ %lsr.iv.next2, %for.body ]
     %lsr.iv = phi i32 [ %n, %for.body.preheader ], [ %lsr.iv.next, %for.body ]
-    %sum.011 = phi i32 [ %div, %for.body ], [ %n, %for.body.preheader ]
-    %div = sdiv i32 %sum.011, %lsr.iv1
+    %sum.09 = phi float [ %add1, %for.body ], [ 0.000000e+00, %for.body.preheader ]
+    %add1 = fadd fast float %add, %sum.09
     %lsr.iv.next = add i32 %lsr.iv, -1
-    %lsr.iv.next2 = add i32 %lsr.iv1, 1
     %exitcond.not = icmp eq i32 %lsr.iv.next, 0
-    br i1 %exitcond.not, label %for.cond.cleanup, label %for.body, !llvm.loop !10
+    br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
   }
 
-  define dso_local void @aliased_store_after_add(i32* noalias nocapture readonly %read, i32* noalias nocapture %write, i32* nocapture %store, i32 %n) local_unnamed_addr #0 {
+  define dso_local void @do_sink_no_aliased_store(float* noalias nocapture readonly %read, float* noalias nocapture %write, float* nocapture %store, i32 %n, float %m) local_unnamed_addr #0 {
   entry:
-    %0 = load i32, i32* %read, align 4, !tbaa !6
-    %cmp10 = icmp sgt i32 %n, 0
-    br i1 %cmp10, label %for.body.preheader, label %for.cond.cleanup
+    %cmp6 = icmp sgt i32 %n, 0
+    br i1 %cmp6, label %for.body.preheader, label %for.cond.cleanup
 
   for.body.preheader:                               ; preds = %entry
-    %1 = add i32 %0, 42
-    store i32 43, i32* %read, align 4, !tbaa !6
+    %0 = load float, float* %read, align 4
+    store float %m, float* %store, align 4
     br label %for.body
 
   for.cond.cleanup:                                 ; preds = %for.body, %entry
-    %sum.0.lcssa = phi i32 [ %n, %entry ], [ %div, %for.body ]
-    store i32 %sum.0.lcssa, i32* %write, align 4, !tbaa !6
+    %sum.0.lcssa = phi float [ 0.000000e+00, %entry ], [ %add, %for.body ]
+    store float %sum.0.lcssa, float* %write, align 4
     ret void
 
   for.body:                                         ; preds = %for.body.preheader, %for.body
-    %lsr.iv1 = phi i32 [ %1, %for.body.preheader ], [ %lsr.iv.next2, %for.body ]
     %lsr.iv = phi i32 [ %n, %for.body.preheader ], [ %lsr.iv.next, %for.body ]
-    %sum.011 = phi i32 [ %div, %for.body ], [ %n, %for.body.preheader ]
-    %div = sdiv i32 %sum.011, %lsr.iv1
+    %sum.07 = phi float [ %add, %for.body ], [ 0.000000e+00, %for.body.preheader ]
+    %add = fadd fast float %sum.07, %0
     %lsr.iv.next = add i32 %lsr.iv, -1
-    %lsr.iv.next2 = add i32 %lsr.iv1, 1
     %exitcond.not = icmp eq i32 %lsr.iv.next, 0
-    br i1 %exitcond.not, label %for.cond.cleanup, label %for.body, !llvm.loop !10
+    br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
   }
 
+  define dso_local void @cant_sink_load_aliased_store(float* nocapture readonly %read, float* nocapture %write, float* nocapture %store, i32 %n, float %m) local_unnamed_addr #0 {
+  entry:
+    %cmp6 = icmp sgt i32 %n, 0
+    br i1 %cmp6, label %for.body.preheader, label %for.cond.cleanup
+
+  for.body.preheader:                               ; preds = %entry
+    %0 = load float, float* %read, align 4
+    store float %m, float* %store, align 4
+    br label %for.body
+
+  for.cond.cleanup:                                 ; preds = %for.body, %entry
+    %sum.0.lcssa = phi float [ 0.000000e+00, %entry ], [ %add, %for.body ]
+    store float %sum.0.lcssa, float* %write, align 4
+    ret void
+
+  for.body:                                         ; preds = %for.body.preheader, %for.body
+    %lsr.iv = phi i32 [ %n, %for.body.preheader ], [ %lsr.iv.next, %for.body ]
+    %sum.07 = phi float [ %add, %for.body ], [ 0.000000e+00, %for.body.preheader ]
+    %add = fadd fast float %sum.07, %0
+    %lsr.iv.next = add i32 %lsr.iv, -1
+    %exitcond.not = icmp eq i32 %lsr.iv.next, 0
+    br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
+  }
+
+  define dso_local void @cant_sink_aliased_store_in_loop(float* nocapture readonly %read, float* nocapture %write, float* nocapture %store, i32 %n, float %m) local_unnamed_addr #0 {
+  entry:
+    %0 = load float, float* %read, align 4, !tbaa !6
+    %cmp6 = icmp sgt i32 %n, 0
+    br i1 %cmp6, label %for.body.preheader, label %for.cond.cleanup
+
+  for.body.preheader:                               ; preds = %entry
+    br label %for.body
+
+  for.cond.cleanup:                                 ; preds = %for.body, %entry
+    %sum.0.lcssa = phi float [ 0.000000e+00, %entry ], [ %add, %for.body ]
+    store float %sum.0.lcssa, float* %write, align 4
+    ret void
+
+  for.body:                                         ; preds = %for.body.preheader, %for.body
+    %lsr.iv = phi i32 [ %n, %for.body.preheader ], [ %lsr.iv.next, %for.body ]
+    %sum.07 = phi float [ %add, %for.body ], [ 0.000000e+00, %for.body.preheader ]
+    %add = fadd fast float %sum.07, %0
+    store float %m, float* %store, align 4
+    %lsr.iv.next = add i32 %lsr.iv, -1
+    %exitcond.not = icmp eq i32 %lsr.iv.next, 0
+    br i1 %exitcond.not, label %for.cond.cleanup, label %for.body
+  }
 
   declare i32 @use(i32)
   declare void @_Z6assignPj(i32*)
+  declare void @H()
 
   !6 = !{!7, !7, i64 0}
   !7 = !{!"int", !8, i64 0}
   !8 = !{!"omnipotent char", !9, i64 0}
   !9 = !{!"Simple C/C++ TBAA"}
   !10 = distinct !{!10, !11}
   !11 = !{!"llvm.loop.mustprogress"}
 
bb.3.for.body:
     %5:gpr32all = COPY %13
     %14:gpr32 = SUBSWri %3, 1, 0, implicit-def $nzcv
     %6:gpr32all = COPY %14
     Bcc 0, %bb.2, implicit $nzcv
     B %bb.3
 
 ...
 ---
-name:            use_is_not_a_copy
+name:            do_sink_use_is_not_a_copy
 alignment:       4
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 hasWinCFI:       false
frameInfo:
   restorePoint:    ''
 fixedStack:      []
 stack:           []
 callSites:       []
 debugValueSubstitutions: []
 constants:       []
 machineFunctionInfo: {}
 body:             |
-  ; CHECK-LABEL: name: use_is_not_a_copy
+  ; CHECK-LABEL: name: do_sink_use_is_not_a_copy
   ; CHECK: bb.0.entry:
   ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
   ; CHECK:   liveins: $w0
   ; CHECK:   [[COPY:%[0-9]+]]:gpr32common = COPY $w0
   ; CHECK:   [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
   ; CHECK:   Bcc 11, %bb.2, implicit $nzcv
   ; CHECK:   B %bb.1
   ; CHECK: bb.1.for.body.preheader:
   ; CHECK:   successors: %bb.3(0x80000000)
-  ; CHECK:   [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @A
-  ; CHECK:   [[LDRWui:%[0-9]+]]:gpr32 = LDRWui killed [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @A :: (dereferenceable load 4 from `i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0)`)
   ; CHECK:   B %bb.3
   ; CHECK: bb.2.for.cond.cleanup:
   ; CHECK:   [[PHI:%[0-9]+]]:gpr32all = PHI [[COPY]], %bb.0, %4, %bb.3
   ; CHECK:   $w0 = COPY [[PHI]]
   ; CHECK:   RET_ReallyLR implicit $w0
   ; CHECK: bb.3.for.body:
   ; CHECK:   successors: %bb.2(0x04000000), %bb.3(0x7c000000)
   ; CHECK:   [[PHI1:%[0-9]+]]:gpr32sp = PHI [[COPY]], %bb.1, %5, %bb.3
   ; CHECK:   [[PHI2:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.1, %4, %bb.3
+  ; CHECK:   [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @A
+  ; CHECK:   [[LDRWui:%[0-9]+]]:gpr32 = LDRWui killed [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @A :: (dereferenceable load 4 from `i32* getelementptr inbounds ([100 x i32], [100 x i32]* @A, i64 0, i64 0)`)
   ; CHECK:   [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[PHI2]], [[LDRWui]]
   ; CHECK:   [[COPY1:%[0-9]+]]:gpr32all = COPY [[SDIVWr]]
   ; CHECK:   [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI1]], 1, 0, implicit-def $nzcv
   ; CHECK:   [[COPY2:%[0-9]+]]:gpr32all = COPY [[SUBSWri1]]
   ; CHECK:   Bcc 0, %bb.2, implicit $nzcv
   ; CHECK:   B %bb.3
   bb.0.entry:
     successors: %bb.1(0x50000000), %bb.2(0x30000000)
bb.3.for.body:
     %4:gpr32all = COPY %10
     %11:gpr32 = SUBSWri %2, 1, 0, implicit-def $nzcv
     %5:gpr32all = COPY %11
     Bcc 0, %bb.2, implicit $nzcv
     B %bb.3
 
 ...
 ---
-name:            sink_add
+name:            cant_sink_load_add_chain_loop_phi_use
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 hasWinCFI:       false
frameInfo:
   restorePoint:    ''
 fixedStack:      []
 stack:           []
 callSites:       []
 debugValueSubstitutions: []
 constants:       []
 machineFunctionInfo: {}
 body:             |
-  ; CHECK-LABEL: name: sink_add
+  ; CHECK-LABEL: name: cant_sink_load_add_chain_loop_phi_use
   ; CHECK: bb.0.entry:
   ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
   ; CHECK:   liveins: $x0, $x1, $w2
   ; CHECK:   [[COPY:%[0-9]+]]:gpr32common = COPY $w2
   ; CHECK:   [[COPY1:%[0-9]+]]:gpr64common = COPY $x1
   ; CHECK:   [[COPY2:%[0-9]+]]:gpr64common = COPY $x0
   ; CHECK:   [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
   ; CHECK:   Bcc 11, %bb.2, implicit $nzcv
bb.3.for.body:
     %7:gpr32all = COPY %16
     %17:gpr32sp = ADDWri %3, 1, 0
     %8:gpr32all = COPY %17
     Bcc 0, %bb.2, implicit $nzcv
     B %bb.3
 
 ...
 ---
-name:            store_after_add
+name:            cant_sink_multi_block_loop_with_call
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 hasWinCFI:       false
 registers:
   - { id: 0, class: gpr32sp, preferred-register: '' }
   - { id: 1, class: gpr32all, preferred-register: '' }
-  - { id: 2, class: gpr32, preferred-register: '' }
-  - { id: 3, class: gpr32common, preferred-register: '' }
-  - { id: 4, class: gpr32sp, preferred-register: '' }
-  - { id: 5, class: gpr32, preferred-register: '' }
-  - { id: 6, class: gpr32all, preferred-register: '' }
-  - { id: 7, class: gpr32all, preferred-register: '' }
+  - { id: 2, class: gpr32all, preferred-register: '' }
+  - { id: 3, class: gpr32all, preferred-register: '' }
+  - { id: 4, class: gpr32common, preferred-register: '' }
+  - { id: 5, class: gpr32common, preferred-register: '' }
+  - { id: 6, class: gpr32, preferred-register: '' }
+  - { id: 7, class: gpr32, preferred-register: '' }
   - { id: 8, class: gpr32all, preferred-register: '' }
-  - { id: 9, class: gpr64common, preferred-register: '' }
-  - { id: 10, class: gpr64common, preferred-register: '' }
-  - { id: 11, class: gpr64common, preferred-register: '' }
-  - { id: 12, class: gpr32common, preferred-register: '' }
-  - { id: 13, class: gpr32common, preferred-register: '' }
+  - { id: 9, class: gpr32all, preferred-register: '' }
+  - { id: 10, class: gpr32all, preferred-register: '' }
+  - { id: 11, class: gpr32all, preferred-register: '' }
+  - { id: 12, class: gpr32all, preferred-register: '' }
+  - { id: 13, class: gpr32, preferred-register: '' }
+  - { id: 14, class: gpr32common, preferred-register: '' }
+  - { id: 15, class: gpr32sp, preferred-register: '' }
+  - { id: 16, class: gpr32, preferred-register: '' }
+  - { id: 17, class: gpr32all, preferred-register: '' }
+  - { id: 18, class: gpr32all, preferred-register: '' }
+  - { id: 19, class: gpr32all, preferred-register: '' }
+  - { id: 20, class: gpr64common, preferred-register: '' }
+  - { id: 21, class: gpr64common, preferred-register: '' }
+  - { id: 22, class: gpr64, preferred-register: '' }
+  - { id: 23, class: gpr32common, preferred-register: '' }
+  - { id: 24, class: gpr32common, preferred-register: '' }
+  - { id: 25, class: gpr32, preferred-register: '' }
+  - { id: 26, class: gpr64common, preferred-register: '' }
+  - { id: 27, class: gpr32, preferred-register: '' }
+  - { id: 28, class: gpr32sp, preferred-register: '' }
+  - { id: 29, class: gpr32, preferred-register: '' }
+  - { id: 30, class: gpr32, preferred-register: '' }
+  - { id: 31, class: gpr32sp, preferred-register: '' }
+  - { id: 32, class: gpr32all, preferred-register: '' }
+  - { id: 33, class: gpr32, preferred-register: '' }
+  - { id: 34, class: gpr32sp, preferred-register: '' }
+  - { id: 35, class: gpr32all, preferred-register: '' }
+  - { id: 36, class: gpr32, preferred-register: '' }
+  - { id: 37, class: gpr64common, preferred-register: '' }
+  - { id: 38, class: gpr32, preferred-register: '' }
+  - { id: 39, class: gpr32, preferred-register: '' }
+  - { id: 40, class: gpr32sp, preferred-register: '' }
+liveins:
+  - { reg: '$x0', virtual-reg: '%20' }
+  - { reg: '$x1', virtual-reg: '%21' }
+  - { reg: '$w3', virtual-reg: '%23' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    1
+  adjustsStack:    true
+  hasCalls:        true
+  stackProtector:  ''
+  maxCallFrameSize: 0
+  cvBytesOfCalleeSavedRegisters: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  localFrameSize:  0
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      []
+stack:           []
+callSites:       []
+debugValueSubstitutions: []
+constants:       []
+machineFunctionInfo: {}
+body:             |
+  ; CHECK-LABEL: name: cant_sink_multi_block_loop_with_call
+  ; CHECK: bb.0.entry:
+  ; CHECK:   successors: %bb.1(0x50000000), %bb.9(0x30000000)
+  ; CHECK:   liveins: $x0, $x1, $w3
+  ; CHECK:   [[COPY:%[0-9]+]]:gpr32common = COPY $w3
+  ; CHECK:   [[COPY1:%[0-9]+]]:gpr64common = COPY $x1
+  ; CHECK:   [[COPY2:%[0-9]+]]:gpr64common = COPY $x0
+  ; CHECK:   [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY2]], 0 :: (load 4 from %ir.read, !tbaa !0)
+  ; CHECK:   STRWui [[COPY]], [[COPY2]], 0 :: (store 4 into %ir.read, !tbaa !0)
+  ; CHECK:   [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
+  ; CHECK:   Bcc 11, %bb.9, implicit $nzcv
+  ; CHECK:   B %bb.1
+  ; CHECK: bb.1.for.body.lr.ph:
+  ; CHECK:   successors: %bb.3(0x30000000), %bb.2(0x50000000)
+  ; CHECK:   [[ADRP:%[0-9]+]]:gpr64common = ADRP target-flags(aarch64-page) @G
+  ; CHECK:   [[LDRWui1:%[0-9]+]]:gpr32 = LDRWui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @G :: (dereferenceable load 4 from @G, !tbaa !0)
+  ; CHECK:   CBZW killed [[LDRWui1]], %bb.3
+  ; CHECK:   B %bb.2
+  ; CHECK: bb.2.for.body.preheader:
+  ; CHECK:   successors: %bb.10(0x80000000)
+  ; CHECK:   [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[LDRWui]], 42, 0
+  ; CHECK:   [[COPY3:%[0-9]+]]:gpr32all = COPY [[ADDWri]]
+  ; CHECK:   B %bb.10
+  ; CHECK: bb.3.for.body.us.preheader:
+  ; CHECK:   successors: %bb.4(0x80000000)
+  ; CHECK:   [[COPY4:%[0-9]+]]:gpr32all = COPY [[SUBSWri]]
+  ; CHECK:   [[ADDWri1:%[0-9]+]]:gpr32sp = ADDWri [[LDRWui]], 42, 0
+  ; CHECK:   [[COPY5:%[0-9]+]]:gpr32all = COPY $wzr
+  ; CHECK:   [[COPY6:%[0-9]+]]:gpr32all = COPY [[COPY5]]
+  ; CHECK:   [[COPY7:%[0-9]+]]:gpr32all = COPY [[ADDWri1]]
+  ; CHECK: bb.4.for.body.us:
+  ; CHECK:   successors: %bb.6(0x30000000), %bb.5(0x50000000)
+  ; CHECK:   [[PHI:%[0-9]+]]:gpr32common = PHI [[COPY7]], %bb.3, %12, %bb.8
+  ; CHECK:   [[PHI1:%[0-9]+]]:gpr32common = PHI [[COPY4]], %bb.3, %11, %bb.8
+  ; CHECK:   [[PHI2:%[0-9]+]]:gpr32 = PHI [[COPY6]], %bb.3, %10, %bb.8
+  ; CHECK:   [[PHI3:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.3, %9, %bb.8
+  ; CHECK:   CBZW [[PHI2]], %bb.6
+  ; CHECK:   B %bb.5
+  ; CHECK: bb.5.if.then.us:
+  ; CHECK:   successors: %bb.7(0x80000000)
+  ; CHECK:   [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[PHI3]], [[PHI]]
+  ; CHECK:   [[COPY8:%[0-9]+]]:gpr32all = COPY [[SDIVWr]]
+  ; CHECK:   B %bb.7
+  ; CHECK: bb.6.if.else.us:
+  ; CHECK:   successors: %bb.7(0x80000000)
+  ; CHECK:   ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+  ; CHECK:   BL @H, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
+  ; CHECK:   ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+  ; CHECK: bb.7.for.inc.us:
+  ; CHECK:   successors: %bb.9(0x04000000), %bb.8(0x7c000000)
+  ; CHECK:   [[PHI4:%[0-9]+]]:gpr32all = PHI [[COPY8]], %bb.5, [[PHI3]], %bb.6
+  ; CHECK:   CBZW [[PHI1]], %bb.9
+  ; CHECK:   B %bb.8
+  ; CHECK: bb.8.for.inc.us.for.body.us_crit_edge:
+  ; CHECK:   successors: %bb.4(0x80000000)
+  ; CHECK:   [[LDRWui2:%[0-9]+]]:gpr32 = LDRWui [[ADRP]], target-flags(aarch64-pageoff, aarch64-nc) @G :: (dereferenceable load 4 from @G, !tbaa !0)
+  ; CHECK:   [[COPY9:%[0-9]+]]:gpr32all = COPY [[LDRWui2]]
+  ; CHECK:   [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI1]], 1, 0, implicit-def dead $nzcv
+  ; CHECK:   [[COPY10:%[0-9]+]]:gpr32all = COPY [[SUBSWri1]]
+  ; CHECK:   [[ADDWri2:%[0-9]+]]:gpr32sp = ADDWri [[PHI]], 1, 0
+  ; CHECK:   [[COPY11:%[0-9]+]]:gpr32all = COPY [[ADDWri2]]
+  ; CHECK:   B %bb.4
+  ; CHECK: bb.9.for.cond.cleanup:
+  ; CHECK:   [[PHI5:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.0, %17, %bb.10, [[PHI4]], %bb.7
+  ; CHECK:   STRWui [[PHI5]], [[COPY1]], 0 :: (store 4 into %ir.write, !tbaa !0)
+  ; CHECK:   RET_ReallyLR
+  ; CHECK: bb.10.for.body:
+  ; CHECK:   successors: %bb.9(0x04000000), %bb.10(0x7c000000)
+  ; CHECK:   [[PHI6:%[0-9]+]]:gpr32common = PHI [[COPY3]], %bb.2, %19, %bb.10
+  ; CHECK:   [[PHI7:%[0-9]+]]:gpr32sp = PHI [[COPY]], %bb.2, %18, %bb.10
+  ; CHECK:   [[PHI8:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.2, %17, %bb.10
+  ; CHECK:   [[SDIVWr1:%[0-9]+]]:gpr32 = SDIVWr [[PHI8]], [[PHI6]]
+  ; CHECK:   [[COPY12:%[0-9]+]]:gpr32all = COPY [[SDIVWr1]]
+  ; CHECK:   [[SUBSWri2:%[0-9]+]]:gpr32 = SUBSWri [[PHI7]], 1, 0, implicit-def $nzcv
+  ; CHECK:   [[COPY13:%[0-9]+]]:gpr32all = COPY [[SUBSWri2]]
+  ; CHECK:   [[ADDWri3:%[0-9]+]]:gpr32sp = ADDWri [[PHI6]], 1, 0
+  ; CHECK:   [[COPY14:%[0-9]+]]:gpr32all = COPY [[ADDWri3]]
+  ; CHECK:   Bcc 0, %bb.9, implicit $nzcv
+  ; CHECK:   B %bb.10
+  bb.0.entry:
+    successors: %bb.1(0x50000000), %bb.9(0x30000000)
+    liveins: $x0, $x1, $w3
+
+    %23:gpr32common = COPY $w3
+    %21:gpr64common = COPY $x1
+    %20:gpr64common = COPY $x0
+    %24:gpr32common = LDRWui %20, 0 :: (load 4 from %ir.read, !tbaa !6)
+    STRWui %23, %20, 0 :: (store 4 into %ir.read, !tbaa !6)
+    %25:gpr32 = SUBSWri %23, 1, 0, implicit-def $nzcv
+    Bcc 11, %bb.9, implicit $nzcv
+    B %bb.1
+
+  bb.1.for.body.lr.ph:
+    successors: %bb.3(0x30000000), %bb.2(0x50000000)
+
+    %26:gpr64common = ADRP target-flags(aarch64-page) @G
+    %27:gpr32 = LDRWui %26, target-flags(aarch64-pageoff, aarch64-nc) @G :: (dereferenceable load 4 from @G, !tbaa !6)
+    CBZW killed %27, %bb.3
+    B %bb.2
+
+  bb.2.for.body.preheader:
+    successors: %bb.10(0x80000000)
+
+    %28:gpr32sp = ADDWri %24, 42, 0
+    %1:gpr32all = COPY %28
+    B %bb.10
+
+  bb.3.for.body.us.preheader:
+    successors: %bb.4(0x80000000)
+
+    %2:gpr32all = COPY %25
+    %34:gpr32sp = ADDWri %24, 42, 0
+    %35:gpr32all = COPY $wzr
+    %32:gpr32all = COPY %35
+    %3:gpr32all = COPY %34
+
+  bb.4.for.body.us:
+    successors: %bb.6(0x30000000), %bb.5(0x50000000)
+
+    %4:gpr32common = PHI %3, %bb.3, %12, %bb.8
+    %5:gpr32common = PHI %2, %bb.3, %11, %bb.8
+    %6:gpr32 = PHI %32, %bb.3, %10, %bb.8
+    %7:gpr32 = PHI %23, %bb.3, %9, %bb.8
+    CBZW %6, %bb.6
+    B %bb.5
+
+  bb.5.if.then.us:
+    successors: %bb.7(0x80000000)
+
+    %36:gpr32 = SDIVWr %7, %4
+    %8:gpr32all = COPY %36
+    B %bb.7
+
+  bb.6.if.else.us:
+    successors: %bb.7(0x80000000)
+
+    ADJCALLSTACKDOWN 0, 0, implicit-def dead $sp, implicit $sp
+    BL @H, csr_aarch64_aapcs, implicit-def dead $lr, implicit $sp, implicit-def $sp
+    ADJCALLSTACKUP 0, 0, implicit-def dead $sp, implicit $sp
+
+  bb.7.for.inc.us:
+    successors: %bb.9(0x04000000), %bb.8(0x7c000000)
+
+    %9:gpr32all = PHI %8, %bb.5, %7, %bb.6
+    CBZW %5, %bb.9
+    B %bb.8
+
+  bb.8.for.inc.us.for.body.us_crit_edge:
+    successors: %bb.4(0x80000000)
+
+    %38:gpr32 = LDRWui %26, target-flags(aarch64-pageoff, aarch64-nc) @G :: (dereferenceable load 4 from @G, !tbaa !6)
+    %10:gpr32all = COPY %38
+    %39:gpr32 = SUBSWri %5, 1, 0, implicit-def dead $nzcv
+    %11:gpr32all = COPY %39
+    %40:gpr32sp = ADDWri %4, 1, 0
+    %12:gpr32all = COPY %40
+    B %bb.4
+
+  bb.9.for.cond.cleanup:
+    %13:gpr32 = PHI %23, %bb.0, %17, %bb.10, %9, %bb.7
+    STRWui %13, %21, 0 :: (store 4 into %ir.write, !tbaa !6)
+    RET_ReallyLR
+
+  bb.10.for.body:
+    successors: %bb.9(0x04000000), %bb.10(0x7c000000)
+
+    %14:gpr32common = PHI %1, %bb.2, %19, %bb.10
+    %15:gpr32sp = PHI %23, %bb.2, %18, %bb.10
+    %16:gpr32 = PHI %23, %bb.2, %17, %bb.10
+    %29:gpr32 = SDIVWr %16, %14
+    %17:gpr32all = COPY %29
+    %30:gpr32 = SUBSWri %15, 1, 0, implicit-def $nzcv
+    %18:gpr32all = COPY %30
+    %31:gpr32sp = ADDWri %14, 1, 0
+    %19:gpr32all = COPY %31
+    Bcc 0, %bb.9, implicit $nzcv
+    B %bb.10
+
+...
+---
+name:            do_sink_load_add
+alignment:       16
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+registers:
+  - { id: 0, class: fpr32, preferred-register: '' }
+  - { id: 1, class: fpr32, preferred-register: '' }
+  - { id: 2, class: gpr32sp, preferred-register: '' }
+  - { id: 3, class: fpr32, preferred-register: '' }
+  - { id: 4, class: fpr32, preferred-register: '' }
+  - { id: 5, class: gpr32all, preferred-register: '' }
+  - { id: 6, class: gpr64common, preferred-register: '' }
+  - { id: 7, class: gpr64common, preferred-register: '' }
+  - { id: 8, class: gpr64, preferred-register: '' }
+  - { id: 9, class: gpr32common, preferred-register: '' }
+  - { id: 10, class: fpr32, preferred-register: '' }
+  - { id: 11, class: fpr32, preferred-register: '' }
+  - { id: 12, class: gpr32, preferred-register: '' }
+  - { id: 13, class: fpr32, preferred-register: '' }
   - { id: 14, class: gpr32, preferred-register: '' }
-  - { id: 15, class: gpr32, preferred-register: '' }
-  - { id: 16, class: gpr32sp, preferred-register: '' }
-  - { id: 17, class: gpr32, preferred-register: '' }
-  - { id: 18, class: gpr32, preferred-register: '' }
-  - { id: 19, class: gpr32sp, preferred-register: '' }
+  - { id: 15, class: fpr32, preferred-register: '' }
+  - { id: 16, class: gpr32, preferred-register: '' }
 liveins:
-  - { reg: '$x0', virtual-reg: '%9' }
-  - { reg: '$x1', virtual-reg: '%10' }
-  - { reg: '$x2', virtual-reg: '%11' }
-  - { reg: '$w3', virtual-reg: '%12' }
+  - { reg: '$x0', virtual-reg: '%6' }
+  - { reg: '$x1', virtual-reg: '%7' }
+  - { reg: '$w3', virtual-reg: '%9' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
frameInfo:
   restorePoint:    ''
 fixedStack:      []
 stack:           []
 callSites:       []
 debugValueSubstitutions: []
 constants:       []
 machineFunctionInfo: {}
 body:             |
-  ; CHECK-LABEL: name: store_after_add
+  ; CHECK-LABEL: name: do_sink_load_add
   ; CHECK: bb.0.entry:
-  ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
-  ; CHECK:   liveins: $x0, $x1, $x2, $w3
+  ; CHECK:   successors: %bb.1(0x50000000), %bb.4(0x30000000)
+  ; CHECK:   liveins: $x0, $x1, $w3
   ; CHECK:   [[COPY:%[0-9]+]]:gpr32common = COPY $w3
-  ; CHECK:   [[COPY1:%[0-9]+]]:gpr64common = COPY $x2
-  ; CHECK:   [[COPY2:%[0-9]+]]:gpr64common = COPY $x1
-  ; CHECK:   [[COPY3:%[0-9]+]]:gpr64common = COPY $x0
+  ; CHECK:   [[COPY1:%[0-9]+]]:gpr64common = COPY $x1
+  ; CHECK:   [[COPY2:%[0-9]+]]:gpr64common = COPY $x0
   ; CHECK:   [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
-  ; CHECK:   Bcc 11, %bb.2, implicit $nzcv
-  ; CHECK:   B %bb.1
+  ; CHECK:   Bcc 10, %bb.1, implicit $nzcv
+  ; CHECK: bb.4:
+  ; CHECK:   successors: %bb.2(0x80000000)
+  ; CHECK:   [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
+  ; CHECK:   B %bb.2
   ; CHECK: bb.1.for.body.preheader:
   ; CHECK:   successors: %bb.3(0x80000000)
-  ; CHECK:   [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY3]], 0 :: (load 4 from %ir.read, !tbaa !0)
-  ; CHECK:   [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[LDRWui]], 42, 0
-  ; CHECK:   [[COPY4:%[0-9]+]]:gpr32all = COPY [[ADDWri]]
-  ; CHECK:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 43
-  ; CHECK:   STRWui killed [[MOVi32imm]], [[COPY1]], 0 :: (store 4 into %ir.store, !tbaa !0)
+  ; CHECK:   [[FMOVS0_1:%[0-9]+]]:fpr32 = FMOVS0
   ; CHECK:   B %bb.3
   ; CHECK: bb.2.for.cond.cleanup:
-  ; CHECK:   [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.0, %6, %bb.3
-  ; CHECK:   STRWui [[PHI]], [[COPY2]], 0 :: (store 4 into %ir.write, !tbaa !0)
+  ; CHECK:   [[PHI:%[0-9]+]]:fpr32 = PHI [[FMOVS0_]], %bb.4, %4, %bb.3
+  ; CHECK:   STRSui [[PHI]], [[COPY1]], 0 :: (store 4 into %ir.write, !tbaa !0)
   ; CHECK:   RET_ReallyLR
   ; CHECK: bb.3.for.body:
   ; CHECK:   successors: %bb.2(0x04000000), %bb.3(0x7c000000)
-  ; CHECK:   [[PHI1:%[0-9]+]]:gpr32common = PHI [[COPY4]], %bb.1, %8, %bb.3
-  ; CHECK:   [[PHI2:%[0-9]+]]:gpr32sp = PHI [[COPY]], %bb.1, %7, %bb.3
-  ; CHECK:   [[PHI3:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.1, %6, %bb.3
-  ; CHECK:   [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[PHI3]], [[PHI1]]
-  ; CHECK:   [[COPY5:%[0-9]+]]:gpr32all = COPY [[SDIVWr]]
-  ; CHECK:   [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI2]], 1, 0, implicit-def $nzcv
-  ; CHECK:   [[COPY6:%[0-9]+]]:gpr32all = COPY [[SUBSWri1]]
-  ; CHECK:   [[ADDWri1:%[0-9]+]]:gpr32sp = ADDWri [[PHI1]], 1, 0
-  ; CHECK:   [[COPY7:%[0-9]+]]:gpr32all = COPY [[ADDWri1]]
+  ; CHECK:   [[PHI1:%[0-9]+]]:gpr32sp = PHI [[COPY]], %bb.1, %5, %bb.3
+  ; CHECK:   [[PHI2:%[0-9]+]]:fpr32 = PHI [[FMOVS0_1]], %bb.1, %4, %bb.3
+  ; CHECK:   [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[COPY2]], 0 :: (load 4 from %ir.read, !tbaa !0)
+  ; CHECK:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 1109917696
+  ; CHECK:   [[COPY3:%[0-9]+]]:fpr32 = COPY [[MOVi32imm]]
+  ; CHECK:   [[FADDSrr:%[0-9]+]]:fpr32 = nnan ninf nsz arcp contract afn reassoc FADDSrr [[LDRSui]], [[COPY3]]
+  ; CHECK:   [[FADDSrr1:%[0-9]+]]:fpr32 = nnan ninf nsz arcp contract afn reassoc FADDSrr [[FADDSrr]], [[PHI2]]
+  ; CHECK:   [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI1]], 1, 0, implicit-def $nzcv
+  ; CHECK:   [[COPY4:%[0-9]+]]:gpr32all = COPY [[SUBSWri1]]
   ; CHECK:   Bcc 0, %bb.2, implicit $nzcv
   ; CHECK:   B %bb.3
   bb.0.entry:
     successors: %bb.1(0x50000000), %bb.2(0x30000000)
-    liveins: $x0, $x1, $x2, $w3
+    liveins: $x0, $x1, $w3
 
-    %12:gpr32common = COPY $w3
-    %11:gpr64common = COPY $x2
-    %10:gpr64common = COPY $x1
-    %9:gpr64common = COPY $x0
-    %13:gpr32common = LDRWui %9, 0 :: (load 4 from %ir.read, !tbaa !6)
-    %15:gpr32 = SUBSWri %12, 1, 0, implicit-def $nzcv
+    %9:gpr32common = COPY $w3
+    %7:gpr64common = COPY $x1
+    %6:gpr64common = COPY $x0
+    %11:fpr32 = LDRSui %6, 0 :: (load 4 from %ir.read, !tbaa !6)
+    %12:gpr32 = MOVi32imm 1109917696
+    %13:fpr32 = COPY %12
+    %0:fpr32 = nnan ninf nsz arcp contract afn reassoc FADDSrr killed %11, killed %13
+    %10:fpr32 = FMOVS0
+    %14:gpr32 = SUBSWri %9, 1, 0, implicit-def $nzcv
     Bcc 11, %bb.2, implicit $nzcv
     B %bb.1
 
   bb.1.for.body.preheader:
     successors: %bb.3(0x80000000)
 
-    %16:gpr32sp = ADDWri %13, 42, 0
-    %1:gpr32all = COPY %16
-    %14:gpr32 = MOVi32imm 43
-    STRWui killed %14, %11, 0 :: (store 4 into %ir.store, !tbaa !6)
+    %15:fpr32 = FMOVS0
     B %bb.3
 
   bb.2.for.cond.cleanup:
-    %2:gpr32 = PHI %12, %bb.0, %6, %bb.3
-    STRWui %2, %10, 0 :: (store 4 into %ir.write, !tbaa !6)
+    %1:fpr32 = PHI %10, %bb.0, %4, %bb.3
+    STRSui %1, %7, 0 :: (store 4 into %ir.write, !tbaa !6)
     RET_ReallyLR
 
   bb.3.for.body:
     successors: %bb.2(0x04000000), %bb.3(0x7c000000)
 
-    %3:gpr32common = PHI %1, %bb.1, %8, %bb.3
-    %4:gpr32sp = PHI %12, %bb.1, %7, %bb.3
-    %5:gpr32 = PHI %12, %bb.1, %6, %bb.3
-    %17:gpr32 = SDIVWr %5, %3
-    %6:gpr32all = COPY %17
-    %18:gpr32 = SUBSWri %4, 1, 0, implicit-def $nzcv
-    %7:gpr32all = COPY %18
-    %19:gpr32sp = ADDWri %3, 1, 0
-    %8:gpr32all = COPY %19
+    %2:gpr32sp = PHI %9, %bb.1, %5, %bb.3
+    %3:fpr32 = PHI %15, %bb.1, %4, %bb.3
+    %4:fpr32 = nnan ninf nsz arcp contract afn reassoc FADDSrr %0, %3
+    %16:gpr32 = SUBSWri %2, 1, 0, implicit-def $nzcv
+    %5:gpr32all = COPY %16
     Bcc 0, %bb.2, implicit $nzcv
     B %bb.3
 
 ...
 ---
-name:            aliased_store_after_add
+name:            do_sink_no_aliased_store
 alignment:       16
 exposesReturnsTwice: false
 legalized:       false
 regBankSelected: false
 selected:        false
 failedISel:      false
 tracksRegLiveness: true
 hasWinCFI:       false
 registers:
-  - { id: 0, class: gpr32sp, preferred-register: '' }
-  - { id: 1, class: gpr32all, preferred-register: '' }
-  - { id: 2, class: gpr32, preferred-register: '' }
-  - { id: 3, class: gpr32common, preferred-register: '' }
-  - { id: 4, class: gpr32sp, preferred-register: '' }
-  - { id: 5, class: gpr32, preferred-register: '' }
-  - { id: 6, class: gpr32all, preferred-register: '' }
-  - { id: 7, class: gpr32all, preferred-register: '' }
-  - { id: 8, class: gpr32all, preferred-register: '' }
-  - { id: 9, class: gpr64common, preferred-register: '' }
-  - { id: 10, class: gpr64common, preferred-register: '' }
-  - { id: 11, class: gpr64common, preferred-register: '' }
-  - { id: 12, class: gpr32common, preferred-register: '' }
-  - { id: 13, class: gpr32common, preferred-register: '' }
+  - { id: 0, class: fpr32, preferred-register: '' }
+  - { id: 1, class: fpr32, preferred-register: '' }
+  - { id: 2, class: gpr32sp, preferred-register: '' }
+  - { id: 3, class: fpr32, preferred-register: '' }
+  - { id: 4, class: fpr32, preferred-register: '' }
+  - { id: 5, class: gpr32all, preferred-register: '' }
+  - { id: 6, class: gpr64common, preferred-register: '' }
+  - { id: 7, class: gpr64common, preferred-register: '' }
+  - { id: 8, class: gpr64common, preferred-register: '' }
+  - { id: 9, class: gpr32common, preferred-register: '' }
+  - { id: 10, class: fpr32, preferred-register: '' }
+  - { id: 11, class: fpr32, preferred-register: '' }
+  - { id: 12, class: gpr32, preferred-register: '' }
+  - { id: 13, class: fpr32, preferred-register: '' }
   - { id: 14, class: gpr32, preferred-register: '' }
-  - { id: 15, class: gpr32, preferred-register: '' }
-  - { id: 16, class: gpr32sp, preferred-register: '' }
-  - { id: 17, class: gpr32, preferred-register: '' }
-  - { id: 18, class: gpr32, preferred-register: '' }
-  - { id: 19, class: gpr32sp, preferred-register: '' }
 liveins:
-  - { reg: '$x0', virtual-reg: '%9' }
-  - { reg: '$x1', virtual-reg: '%10' }
-  - { reg: '$x2', virtual-reg: '%11' }
-  - { reg: '$w3', virtual-reg: '%12' }
+  - { reg: '$x0', virtual-reg: '%6' }
+  - { reg: '$x1', virtual-reg: '%7' }
+  - { reg: '$x2', virtual-reg: '%8' }
+  - { reg: '$w3', virtual-reg: '%9' }
+  - { reg: '$s0', virtual-reg: '%10' }
 frameInfo:
   isFrameAddressTaken: false
   isReturnAddressTaken: false
   hasStackMap:     false
   hasPatchPoint:   false
   stackSize:       0
   offsetAdjustment: 0
   maxAlignment:    1
frameInfo:
   restorePoint:    ''
 fixedStack:      []
 stack:           []
 callSites:       []
 debugValueSubstitutions: []
 constants:       []
 machineFunctionInfo: {}
 body:             |
-  ; CHECK-LABEL: name: aliased_store_after_add
+  ; CHECK-LABEL: name: do_sink_no_aliased_store
   ; CHECK: bb.0.entry:
-  ; CHECK:   successors: %bb.1(0x50000000), %bb.2(0x30000000)
-  ; CHECK:   liveins: $x0, $x1, $x2, $w3
-  ; CHECK:   [[COPY:%[0-9]+]]:gpr32common = COPY $w3
-  ; CHECK:   [[COPY1:%[0-9]+]]:gpr64common = COPY $x2
-  ; CHECK:   [[COPY2:%[0-9]+]]:gpr64common = COPY $x1
-  ; CHECK:   [[COPY3:%[0-9]+]]:gpr64common = COPY $x0
-  ; CHECK:   [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY]], 1, 0, implicit-def $nzcv
-  ; CHECK:   Bcc 11, %bb.2, implicit $nzcv
-  ; CHECK:   B %bb.1
+  ; CHECK:   successors: %bb.1(0x50000000), %bb.4(0x30000000)
+  ; CHECK:   liveins: $x0, $x1, $x2, $w3, $s0
+  ; CHECK:   [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+  ; CHECK:   [[COPY1:%[0-9]+]]:gpr32common = COPY $w3
+  ; CHECK:   [[COPY2:%[0-9]+]]:gpr64common = COPY $x2
+  ; CHECK:   [[COPY3:%[0-9]+]]:gpr64common = COPY $x1
+  ; CHECK:   [[COPY4:%[0-9]+]]:gpr64common = COPY $x0
+  ; CHECK:   [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY1]], 1, 0, implicit-def $nzcv
+  ; CHECK:   Bcc 10, %bb.1, implicit $nzcv
+  ; CHECK: bb.4:
+  ; CHECK:   successors: %bb.2(0x80000000)
+  ; CHECK:   [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
+  ; CHECK:   B %bb.2
   ; CHECK: bb.1.for.body.preheader:
   ; CHECK:   successors: %bb.3(0x80000000)
-  ; CHECK:   [[LDRWui:%[0-9]+]]:gpr32common = LDRWui [[COPY3]], 0 :: (load 4 from %ir.read, !tbaa !0)
-  ; CHECK:   [[ADDWri:%[0-9]+]]:gpr32sp = ADDWri [[LDRWui]], 42, 0
-  ; CHECK:   [[COPY4:%[0-9]+]]:gpr32all = COPY [[ADDWri]]
-  ; CHECK:   [[MOVi32imm:%[0-9]+]]:gpr32 = MOVi32imm 43
-  ; CHECK:   STRWui killed [[MOVi32imm]], [[COPY3]], 0 :: (store 4 into %ir.read, !tbaa !0)
+  ; CHECK:   [[FMOVS0_1:%[0-9]+]]:fpr32 = FMOVS0
+  ; CHECK:   STRSui [[COPY]], [[COPY2]], 0 :: (store 4 into %ir.store, !tbaa !0)
   ; CHECK:   B %bb.3
   ; CHECK: bb.2.for.cond.cleanup:
-  ; CHECK:   [[PHI:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.0, %6, %bb.3
-  ; CHECK:   STRWui [[PHI]], [[COPY2]], 0 :: (store 4 into %ir.write, !tbaa !0)
+  ; CHECK:   [[PHI:%[0-9]+]]:fpr32 = PHI [[FMOVS0_]], %bb.4, %4, %bb.3
+  ; CHECK:   STRSui [[PHI]], [[COPY3]], 0 :: (store 4 into %ir.write, !tbaa !0)
   ; CHECK:   RET_ReallyLR
   ; CHECK: bb.3.for.body:
   ; CHECK:   successors: %bb.2(0x04000000), %bb.3(0x7c000000)
-  ; CHECK:   [[PHI1:%[0-9]+]]:gpr32common = PHI [[COPY4]], %bb.1, %8, %bb.3
-  ; CHECK:   [[PHI2:%[0-9]+]]:gpr32sp = PHI [[COPY]], %bb.1, %7, %bb.3
-  ; CHECK:   [[PHI3:%[0-9]+]]:gpr32 = PHI [[COPY]], %bb.1, %6, %bb.3
-  ; CHECK:   [[SDIVWr:%[0-9]+]]:gpr32 = SDIVWr [[PHI3]], [[PHI1]]
-  ; CHECK:   [[COPY5:%[0-9]+]]:gpr32all = COPY [[SDIVWr]]
-  ; CHECK:   [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI2]], 1, 0, implicit-def $nzcv
-  ; CHECK:   [[COPY6:%[0-9]+]]:gpr32all = COPY [[SUBSWri1]]
-  ; CHECK:   [[ADDWri1:%[0-9]+]]:gpr32sp = ADDWri [[PHI1]], 1, 0
-  ; CHECK:   [[COPY7:%[0-9]+]]:gpr32all = COPY [[ADDWri1]]
+  ; CHECK:   [[PHI1:%[0-9]+]]:gpr32sp = PHI [[COPY1]], %bb.1, %5, %bb.3
+  ; CHECK:   [[PHI2:%[0-9]+]]:fpr32 = PHI [[FMOVS0_1]], %bb.1, %4, %bb.3
+  ; CHECK:   [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[COPY4]], 0 :: (load 4 from %ir.read, !tbaa !0)
+  ; CHECK:   [[FADDSrr:%[0-9]+]]:fpr32 = nnan ninf nsz arcp contract afn reassoc FADDSrr [[PHI2]], [[LDRSui]]
+  ; CHECK:   [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI1]], 1, 0, implicit-def $nzcv
+  ; CHECK:   [[COPY5:%[0-9]+]]:gpr32all = COPY [[SUBSWri1]]
   ; CHECK:   Bcc 0, %bb.2, implicit $nzcv
   ; CHECK:   B %bb.3
   bb.0.entry:
     successors: %bb.1(0x50000000), %bb.2(0x30000000)
-    liveins: $x0, $x1, $x2, $w3
+    liveins: $x0, $x1, $x2, $w3, $s0
 
-    %12:gpr32common = COPY $w3
-    %11:gpr64common = COPY $x2
-    %10:gpr64common = COPY $x1
-    %9:gpr64common = COPY $x0
-    %13:gpr32common = LDRWui %9, 0 :: (load 4 from %ir.read, !tbaa !6)
-    %15:gpr32 = SUBSWri %12, 1, 0, implicit-def $nzcv
+    %10:fpr32 = COPY $s0
+    %9:gpr32common = COPY $w3
+    %8:gpr64common = COPY $x2
+    %7:gpr64common = COPY $x1
+    %6:gpr64common = COPY $x0
+    %11:fpr32 = FMOVS0
+    %12:gpr32 = SUBSWri %9, 1, 0, implicit-def $nzcv
     Bcc 11, %bb.2, implicit $nzcv
     B %bb.1
 
   bb.1.for.body.preheader:
     successors: %bb.3(0x80000000)
 
-    %16:gpr32sp = ADDWri %13, 42, 0
-    %1:gpr32all = COPY %16
-    %14:gpr32 = MOVi32imm 43
-    STRWui killed %14, %9, 0 :: (store 4 into %ir.read, !tbaa !6)
+    %13:fpr32 = FMOVS0
+    %0:fpr32 = LDRSui %6, 0 :: (load 4 from %ir.read, !tbaa !6)
+    STRSui %10, %8, 0 :: (store 4 into %ir.store, !tbaa !6)
     B %bb.3
 
   bb.2.for.cond.cleanup:
-    %2:gpr32 = PHI %12, %bb.0, %6, %bb.3
-    STRWui %2, %10, 0 :: (store 4 into %ir.write, !tbaa !6)
+    %1:fpr32 = PHI %11, %bb.0, %4, %bb.3
+    STRSui %1, %7, 0 :: (store 4 into %ir.write, !tbaa !6)
     RET_ReallyLR
 
   bb.3.for.body:
     successors: %bb.2(0x04000000), %bb.3(0x7c000000)
 
-    %3:gpr32common = PHI %1, %bb.1, %8, %bb.3
-    %4:gpr32sp = PHI %12, %bb.1, %7, %bb.3
-    %5:gpr32 = PHI %12, %bb.1, %6, %bb.3
-    %17:gpr32 = SDIVWr %5, %3
-    %6:gpr32all = COPY %17
-    %18:gpr32 = SUBSWri %4, 1, 0, implicit-def $nzcv
-    %7:gpr32all = COPY %18
-    %19:gpr32sp = ADDWri %3, 1, 0
-    %8:gpr32all = COPY %19
+    %2:gpr32sp = PHI %9, %bb.1, %5, %bb.3
+    %3:fpr32 = PHI %13, %bb.1, %4, %bb.3
+    %4:fpr32 = nnan ninf nsz arcp contract afn reassoc FADDSrr %3, %0
+    %14:gpr32 = SUBSWri %2, 1, 0, implicit-def $nzcv
+    %5:gpr32all = COPY %14
+    Bcc 0, %bb.2, implicit $nzcv
+    B %bb.3
+
+...
+---
+name:           cant_sink_load_aliased_store
+alignment:       16
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+registers:
+  - { id: 0, class: fpr32, preferred-register: '' }
+  - { id: 1, class: fpr32, preferred-register: '' }
+  - { id: 2, class: gpr32sp, preferred-register: '' }
+  - { id: 3, class: fpr32, preferred-register: '' }
+  - { id: 4, class: fpr32, preferred-register: '' }
+  - { id: 5, class: gpr32all, preferred-register: '' }
+  - { id: 6, class: gpr64common, preferred-register: '' }
+  - { id: 7, class: gpr64common, preferred-register: '' }
+  - { id: 8, class: gpr64common, preferred-register: '' }
+  - { id: 9, class: gpr32common, preferred-register: '' }
+  - { id: 10, class: fpr32, preferred-register: '' }
+  - { id: 11, class: fpr32, preferred-register: '' }
+  - { id: 12, class: gpr32, preferred-register: '' }
+  - { id: 13, class: fpr32, preferred-register: '' }
+  - { id: 14, class: gpr32, preferred-register: '' }
+liveins:
+  - { reg: '$x0', virtual-reg: '%6' }
+  - { reg: '$x1', virtual-reg: '%7' }
+  - { reg: '$x2', virtual-reg: '%8' }
+  - { reg: '$w3', virtual-reg: '%9' }
+  - { reg: '$s0', virtual-reg: '%10' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    1
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  maxCallFrameSize: 0
+  cvBytesOfCalleeSavedRegisters: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  localFrameSize:  0
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      []
+stack:           []
+callSites:       []
+debugValueSubstitutions: []
+constants:       []
+machineFunctionInfo: {}
+body:             |
+  ; CHECK-LABEL: name: cant_sink_load_aliased_store
+  ; CHECK: bb.0.entry:
+  ; CHECK:   successors: %bb.1(0x50000000), %bb.4(0x30000000)
+  ; CHECK:   liveins: $x0, $x1, $x2, $w3, $s0
+  ; CHECK:   [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+  ; CHECK:   [[COPY1:%[0-9]+]]:gpr32common = COPY $w3
+  ; CHECK:   [[COPY2:%[0-9]+]]:gpr64common = COPY $x2
+  ; CHECK:   [[COPY3:%[0-9]+]]:gpr64common = COPY $x1
+  ; CHECK:   [[COPY4:%[0-9]+]]:gpr64common = COPY $x0
+  ; CHECK:   [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY1]], 1, 0, implicit-def $nzcv
+  ; CHECK:   Bcc 10, %bb.1, implicit $nzcv
+  ; CHECK: bb.4:
+  ; CHECK:   successors: %bb.2(0x80000000)
+  ; CHECK:   [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
+  ; CHECK:   B %bb.2
+  ; CHECK: bb.1.for.body.preheader:
+  ; CHECK:   successors: %bb.3(0x80000000)
+  ; CHECK:   [[FMOVS0_1:%[0-9]+]]:fpr32 = FMOVS0
+  ; CHECK:   [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[COPY4]], 0 :: (load 4 from %ir.read, !tbaa !0)
+  ; CHECK:   STRSui [[COPY]], [[COPY2]], 0 :: (store 4 into %ir.store, !tbaa !0)
+  ; CHECK:   B %bb.3
+  ; CHECK: bb.2.for.cond.cleanup:
+  ; CHECK:   [[PHI:%[0-9]+]]:fpr32 = PHI [[FMOVS0_]], %bb.4, %4, %bb.3
+  ; CHECK:   STRSui [[PHI]], [[COPY3]], 0 :: (store 4 into %ir.write, !tbaa !0)
+  ; CHECK:   RET_ReallyLR
+  ; CHECK: bb.3.for.body:
+  ; CHECK:   successors: %bb.2(0x04000000), %bb.3(0x7c000000)
+  ; CHECK:   [[PHI1:%[0-9]+]]:gpr32sp = PHI [[COPY1]], %bb.1, %5, %bb.3
+  ; CHECK:   [[PHI2:%[0-9]+]]:fpr32 = PHI [[FMOVS0_1]], %bb.1, %4, %bb.3
+  ; CHECK:   [[FADDSrr:%[0-9]+]]:fpr32 = nnan ninf nsz arcp contract afn reassoc FADDSrr [[PHI2]], [[LDRSui]]
+  ; CHECK:   [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI1]], 1, 0, implicit-def $nzcv
+  ; CHECK:   [[COPY5:%[0-9]+]]:gpr32all = COPY [[SUBSWri1]]
+  ; CHECK:   Bcc 0, %bb.2, implicit $nzcv
+  ; CHECK:   B %bb.3
+  bb.0.entry:
+    successors: %bb.1(0x50000000), %bb.2(0x30000000)
+    liveins: $x0, $x1, $x2, $w3, $s0
+
+    %10:fpr32 = COPY $s0
+    %9:gpr32common = COPY $w3
+    %8:gpr64common = COPY $x2
+    %7:gpr64common = COPY $x1
+    %6:gpr64common = COPY $x0
+    %11:fpr32 = FMOVS0
+    %12:gpr32 = SUBSWri %9, 1, 0, implicit-def $nzcv
+    Bcc 11, %bb.2, implicit $nzcv
+    B %bb.1
+
+  bb.1.for.body.preheader:
+    successors: %bb.3(0x80000000)
+
+    %13:fpr32 = FMOVS0
+    %0:fpr32 = LDRSui %6, 0 :: (load 4 from %ir.read, !tbaa !6)
+    STRSui %10, %8, 0 :: (store 4 into %ir.store, !tbaa !6)
+    B %bb.3
+
+  bb.2.for.cond.cleanup:
+    %1:fpr32 = PHI %11, %bb.0, %4, %bb.3
+    STRSui %1, %7, 0 :: (store 4 into %ir.write, !tbaa !6)
+    RET_ReallyLR
+
+  bb.3.for.body:
+    successors: %bb.2(0x04000000), %bb.3(0x7c000000)
+
+    %2:gpr32sp = PHI %9, %bb.1, %5, %bb.3
+    %3:fpr32 = PHI %13, %bb.1, %4, %bb.3
+    %4:fpr32 = nnan ninf nsz arcp contract afn reassoc FADDSrr %3, %0
+    %14:gpr32 = SUBSWri %2, 1, 0, implicit-def $nzcv
+    %5:gpr32all = COPY %14
+    Bcc 0, %bb.2, implicit $nzcv
+    B %bb.3
+
+...
+---
+name:            cant_sink_aliased_store_in_loop
+alignment:       16
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+registers:
+  - { id: 0, class: fpr32, preferred-register: '' }
+  - { id: 1, class: fpr32, preferred-register: '' }
+  - { id: 2, class: gpr32sp, preferred-register: '' }
+  - { id: 3, class: fpr32, preferred-register: '' }
+  - { id: 4, class: fpr32, preferred-register: '' }
+  - { id: 5, class: gpr32all, preferred-register: '' }
+  - { id: 6, class: gpr64common, preferred-register: '' }
+  - { id: 7, class: gpr64common, preferred-register: '' }
+  - { id: 8, class: gpr64common, preferred-register: '' }
+  - { id: 9, class: gpr32common, preferred-register: '' }
+  - { id: 10, class: fpr32, preferred-register: '' }
+  - { id: 11, class: fpr32, preferred-register: '' }
+  - { id: 12, class: gpr32, preferred-register: '' }
+  - { id: 13, class: fpr32, preferred-register: '' }
+  - { id: 14, class: gpr32, preferred-register: '' }
+liveins:
+  - { reg: '$x0', virtual-reg: '%6' }
+  - { reg: '$x1', virtual-reg: '%7' }
+  - { reg: '$x2', virtual-reg: '%8' }
+  - { reg: '$w3', virtual-reg: '%9' }
+  - { reg: '$s0', virtual-reg: '%10' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    1
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  maxCallFrameSize: 0
+  cvBytesOfCalleeSavedRegisters: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  localFrameSize:  0
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      []
+stack:           []
+callSites:       []
+debugValueSubstitutions: []
+constants:       []
+machineFunctionInfo: {}
+body:             |
+  ; CHECK-LABEL: name: cant_sink_aliased_store_in_loop
+  ; CHECK: bb.0.entry:
+  ; CHECK:   successors: %bb.1(0x50000000), %bb.4(0x30000000)
+  ; CHECK:   liveins: $x0, $x1, $x2, $w3, $s0
+  ; CHECK:   [[COPY:%[0-9]+]]:fpr32 = COPY $s0
+  ; CHECK:   [[COPY1:%[0-9]+]]:gpr32common = COPY $w3
+  ; CHECK:   [[COPY2:%[0-9]+]]:gpr64common = COPY $x2
+  ; CHECK:   [[COPY3:%[0-9]+]]:gpr64common = COPY $x1
+  ; CHECK:   [[COPY4:%[0-9]+]]:gpr64common = COPY $x0
+  ; CHECK:   [[SUBSWri:%[0-9]+]]:gpr32 = SUBSWri [[COPY1]], 1, 0, implicit-def $nzcv
+  ; CHECK:   Bcc 10, %bb.1, implicit $nzcv
+  ; CHECK: bb.4:
+  ; CHECK:   successors: %bb.2(0x80000000)
+  ; CHECK:   [[FMOVS0_:%[0-9]+]]:fpr32 = FMOVS0
+  ; CHECK:   B %bb.2
+  ; CHECK: bb.1.for.body.preheader:
+  ; CHECK:   successors: %bb.3(0x80000000)
+  ; CHECK:   [[LDRSui:%[0-9]+]]:fpr32 = LDRSui [[COPY4]], 0 :: (load 4 from %ir.read, !tbaa !0)
+  ; CHECK:   [[FMOVS0_1:%[0-9]+]]:fpr32 = FMOVS0
+  ; CHECK:   B %bb.3
+  ; CHECK: bb.2.for.cond.cleanup:
+  ; CHECK:   [[PHI:%[0-9]+]]:fpr32 = PHI [[FMOVS0_]], %bb.4, %4, %bb.3
+  ; CHECK:   STRSui [[PHI]], [[COPY3]], 0 :: (store 4 into %ir.write, !tbaa !0)
+  ; CHECK:   RET_ReallyLR
+  ; CHECK: bb.3.for.body:
+  ; CHECK:   successors: %bb.2(0x04000000), %bb.3(0x7c000000)
+  ; CHECK:   [[PHI1:%[0-9]+]]:gpr32sp = PHI [[COPY1]], %bb.1, %5, %bb.3
+  ; CHECK:   [[PHI2:%[0-9]+]]:fpr32 = PHI [[FMOVS0_1]], %bb.1, %4, %bb.3
+  ; CHECK:   [[FADDSrr:%[0-9]+]]:fpr32 = nnan ninf nsz arcp contract afn reassoc FADDSrr [[PHI2]], [[LDRSui]]
+  ; CHECK:   STRSui [[COPY]], [[COPY2]], 0 :: (store 4 into %ir.store, !tbaa !0)
+  ; CHECK:   [[SUBSWri1:%[0-9]+]]:gpr32 = SUBSWri [[PHI1]], 1, 0, implicit-def $nzcv
+  ; CHECK:   [[COPY5:%[0-9]+]]:gpr32all = COPY [[SUBSWri1]]
+  ; CHECK:   Bcc 0, %bb.2, implicit $nzcv
+  ; CHECK:   B %bb.3
+  bb.0.entry:
+    successors: %bb.1(0x50000000), %bb.2(0x30000000)
+    liveins: $x0, $x1, $x2, $w3, $s0
+
+    %10:fpr32 = COPY $s0
+    %9:gpr32common = COPY $w3
+    %8:gpr64common = COPY $x2
+    %7:gpr64common = COPY $x1
+    %6:gpr64common = COPY $x0
+    %0:fpr32 = LDRSui %6, 0 :: (load 4 from %ir.read, !tbaa !6)
+    %11:fpr32 = FMOVS0
+    %12:gpr32 = SUBSWri %9, 1, 0, implicit-def $nzcv
+    Bcc 11, %bb.2, implicit $nzcv
+    B %bb.1
+
+  bb.1.for.body.preheader:
+    successors: %bb.3(0x80000000)
+
+    %13:fpr32 = FMOVS0
+    B %bb.3
+
+  bb.2.for.cond.cleanup:
+    %1:fpr32 = PHI %11, %bb.0, %4, %bb.3
+    STRSui %1, %7, 0 :: (store 4 into %ir.write, !tbaa !6)
+    RET_ReallyLR
+
+  bb.3.for.body:
+    successors: %bb.2(0x04000000), %bb.3(0x7c000000)
+
+    %2:gpr32sp = PHI %9, %bb.1, %5, %bb.3
+    %3:fpr32 = PHI %13, %bb.1, %4, %bb.3
+    %4:fpr32 = nnan ninf nsz arcp contract afn reassoc FADDSrr %3, %0
+    STRSui %10, %8, 0 :: (store 4 into %ir.store, !tbaa !6)
+    %14:gpr32 = SUBSWri %2, 1, 0, implicit-def $nzcv
+    %5:gpr32all = COPY %14
     Bcc 0, %bb.2, implicit $nzcv
     B %bb.3
 
 ...
 

llvm/test/CodeGen/X86/loop-sink.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=x86_64-- -run-pass=machine-sink -sink-insts-to-avoid-spills  %s -o - | FileCheck %s
+--- |
+  target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+  target triple = "x86_64-unknown-linux-gnu"
+
+  @off = dso_local local_unnamed_addr global i32 0, align 4
+  @C4VERT = dso_local local_unnamed_addr global i64 0, align 8
+  @C2VERT = dso_local local_unnamed_addr global i64 0, align 8
+
+  ; Function Attrs: norecurse nounwind readonly uwtable
+  define dso_local i32 @value(i64 %b1, i64 %b2) local_unnamed_addr #0 {
+  entry:
+    %0 = load i32, i32* @off, align 4
+    %conv2 = sitofp i32 %0 to float
+    %div3 = fdiv float %conv2, 1.000000e+01
+    %1 = load i64, i64* @C4VERT, align 8
+    %2 = load i64, i64* @C2VERT, align 8, !tbaa !2
+    %shl.1 = shl i64 %1, 1
+    %shl.2 = shl i64 %1, 2
+    %shl.3 = shl i64 %1, 3
+    %shl.4 = shl i64 %1, 4
+    %shl.5 = shl i64 %1, 5
+    %shl.6 = shl i64 %1, 6
+    %shl.7 = shl i64 %1, 7
+    %shl.8 = shl i64 %1, 8
+    %shl.9 = shl i64 %1, 9
+    %shl.10 = shl i64 %1, 10
+    %shl.11 = shl i64 %1, 11
+    %shl.12 = shl i64 %1, 12
+    %shl.13 = shl i64 %1, 13
+    %shl.14 = shl i64 %1, 14
+    %shl.15 = shl i64 %1, 15
+    %shl.16 = shl i64 %1, 16
+    %shl.17 = shl i64 %1, 17
+    %shl.18 = shl i64 %1, 18
+    %shl.19 = shl i64 %1, 19
+    %shl.20 = shl i64 %1, 20
+    %shl23.1 = shl i64 %2, 1
+    %shl23.2 = shl i64 %2, 2
+    %shl23.3 = shl i64 %2, 3
+    %shl23.4 = shl i64 %2, 4
+    %shl23.5 = shl i64 %2, 5
+    %shl23.6 = shl i64 %2, 6
+    %shl23.7 = shl i64 %2, 7
+    %shl23.8 = shl i64 %2, 8
+    %shl23.9 = shl i64 %2, 9
+    %shl23.10 = shl i64 %2, 10
+    %shl23.11 = shl i64 %2, 11
+    %shl23.12 = shl i64 %2, 12
+    %shl23.13 = shl i64 %2, 13
+    %shl23.14 = shl i64 %2, 14
+    %shl23.15 = shl i64 %2, 15
+    %shl23.16 = shl i64 %2, 16
+    %shl23.17 = shl i64 %2, 17
+    %shl23.18 = shl i64 %2, 18
+    %shl23.19 = shl i64 %2, 19
+    %shl23.20 = shl i64 %2, 20
+    br label %for.body
+
+  for.body:                                         ; preds = %for.body, %entry
+    %value.072 = phi i32 [ 0, %entry ], [ %value.4.20, %for.body ]
+    %cmp1 = phi i1 [ true, %entry ], [ false, %for.body ]
+    %b.0 = select i1 %cmp1, i64 %b1, i64 %b2
+    %mod.0.v = select i1 %cmp1, float -1.000000e+00, float 1.000000e+00
+    %mod.0 = fadd float %div3, %mod.0.v
+    %mul = fmul float %mod.0, 1.000000e+03
+    %and = and i64 %1, %b.0
+    %cmp11 = icmp eq i64 %and, %1
+    %conv14 = sitofp i32 %value.072 to float
+    %add15 = fadd float %mul, %conv14
+    %conv16 = fptosi float %add15 to i32
+    %value.2 = select i1 %cmp11, i32 %conv16, i32 %value.072
+    %and.1 = and i64 %shl.1, %b.0
+    %cmp11.1 = icmp eq i64 %and.1, %shl.1
+    %conv14.1 = sitofp i32 %value.2 to float
+    %add15.1 = fadd float %mul, %conv14.1
+    %conv16.1 = fptosi float %add15.1 to i32
+    %value.2.1 = select i1 %cmp11.1, i32 %conv16.1, i32 %value.2
+    %and.2 = and i64 %shl.2, %b.0
+    %cmp11.2 = icmp eq i64 %and.2, %shl.2
+    %conv14.2 = sitofp i32 %value.2.1 to float
+    %add15.2 = fadd float %mul, %conv14.2
+    %conv16.2 = fptosi float %add15.2 to i32
+    %value.2.2 = select i1 %cmp11.2, i32 %conv16.2, i32 %value.2.1
+    %and.3 = and i64 %shl.3, %b.0
+    %cmp11.3 = icmp eq i64 %and.3, %shl.3
+    %conv14.3 = sitofp i32 %value.2.2 to float
+    %add15.3 = fadd float %mul, %conv14.3
+    %conv16.3 = fptosi float %add15.3 to i32
+    %value.2.3 = select i1 %cmp11.3, i32 %conv16.3, i32 %value.2.2
+    %and.4 = and i64 %shl.4, %b.0
+    %cmp11.4 = icmp eq i64 %and.4, %shl.4
+    %conv14.4 = sitofp i32 %value.2.3 to float
+    %add15.4 = fadd float %mul, %conv14.4
+    %conv16.4 = fptosi float %add15.4 to i32
+    %value.2.4 = select i1 %cmp11.4, i32 %conv16.4, i32 %value.2.3
+    %and.5 = and i64 %shl.5, %b.0
+    %cmp11.5 = icmp eq i64 %and.5, %shl.5
+    %conv14.5 = sitofp i32 %value.2.4 to float
+    %add15.5 = fadd float %mul, %conv14.5
+    %conv16.5 = fptosi float %add15.5 to i32
+    %value.2.5 = select i1 %cmp11.5, i32 %conv16.5, i32 %value.2.4
+    %and.6 = and i64 %shl.6, %b.0
+    %cmp11.6 = icmp eq i64 %and.6, %shl.6
+    %conv14.6 = sitofp i32 %value.2.5 to float
+    %add15.6 = fadd float %mul, %conv14.6
+    %conv16.6 = fptosi float %add15.6 to i32
+    %value.2.6 = select i1 %cmp11.6, i32 %conv16.6, i32 %value.2.5
+    %and.7 = and i64 %shl.7, %b.0
+    %cmp11.7 = icmp eq i64 %and.7, %shl.7
+    %conv14.7 = sitofp i32 %value.2.6 to float
+    %add15.7 = fadd float %mul, %conv14.7
+    %conv16.7 = fptosi float %add15.7 to i32
+    %value.2.7 = select i1 %cmp11.7, i32 %conv16.7, i32 %value.2.6
+    %and.8 = and i64 %shl.8, %b.0
+    %cmp11.8 = icmp eq i64 %and.8, %shl.8
+    %conv14.8 = sitofp i32 %value.2.7 to float
+    %add15.8 = fadd float %mul, %conv14.8
+    %conv16.8 = fptosi float %add15.8 to i32
+    %value.2.8 = select i1 %cmp11.8, i32 %conv16.8, i32 %value.2.7
+    %and.9 = and i64 %shl.9, %b.0
+    %cmp11.9 = icmp eq i64 %and.9, %shl.9
+    %conv14.9 = sitofp i32 %value.2.8 to float
+    %add15.9 = fadd float %mul, %conv14.9
+    %conv16.9 = fptosi float %add15.9 to i32
+    %value.2.9 = select i1 %cmp11.9, i32 %conv16.9, i32 %value.2.8
+    %and.10 = and i64 %shl.10, %b.0
+    %cmp11.10 = icmp eq i64 %and.10, %shl.10
+    %conv14.10 = sitofp i32 %value.2.9 to float
+    %add15.10 = fadd float %mul, %conv14.10
+    %conv16.10 = fptosi float %add15.10 to i32
+    %value.2.10 = select i1 %cmp11.10, i32 %conv16.10, i32 %value.2.9
+    %and.11 = and i64 %shl.11, %b.0
+    %cmp11.11 = icmp eq i64 %and.11, %shl.11
+    %conv14.11 = sitofp i32 %value.2.10 to float
+    %add15.11 = fadd float %mul, %conv14.11
+    %conv16.11 = fptosi float %add15.11 to i32
+    %value.2.11 = select i1 %cmp11.11, i32 %conv16.11, i32 %value.2.10
+    %and.12 = and i64 %shl.12, %b.0
+    %cmp11.12 = icmp eq i64 %and.12, %shl.12
+    %conv14.12 = sitofp i32 %value.2.11 to float
+    %add15.12 = fadd float %mul, %conv14.12
+    %conv16.12 = fptosi float %add15.12 to i32
+    %value.2.12 = select i1 %cmp11.12, i32 %conv16.12, i32 %value.2.11
+    %and.13 = and i64 %shl.13, %b.0
+    %cmp11.13 = icmp eq i64 %and.13, %shl.13
+    %conv14.13 = sitofp i32 %value.2.12 to float
+    %add15.13 = fadd float %mul, %conv14.13
+    %conv16.13 = fptosi float %add15.13 to i32
+    %value.2.13 = select i1 %cmp11.13, i32 %conv16.13, i32 %value.2.12
+    %and.14 = and i64 %shl.14, %b.0
+    %cmp11.14 = icmp eq i64 %and.14, %shl.14
+    %conv14.14 = sitofp i32 %value.2.13 to float
+    %add15.14 = fadd float %mul, %conv14.14
+    %conv16.14 = fptosi float %add15.14 to i32
+    %value.2.14 = select i1 %cmp11.14, i32 %conv16.14, i32 %value.2.13
+    %and.15 = and i64 %shl.15, %b.0
+    %cmp11.15 = icmp eq i64 %and.15, %shl.15
+    %conv14.15 = sitofp i32 %value.2.14 to float
+    %add15.15 = fadd float %mul, %conv14.15
+    %conv16.15 = fptosi float %add15.15 to i32
+    %value.2.15 = select i1 %cmp11.15, i32 %conv16.15, i32 %value.2.14
+    %and.16 = and i64 %shl.16, %b.0
+    %cmp11.16 = icmp eq i64 %and.16, %shl.16
+    %conv14.16 = sitofp i32 %value.2.15 to float
+    %add15.16 = fadd float %mul, %conv14.16
+    %conv16.16 = fptosi float %add15.16 to i32
+    %value.2.16 = select i1 %cmp11.16, i32 %conv16.16, i32 %value.2.15
+    %and.17 = and i64 %shl.17, %b.0
+    %cmp11.17 = icmp eq i64 %and.17, %shl.17
+    %conv14.17 = sitofp i32 %value.2.16 to float
+    %add15.17 = fadd float %mul, %conv14.17
+    %conv16.17 = fptosi float %add15.17 to i32
+    %value.2.17 = select i1 %cmp11.17, i32 %conv16.17, i32 %value.2.16
+    %and.18 = and i64 %shl.18, %b.0
+    %cmp11.18 = icmp eq i64 %and.18, %shl.18
+    %conv14.18 = sitofp i32 %value.2.17 to float
+    %add15.18 = fadd float %mul, %conv14.18
+    %conv16.18 = fptosi float %add15.18 to i32
+    %value.2.18 = select i1 %cmp11.18, i32 %conv16.18, i32 %value.2.17
+    %and.19 = and i64 %shl.19, %b.0
+    %cmp11.19 = icmp eq i64 %and.19, %shl.19
+    %conv14.19 = sitofp i32 %value.2.18 to float
+    %add15.19 = fadd float %mul, %conv14.19
+    %conv16.19 = fptosi float %add15.19 to i32
+    %value.2.19 = select i1 %cmp11.19, i32 %conv16.19, i32 %value.2.18
+    %and.20 = and i64 %shl.20, %b.0
+    %cmp11.20 = icmp eq i64 %and.20, %shl.20
+    %conv14.20 = sitofp i32 %value.2.19 to float
+    %add15.20 = fadd float %mul, %conv14.20
+    %conv16.20 = fptosi float %add15.20 to i32
+    %value.2.20 = select i1 %cmp11.20, i32 %conv16.20, i32 %value.2.19
+    %bo.0 = select i1 %cmp1, i64 %b2, i64 %b1
+    %mul33 = fmul float %mod.0, 5.000000e+00
+    %and24 = and i64 %2, %b.0
+    %cmp27 = icmp eq i64 %and24, %2
+    %and31 = and i64 %1, %bo.0
+    %tobool.not = icmp eq i64 %and31, 0
+    %or.cond = and i1 %cmp27, %tobool.not
+    %conv34 = sitofp i32 %value.2.20 to float
+    %add35 = fadd float %mul33, %conv34
+    %conv36 = fptosi float %add35 to i32
+    %value.4 = select i1 %or.cond, i32 %conv36, i32 %value.2.20
+    %and24.1 = and i64 %shl23.1, %b.0
+    %cmp27.1 = icmp eq i64 %and24.1, %shl23.1
+    %and31.1 = and i64 %shl.1, %bo.0
+    %tobool.not.1 = icmp eq i64 %and31.1, 0
+    %or.cond73 = and i1 %cmp27.1, %tobool.not.1
+    %conv34.1 = sitofp i32 %value.4 to float
+    %add35.1 = fadd float %mul33, %conv34.1
+    %conv36.1 = fptosi float %add35.1 to i32
+    %value.4.1 = select i1 %or.cond73, i32 %conv36.1, i32 %value.4
+    %and24.2 = and i64 %shl23.2, %b.0
+    %cmp27.2 = icmp eq i64 %and24.2, %shl23.2
+    %and31.2 = and i64 %shl.2, %bo.0
+    %tobool.not.2 = icmp eq i64 %and31.2, 0
+    %or.cond74 = and i1 %cmp27.2, %tobool.not.2
+    %conv34.2 = sitofp i32 %value.4.1 to float
+    %add35.2 = fadd float %mul33, %conv34.2
+    %conv36.2 = fptosi float %add35.2 to i32
+    %value.4.2 = select i1 %or.cond74, i32 %conv36.2, i32 %value.4.1
+    %and24.3 = and i64 %shl23.3, %b.0
+    %cmp27.3 = icmp eq i64 %and24.3, %shl23.3
+    %and31.3 = and i64 %shl.3, %bo.0
+    %tobool.not.3 = icmp eq i64 %and31.3, 0
+    %or.cond75 = and i1 %cmp27.3, %tobool.not.3
+    %conv34.3 = sitofp i32 %value.4.2 to float
+    %add35.3 = fadd float %mul33, %conv34.3
+    %conv36.3 = fptosi float %add35.3 to i32
+    %value.4.3 = select i1 %or.cond75, i32 %conv36.3, i32 %value.4.2
+    %and24.4 = and i64 %shl23.4, %b.0
+    %cmp27.4 = icmp eq i64 %and24.4, %shl23.4
+    %and31.4 = and i64 %shl.4, %bo.0
+    %tobool.not.4 = icmp eq i64 %and31.4, 0
+    %or.cond76 = and i1 %cmp27.4, %tobool.not.4
+    %conv34.4 = sitofp i32 %value.4.3 to float
+    %add35.4 = fadd float %mul33, %conv34.4
+    %conv36.4 = fptosi float %add35.4 to i32
+    %value.4.4 = select i1 %or.cond76, i32 %conv36.4, i32 %value.4.3
+    %and24.5 = and i64 %shl23.5, %b.0
+    %cmp27.5 = icmp eq i64 %and24.5, %shl23.5
+    %and31.5 = and i64 %shl.5, %bo.0
+    %tobool.not.5 = icmp eq i64 %and31.5, 0
+    %or.cond77 = and i1 %cmp27.5, %tobool.not.5
+    %conv34.5 = sitofp i32 %value.4.4 to float
+    %add35.5 = fadd float %mul33, %conv34.5
+    %conv36.5 = fptosi float %add35.5 to i32
+    %value.4.5 = select i1 %or.cond77, i32 %conv36.5, i32 %value.4.4
+    %and24.6 = and i64 %shl23.6, %b.0
+    %cmp27.6 = icmp eq i64 %and24.6, %shl23.6
+    %and31.6 = and i64 %shl.6, %bo.0
+    %tobool.not.6 = icmp eq i64 %and31.6, 0
+    %or.cond78 = and i1 %cmp27.6, %tobool.not.6
+    %conv34.6 = sitofp i32 %value.4.5 to float
+    %add35.6 = fadd float %mul33, %conv34.6
+    %conv36.6 = fptosi float %add35.6 to i32
+    %value.4.6 = select i1 %or.cond78, i32 %conv36.6, i32 %value.4.5
+    %and24.7 = and i64 %shl23.7, %b.0
+    %cmp27.7 = icmp eq i64 %and24.7, %shl23.7
+    %and31.7 = and i64 %shl.7, %bo.0
+    %tobool.not.7 = icmp eq i64 %and31.7, 0
+    %or.cond79 = and i1 %cmp27.7, %tobool.not.7
+    %conv34.7 = sitofp i32 %value.4.6 to float
+    %add35.7 = fadd float %mul33, %conv34.7
+    %conv36.7 = fptosi float %add35.7 to i32
+    %value.4.7 = select i1 %or.cond79, i32 %conv36.7, i32 %value.4.6
+    %and24.8 = and i64 %shl23.8, %b.0
+    %cmp27.8 = icmp eq i64 %and24.8, %shl23.8
+    %and31.8 = and i64 %shl.8, %bo.0
+    %tobool.not.8 = icmp eq i64 %and31.8, 0
+    %or.cond80 = and i1 %cmp27.8, %tobool.not.8
+    %conv34.8 = sitofp i32 %value.4.7 to float
+    %add35.8 = fadd float %mul33, %conv34.8
+    %conv36.8 = fptosi float %add35.8 to i32
+    %value.4.8 = select i1 %or.cond80, i32 %conv36.8, i32 %value.4.7
+    %and24.9 = and i64 %shl23.9, %b.0
+    %cmp27.9 = icmp eq i64 %and24.9, %shl23.9
+    %and31.9 = and i64 %shl.9, %bo.0
+    %tobool.not.9 = icmp eq i64 %and31.9, 0
+    %or.cond81 = and i1 %cmp27.9, %tobool.not.9
+    %conv34.9 = sitofp i32 %value.4.8 to float
+    %add35.9 = fadd float %mul33, %conv34.9
+    %conv36.9 = fptosi float %add35.9 to i32
+    %value.4.9 = select i1 %or.cond81, i32 %conv36.9, i32 %value.4.8
+    %and24.10 = and i64 %shl23.10, %b.0
+    %cmp27.10 = icmp eq i64 %and24.10, %shl23.10
+    %and31.10 = and i64 %shl.10, %bo.0
+    %tobool.not.10 = icmp eq i64 %and31.10, 0
+    %or.cond82 = and i1 %cmp27.10, %tobool.not.10
+    %conv34.10 = sitofp i32 %value.4.9 to float
+    %add35.10 = fadd float %mul33, %conv34.10
+    %conv36.10 = fptosi float %add35.10 to i32
+    %value.4.10 = select i1 %or.cond82, i32 %conv36.10, i32 %value.4.9
+    %and24.11 = and i64 %shl23.11, %b.0
+    %cmp27.11 = icmp eq i64 %and24.11, %shl23.11
+    %and31.11 = and i64 %shl.11, %bo.0
+    %tobool.not.11 = icmp eq i64 %and31.11, 0
+    %or.cond83 = and i1 %cmp27.11, %tobool.not.11
+    %conv34.11 = sitofp i32 %value.4.10 to float
+    %add35.11 = fadd float %mul33, %conv34.11
+    %conv36.11 = fptosi float %add35.11 to i32
+    %value.4.11 = select i1 %or.cond83, i32 %conv36.11, i32 %value.4.10
+    %and24.12 = and i64 %shl23.12, %b.0
+    %cmp27.12 = icmp eq i64 %and24.12, %shl23.12
+    %and31.12 = and i64 %shl.12, %bo.0
+    %tobool.not.12 = icmp eq i64 %and31.12, 0
+    %or.cond84 = and i1 %cmp27.12, %tobool.not.12
+    %conv34.12 = sitofp i32 %value.4.11 to float
+    %add35.12 = fadd float %mul33, %conv34.12
+    %conv36.12 = fptosi float %add35.12 to i32
+    %value.4.12 = select i1 %or.cond84, i32 %conv36.12, i32 %value.4.11
+    %and24.13 = and i64 %shl23.13, %b.0
+    %cmp27.13 = icmp eq i64 %and24.13, %shl23.13
+    %and31.13 = and i64 %shl.13, %bo.0
+    %tobool.not.13 = icmp eq i64 %and31.13, 0
+    %or.cond85 = and i1 %cmp27.13, %tobool.not.13
+    %conv34.13 = sitofp i32 %value.4.12 to float
+    %add35.13 = fadd float %mul33, %conv34.13
+    %conv36.13 = fptosi float %add35.13 to i32
+    %value.4.13 = select i1 %or.cond85, i32 %conv36.13, i32 %value.4.12
+    %and24.14 = and i64 %shl23.14, %b.0
+    %cmp27.14 = icmp eq i64 %and24.14, %shl23.14
+    %and31.14 = and i64 %shl.14, %bo.0
+    %tobool.not.14 = icmp eq i64 %and31.14, 0
+    %or.cond86 = and i1 %cmp27.14, %tobool.not.14
+    %conv34.14 = sitofp i32 %value.4.13 to float
+    %add35.14 = fadd float %mul33, %conv34.14
+    %conv36.14 = fptosi float %add35.14 to i32
+    %value.4.14 = select i1 %or.cond86, i32 %conv36.14, i32 %value.4.13
+    %and24.15 = and i64 %shl23.15, %b.0
+    %cmp27.15 = icmp eq i64 %and24.15, %shl23.15
+    %and31.15 = and i64 %shl.15, %bo.0
+    %tobool.not.15 = icmp eq i64 %and31.15, 0
+    %or.cond87 = and i1 %cmp27.15, %tobool.not.15
+    %conv34.15 = sitofp i32 %value.4.14 to float
+    %add35.15 = fadd float %mul33, %conv34.15
+    %conv36.15 = fptosi float %add35.15 to i32
+    %value.4.15 = select i1 %or.cond87, i32 %conv36.15, i32 %value.4.14
+    %and24.16 = and i64 %shl23.16, %b.0
+    %cmp27.16 = icmp eq i64 %and24.16, %shl23.16
+    %and31.16 = and i64 %shl.16, %bo.0
+    %tobool.not.16 = icmp eq i64 %and31.16, 0
+    %or.cond88 = and i1 %cmp27.16, %tobool.not.16
+    %conv34.16 = sitofp i32 %value.4.15 to float
+    %add35.16 = fadd float %mul33, %conv34.16
+    %conv36.16 = fptosi float %add35.16 to i32
+    %value.4.16 = select i1 %or.cond88, i32 %conv36.16, i32 %value.4.15
+    %and24.17 = and i64 %shl23.17, %b.0
+    %cmp27.17 = icmp eq i64 %and24.17, %shl23.17
+    %and31.17 = and i64 %shl.17, %bo.0
+    %tobool.not.17 = icmp eq i64 %and31.17, 0
+    %or.cond89 = and i1 %cmp27.17, %tobool.not.17
+    %conv34.17 = sitofp i32 %value.4.16 to float
+    %add35.17 = fadd float %mul33, %conv34.17
+    %conv36.17 = fptosi float %add35.17 to i32
+    %value.4.17 = select i1 %or.cond89, i32 %conv36.17, i32 %value.4.16
+    %and24.18 = and i64 %shl23.18, %b.0
+    %cmp27.18 = icmp eq i64 %and24.18, %shl23.18
+    %and31.18 = and i64 %shl.18, %bo.0
+    %tobool.not.18 = icmp eq i64 %and31.18, 0
+    %or.cond90 = and i1 %cmp27.18, %tobool.not.18
+    %conv34.18 = sitofp i32 %value.4.17 to float
+    %add35.18 = fadd float %mul33, %conv34.18
+    %conv36.18 = fptosi float %add35.18 to i32
+    %value.4.18 = select i1 %or.cond90, i32 %conv36.18, i32 %value.4.17
+    %and24.19 = and i64 %shl23.19, %b.0
+    %cmp27.19 = icmp eq i64 %and24.19, %shl23.19
+    %and31.19 = and i64 %shl.19, %bo.0
+    %tobool.not.19 = icmp eq i64 %and31.19, 0
+    %or.cond91 = and i1 %cmp27.19, %tobool.not.19
+    %conv34.19 = sitofp i32 %value.4.18 to float
+    %add35.19 = fadd float %mul33, %conv34.19
+    %conv36.19 = fptosi float %add35.19 to i32
+    %value.4.19 = select i1 %or.cond91, i32 %conv36.19, i32 %value.4.18
+    %and24.20 = and i64 %shl23.20, %b.0
+    %cmp27.20 = icmp eq i64 %and24.20, %shl23.20
+    %and31.20 = and i64 %shl.20, %bo.0
+    %tobool.not.20 = icmp eq i64 %and31.20, 0
+    %or.cond92 = and i1 %cmp27.20, %tobool.not.20
+    %conv34.20 = sitofp i32 %value.4.19 to float
+    %add35.20 = fadd float %mul33, %conv34.20
+    %conv36.20 = fptosi float %add35.20 to i32
+    %value.4.20 = select i1 %or.cond92, i32 %conv36.20, i32 %value.4.19
+    br i1 %cmp1, label %for.body, label %for.end43, !llvm.loop !6
+
+  for.end43:                                        ; preds = %for.body
+    ret i32 %value.4.20
+  }
+
+  attributes #0 = { norecurse nounwind readonly uwtable "disable-tail-calls"="false" "frame-pointer"="none" "less-precise-fpmad"="false" "min-legal-vector-width"="0" "no-infs-fp-math"="false" "no-jump-tables"="false" "no-nans-fp-math"="false" "no-signed-zeros-fp-math"="false" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="x86-64" "target-features"="+cx8,+fxsr,+mmx,+sse,+sse2,+x87" "tune-cpu"="generic" "unsafe-fp-math"="false" "use-soft-float"="false" }
+
+  !llvm.module.flags = !{!0}
+  !llvm.ident = !{!1}
+
+  !0 = !{i32 1, !"wchar_size", i32 4}
+  !1 = !{!"clang version 13.0.0 (https://github.com/llvm/llvm-project.git 06829034ca64b8c83a5b20d8abe5ddbfe7af0004)"}
+  !2 = !{!3, !3, i64 0}
+  !3 = !{!"long long", !4, i64 0}
+  !4 = !{!"omnipotent char", !5, i64 0}
+  !5 = !{!"Simple C/C++ TBAA"}
+  !6 = distinct !{!6, !7}
+  !7 = !{!"llvm.loop.mustprogress"}
+
+...
+---
+name:            value
+alignment:       16
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+registers:
+  - { id: 0, class: fr32, preferred-register: '' }
+  - { id: 1, class: gr64, preferred-register: '' }
+  - { id: 2, class: gr64, preferred-register: '' }
+  - { id: 3, class: gr64, preferred-register: '' }
+  - { id: 4, class: gr64, preferred-register: '' }
+  - { id: 5, class: gr64, preferred-register: '' }
+  - { id: 6, class: gr64, preferred-register: '' }
+  - { id: 7, class: gr64, preferred-register: '' }
+  - { id: 8, class: gr64, preferred-register: '' }
+  - { id: 9, class: gr64, preferred-register: '' }
+  - { id: 10, class: gr64, preferred-register: '' }
+  - { id: 11, class: gr64, preferred-register: '' }
+  - { id: 12, class: gr64, preferred-register: '' }
+  - { id: 13, class: gr64, preferred-register: '' }
+  - { id: 14, class: gr64, preferred-register: '' }
+  - { id: 15, class: gr64, preferred-register: '' }
+  - { id: 16, class: gr64, preferred-register: '' }
+  - { id: 17, class: gr64, preferred-register: '' }
+  - { id: 18, class: gr64, preferred-register: '' }
+  - { id: 19, class: gr64, preferred-register: '' }
+  - { id: 20, class: gr64, preferred-register: '' }
+  - { id: 21, class: gr64, preferred-register: '' }
+  - { id: 22, class: gr64, preferred-register: '' }
+  - { id: 23, class: gr64, preferred-register: '' }
+  - { id: 24, class: gr64, preferred-register: '' }
+  - { id: 25, class: gr64, preferred-register: '' }
+  - { id: 26, class: gr64, preferred-register: '' }
+  - { id: 27, class: gr64, preferred-register: '' }
+  - { id: 28, class: gr64, preferred-register: '' }
+  - { id: 29, class: gr64, preferred-register: '' }
+  - { id: 30, class: gr64, preferred-register: '' }
+  - { id: 31, class: gr64, preferred-register: '' }
+  - { id: 32, class: gr64, preferred-register: '' }
+  - { id: 33, class: gr64, preferred-register: '' }
+  - { id: 34, class: gr64, preferred-register: '' }
+  - { id: 35, class: gr64, preferred-register: '' }
+  - { id: 36, class: gr64, preferred-register: '' }
+  - { id: 37, class: gr64, preferred-register: '' }
+  - { id: 38, class: gr64, preferred-register: '' }
+  - { id: 39, class: gr64, preferred-register: '' }
+  - { id: 40, class: gr64, preferred-register: '' }
+  - { id: 41, class: gr64, preferred-register: '' }
+  - { id: 42, class: gr64, preferred-register: '' }
+  - { id: 43, class: gr32, preferred-register: '' }
+  - { id: 44, class: gr8, preferred-register: '' }
+  - { id: 45, class: gr32, preferred-register: '' }
+  - { id: 46, class: gr64, preferred-register: '' }
+  - { id: 47, class: gr64, preferred-register: '' }
+  - { id: 48, class: gr32, preferred-register: '' }
+  - { id: 49, class: gr8, preferred-register: '' }
+  - { id: 50, class: fr32, preferred-register: '' }
+  - { id: 51, class: gr8, preferred-register: '' }
+  - { id: 52, class: gr64, preferred-register: '' }
+  - { id: 53, class: fr32, preferred-register: '' }
+  - { id: 54, class: fr32, preferred-register: '' }
+  - { id: 55, class: fr32, preferred-register: '' }
+  - { id: 56, class: fr32, preferred-register: '' }
+  - { id: 57, class: fr32, preferred-register: '' }
+  - { id: 58, class: gr64, preferred-register: '' }
+  - { id: 59, class: gr64, preferred-register: '' }
+  - { id: 60, class: gr64, preferred-register: '' }
+  - { id: 61, class: fr32, preferred-register: '' }
+  - { id: 62, class: fr32, preferred-register: '' }
+  - { id: 63, class: gr32, preferred-register: '' }
+  - { id: 64, class: gr32, preferred-register: '' }
+  - { id: 65, class: gr64, preferred-register: '' }
+  - { id: 66, class: gr64, preferred-register: '' }
+  - { id: 67, class: fr32, preferred-register: '' }
+  - { id: 68, class: fr32, preferred-register: '' }
+  - { id: 69, class: gr32, preferred-register: '' }
+  - { id: 70, class: gr32, preferred-register: '' }
+  - { id: 71, class: gr64, preferred-register: '' }
+  - { id: 72, class: gr64, preferred-register: '' }
+  - { id: 73, class: fr32, preferred-register: '' }
+  - { id: 74, class: fr32, preferred-register: '' }
+  - { id: 75, class: gr32, preferred-register: '' }
+  - { id: 76, class: gr32, preferred-register: '' }
+  - { id: 77, class: gr64, preferred-register: '' }
+  - { id: 78, class: gr64, preferred-register: '' }
+  - { id: 79, class: fr32, preferred-register: '' }
+  - { id: 80, class: fr32, preferred-register: '' }
+  - { id: 81, class: gr32, preferred-register: '' }
+  - { id: 82, class: gr32, preferred-register: '' }
+  - { id: 83, class: gr64, preferred-register: '' }
+  - { id: 84, class: gr64, preferred-register: '' }
+  - { id: 85, class: fr32, preferred-register: '' }
+  - { id: 86, class: fr32, preferred-register: '' }
+  - { id: 87, class: gr32, preferred-register: '' }
+  - { id: 88, class: gr32, preferred-register: '' }
+  - { id: 89, class: gr64, preferred-register: '' }
+  - { id: 90, class: gr64, preferred-register: '' }
+  - { id: 91, class: fr32, preferred-register: '' }
+  - { id: 92, class: fr32, preferred-register: '' }
+  - { id: 93, class: gr32, preferred-register: '' }
+  - { id: 94, class: gr32, preferred-register: '' }
+  - { id: 95, class: gr64, preferred-register: '' }
+  - { id: 96, class: gr64, preferred-register: '' }
+  - { id: 97, class: fr32, preferred-register: '' }
+  - { id: 98, class: fr32, preferred-register: '' }
+  - { id: 99, class: gr32, preferred-register: '' }
+  - { id: 100, class: gr32, preferred-register: '' }
+  - { id: 101, class: gr64, preferred-register: '' }
+  - { id: 102, class: gr64, preferred-register: '' }
+  - { id: 103, class: fr32, preferred-register: '' }
+  - { id: 104, class: fr32, preferred-register: '' }
+  - { id: 105, class: gr32, preferred-register: '' }
+  - { id: 106, class: gr32, preferred-register: '' }
+  - { id: 107, class: gr64, preferred-register: '' }
+  - { id: 108, class: gr64, preferred-register: '' }
+  - { id: 109, class: fr32, preferred-register: '' }
+  - { id: 110, class: fr32, preferred-register: '' }
+  - { id: 111, class: gr32, preferred-register: '' }
+  - { id: 112, class: gr32, preferred-register: '' }
+  - { id: 113, class: gr64, preferred-register: '' }
+  - { id: 114, class: gr64, preferred-register: '' }
+  - { id: 115, class: fr32, preferred-register: '' }
+  - { id: 116, class: fr32, preferred-register: '' }
+  - { id: 117, class: gr32, preferred-register: '' }
+  - { id: 118, class: gr32, preferred-register: '' }
+  - { id: 119, class: gr64, preferred-register: '' }
+  - { id: 120, class: gr64, preferred-register: '' }
+  - { id: 121, class: fr32, preferred-register: '' }
+  - { id: 122, class: fr32, preferred-register: '' }
+  - { id: 123, class: gr32, preferred-register: '' }
+  - { id: 124, class: gr32, preferred-register: '' }
+  - { id: 125, class: gr64, preferred-register: '' }
+  - { id: 126, class: gr64, preferred-register: '' }
+  - { id: 127, class: fr32, preferred-register: '' }
+  - { id: 128, class: fr32, preferred-register: '' }
+  - { id: 129, class: gr32, preferred-register: '' }
+  - { id: 130, class: gr32, preferred-register: '' }
+  - { id: 131, class: gr64, preferred-register: '' }
+  - { id: 132, class: gr64, preferred-register: '' }
+  - { id: 133, class: fr32, preferred-register: '' }
+  - { id: 134, class: fr32, preferred-register: '' }
+  - { id: 135, class: gr32, preferred-register: '' }
+  - { id: 136, class: gr32, preferred-register: '' }
+  - { id: 137, class: gr64, preferred-register: '' }
+  - { id: 138, class: gr64, preferred-register: '' }
+  - { id: 139, class: fr32, preferred-register: '' }
+  - { id: 140, class: fr32, preferred-register: '' }
+  - { id: 141, class: gr32, preferred-register: '' }
+  - { id: 142, class: gr32, preferred-register: '' }
+  - { id: 143, class: gr64, preferred-register: '' }
+  - { id: 144, class: gr64, preferred-register: '' }
+  - { id: 145, class: fr32, preferred-register: '' }
+  - { id: 146, class: fr32, preferred-register: '' }
+  - { id: 147, class: gr32, preferred-register: '' }
+  - { id: 148, class: gr32, preferred-register: '' }
+  - { id: 149, class: gr64, preferred-register: '' }
+  - { id: 150, class: gr64, preferred-register: '' }
+  - { id: 151, class: fr32, preferred-register: '' }
+  - { id: 152, class: fr32, preferred-register: '' }
+  - { id: 153, class: gr32, preferred-register: '' }
+  - { id: 154, class: gr32, preferred-register: '' }
+  - { id: 155, class: gr64, preferred-register: '' }
+  - { id: 156, class: gr64, preferred-register: '' }
+  - { id: 157, class: fr32, preferred-register: '' }
+  - { id: 158, class: fr32, preferred-register: '' }
+  - { id: 159, class: gr32, preferred-register: '' }
+  - { id: 160, class: gr32, preferred-register: '' }
+  - { id: 161, class: gr64, preferred-register: '' }
+  - { id: 162, class: gr64, preferred-register: '' }
+  - { id: 163, class: fr32, preferred-register: '' }
+  - { id: 164, class: fr32, preferred-register: '' }
+  - { id: 165, class: gr32, preferred-register: '' }
+  - { id: 166, class: gr32, preferred-register: '' }
+  - { id: 167, class: gr64, preferred-register: '' }
+  - { id: 168, class: gr64, preferred-register: '' }
+  - { id: 169, class: fr32, preferred-register: '' }
+  - { id: 170, class: fr32, preferred-register: '' }
+  - { id: 171, class: gr32, preferred-register: '' }
+  - { id: 172, class: gr32, preferred-register: '' }
+  - { id: 173, class: gr64, preferred-register: '' }
+  - { id: 174, class: gr64, preferred-register: '' }
+  - { id: 175, class: fr32, preferred-register: '' }
+  - { id: 176, class: fr32, preferred-register: '' }
+  - { id: 177, class: gr32, preferred-register: '' }
+  - { id: 178, class: gr32, preferred-register: '' }
+  - { id: 179, class: gr64, preferred-register: '' }
+  - { id: 180, class: gr64, preferred-register: '' }
+  - { id: 181, class: fr32, preferred-register: '' }
+  - { id: 182, class: fr32, preferred-register: '' }
+  - { id: 183, class: gr32, preferred-register: '' }
+  - { id: 184, class: gr32, preferred-register: '' }
+  - { id: 185, class: fr32, preferred-register: '' }
+  - { id: 186, class: gr64, preferred-register: '' }
+  - { id: 187, class: gr64, preferred-register: '' }
+  - { id: 188, class: gr64, preferred-register: '' }
+  - { id: 189, class: fr32, preferred-register: '' }
+  - { id: 190, class: fr32, preferred-register: '' }
+  - { id: 191, class: gr32, preferred-register: '' }
+  - { id: 192, class: gr64, preferred-register: '' }
+  - { id: 193, class: gr32, preferred-register: '' }
+  - { id: 194, class: gr64, preferred-register: '' }
+  - { id: 195, class: gr64, preferred-register: '' }
+  - { id: 196, class: gr64, preferred-register: '' }
+  - { id: 197, class: fr32, preferred-register: '' }
+  - { id: 198, class: fr32, preferred-register: '' }
+  - { id: 199, class: gr32, preferred-register: '' }
+  - { id: 200, class: gr64, preferred-register: '' }
+  - { id: 201, class: gr32, preferred-register: '' }
+  - { id: 202, class: gr64, preferred-register: '' }
+  - { id: 203, class: gr64, preferred-register: '' }
+  - { id: 204, class: gr64, preferred-register: '' }
+  - { id: 205, class: fr32, preferred-register: '' }
+  - { id: 206, class: fr32, preferred-register: '' }
+  - { id: 207, class: gr32, preferred-register: '' }
+  - { id: 208, class: gr64, preferred-register: '' }
+  - { id: 209, class: gr32, preferred-register: '' }
+  - { id: 210, class: gr64, preferred-register: '' }
+  - { id: 211, class: gr64, preferred-register: '' }
+  - { id: 212, class: gr64, preferred-register: '' }
+  - { id: 213, class: fr32, preferred-register: '' }
+  - { id: 214, class: fr32, preferred-register: '' }
+  - { id: 215, class: gr32, preferred-register: '' }
+  - { id: 216, class: gr64, preferred-register: '' }
+  - { id: 217, class: gr32, preferred-register: '' }
+  - { id: 218, class: gr64, preferred-register: '' }
+  - { id: 219, class: gr64, preferred-register: '' }
+  - { id: 220, class: gr64, preferred-register: '' }
+  - { id: 221, class: fr32, preferred-register: '' }
+  - { id: 222, class: fr32, preferred-register: '' }
+  - { id: 223, class: gr32, preferred-register: '' }
+  - { id: 224, class: gr64, preferred-register: '' }
+  - { id: 225, class: gr32, preferred-register: '' }
+  - { id: 226, class: gr64, preferred-register: '' }
+  - { id: 227, class: gr64, preferred-register: '' }
+  - { id: 228, class: gr64, preferred-register: '' }
+  - { id: 229, class: fr32, preferred-register: '' }
+  - { id: 230, class: fr32, preferred-register: '' }
+  - { id: 231, class: gr32, preferred-register: '' }
+  - { id: 232, class: gr64, preferred-register: '' }
+  - { id: 233, class: gr32, preferred-register: '' }
+  - { id: 234, class: gr64, preferred-register: '' }
+  - { id: 235, class: gr64, preferred-register: '' }
+  - { id: 236, class: gr64, preferred-register: '' }
+  - { id: 237, class: fr32, preferred-register: '' }
+  - { id: 238, class: fr32, preferred-register: '' }
+  - { id: 239, class: gr32, preferred-register: '' }
+  - { id: 240, class: gr64, preferred-register: '' }
+  - { id: 241, class: gr32, preferred-register: '' }
+  - { id: 242, class: gr64, preferred-register: '' }
+  - { id: 243, class: gr64, preferred-register: '' }
+  - { id: 244, class: gr64, preferred-register: '' }
+  - { id: 245, class: fr32, preferred-register: '' }
+  - { id: 246, class: fr32, preferred-register: '' }
+  - { id: 247, class: gr32, preferred-register: '' }
+  - { id: 248, class: gr64, preferred-register: '' }
+  - { id: 249, class: gr32, preferred-register: '' }
+  - { id: 250, class: gr64, preferred-register: '' }
+  - { id: 251, class: gr64, preferred-register: '' }
+  - { id: 252, class: gr64, preferred-register: '' }
+  - { id: 253, class: fr32, preferred-register: '' }
+  - { id: 254, class: fr32, preferred-register: '' }
+  - { id: 255, class: gr32, preferred-register: '' }
+  - { id: 256, class: gr64, preferred-register: '' }
+  - { id: 257, class: gr32, preferred-register: '' }
+  - { id: 258, class: gr64, preferred-register: '' }
+  - { id: 259, class: gr64, preferred-register: '' }
+  - { id: 260, class: gr64, preferred-register: '' }
+  - { id: 261, class: fr32, preferred-register: '' }
+  - { id: 262, class: fr32, preferred-register: '' }
+  - { id: 263, class: gr32, preferred-register: '' }
+  - { id: 264, class: gr64, preferred-register: '' }
+  - { id: 265, class: gr32, preferred-register: '' }
+  - { id: 266, class: gr64, preferred-register: '' }
+  - { id: 267, class: gr64, preferred-register: '' }
+  - { id: 268, class: gr64, preferred-register: '' }
+  - { id: 269, class: fr32, preferred-register: '' }
+  - { id: 270, class: fr32, preferred-register: '' }
+  - { id: 271, class: gr32, preferred-register: '' }
+  - { id: 272, class: gr64, preferred-register: '' }
+  - { id: 273, class: gr32, preferred-register: '' }
+  - { id: 274, class: gr64, preferred-register: '' }
+  - { id: 275, class: gr64, preferred-register: '' }
+  - { id: 276, class: gr64, preferred-register: '' }
+  - { id: 277, class: fr32, preferred-register: '' }
+  - { id: 278, class: fr32, preferred-register: '' }
+  - { id: 279, class: gr32, preferred-register: '' }
+  - { id: 280, class: gr64, preferred-register: '' }
+  - { id: 281, class: gr32, preferred-register: '' }
+  - { id: 282, class: gr64, preferred-register: '' }
+  - { id: 283, class: gr64, preferred-register: '' }
+  - { id: 284, class: gr64, preferred-register: '' }
+  - { id: 285, class: fr32, preferred-register: '' }
+  - { id: 286, class: fr32, preferred-register: '' }
+  - { id: 287, class: gr32, preferred-register: '' }
+  - { id: 288, class: gr64, preferred-register: '' }
+  - { id: 289, class: gr32, preferred-register: '' }
+  - { id: 290, class: gr64, preferred-register: '' }
+  - { id: 291, class: gr64, preferred-register: '' }
+  - { id: 292, class: gr64, preferred-register: '' }
+  - { id: 293, class: fr32, preferred-register: '' }
+  - { id: 294, class: fr32, preferred-register: '' }
+  - { id: 295, class: gr32, preferred-register: '' }
+  - { id: 296, class: gr64, preferred-register: '' }
+  - { id: 297, class: gr32, preferred-register: '' }
+  - { id: 298, class: gr64, preferred-register: '' }
+  - { id: 299, class: gr64, preferred-register: '' }
+  - { id: 300, class: gr64, preferred-register: '' }
+  - { id: 301, class: fr32, preferred-register: '' }
+  - { id: 302, class: fr32, preferred-register: '' }
+  - { id: 303, class: gr32, preferred-register: '' }
+  - { id: 304, class: gr64, preferred-register: '' }
+  - { id: 305, class: gr32, preferred-register: '' }
+  - { id: 306, class: gr64, preferred-register: '' }
+  - { id: 307, class: gr64, preferred-register: '' }
+  - { id: 308, class: gr64, preferred-register: '' }
+  - { id: 309, class: fr32, preferred-register: '' }
+  - { id: 310, class: fr32, preferred-register: '' }
+  - { id: 311, class: gr32, preferred-register: '' }
+  - { id: 312, class: gr64, preferred-register: '' }
+  - { id: 313, class: gr32, preferred-register: '' }
+  - { id: 314, class: gr64, preferred-register: '' }
+  - { id: 315, class: gr64, preferred-register: '' }
+  - { id: 316, class: gr64, preferred-register: '' }
+  - { id: 317, class: fr32, preferred-register: '' }
+  - { id: 318, class: fr32, preferred-register: '' }
+  - { id: 319, class: gr32, preferred-register: '' }
+  - { id: 320, class: gr64, preferred-register: '' }
+  - { id: 321, class: gr32, preferred-register: '' }
+  - { id: 322, class: gr64, preferred-register: '' }
+  - { id: 323, class: gr64, preferred-register: '' }
+  - { id: 324, class: gr64, preferred-register: '' }
+  - { id: 325, class: fr32, preferred-register: '' }
+  - { id: 326, class: fr32, preferred-register: '' }
+  - { id: 327, class: gr32, preferred-register: '' }
+  - { id: 328, class: gr64, preferred-register: '' }
+  - { id: 329, class: gr32, preferred-register: '' }
+  - { id: 330, class: gr64, preferred-register: '' }
+  - { id: 331, class: gr64, preferred-register: '' }
+  - { id: 332, class: gr64, preferred-register: '' }
+  - { id: 333, class: fr32, preferred-register: '' }
+  - { id: 334, class: fr32, preferred-register: '' }
+  - { id: 335, class: gr32, preferred-register: '' }
+  - { id: 336, class: gr64, preferred-register: '' }
+  - { id: 337, class: gr32, preferred-register: '' }
+  - { id: 338, class: gr64, preferred-register: '' }
+  - { id: 339, class: gr64, preferred-register: '' }
+  - { id: 340, class: gr64, preferred-register: '' }
+  - { id: 341, class: fr32, preferred-register: '' }
+  - { id: 342, class: fr32, preferred-register: '' }
+  - { id: 343, class: gr32, preferred-register: '' }
+  - { id: 344, class: gr64, preferred-register: '' }
+  - { id: 345, class: gr32, preferred-register: '' }
+  - { id: 346, class: gr64, preferred-register: '' }
+  - { id: 347, class: gr64, preferred-register: '' }
+  - { id: 348, class: gr64, preferred-register: '' }
+  - { id: 349, class: fr32, preferred-register: '' }
+  - { id: 350, class: fr32, preferred-register: '' }
+  - { id: 351, class: gr32, preferred-register: '' }
+  - { id: 352, class: gr64, preferred-register: '' }
+  - { id: 353, class: gr32, preferred-register: '' }
+  - { id: 354, class: fr32, preferred-register: '' }
+  - { id: 355, class: fr32, preferred-register: '' }
+liveins:
+  - { reg: '$rdi', virtual-reg: '%46' }
+  - { reg: '$rsi', virtual-reg: '%47' }
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    1
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  maxCallFrameSize: 4294967295
+  cvBytesOfCalleeSavedRegisters: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  localFrameSize:  0
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      []
+stack:           []
+callSites:       []
+debugValueSubstitutions: []
+constants:
+  - id:              0
+    value:           'float 1.000000e+01'
+    alignment:       4
+    isTargetSpecific: false
+  - id:              1
+    value:           'float -1.000000e+00'
+    alignment:       4
+    isTargetSpecific: false
+  - id:              2
+    value:           'float 1.000000e+00'
+    alignment:       4
+    isTargetSpecific: false
+  - id:              3
+    value:           'float 1.000000e+03'
+    alignment:       4
+    isTargetSpecific: false
+  - id:              4
+    value:           'float 5.000000e+00'
+    alignment:       4
+    isTargetSpecific: false
+machineFunctionInfo: {}
+body:             |
+  ; CHECK-LABEL: name: value
+  ; CHECK: bb.0.entry:
+  ; CHECK:   successors: %bb.1(0x80000000)
+  ; CHECK:   liveins: $rdi, $rsi
+  ; CHECK:   [[COPY:%[0-9]+]]:gr64 = COPY $rsi
+  ; CHECK:   [[COPY1:%[0-9]+]]:gr64 = COPY $rdi
+  ; CHECK:   %50:fr32 = nofpexcept CVTSI2SSrm $rip, 1, $noreg, @off, $noreg, implicit $mxcsr :: (dereferenceable load 4 from @off)
+  ; CHECK:   %0:fr32 = nofpexcept DIVSSrm %50, $rip, 1, $noreg, %const.0, $noreg, implicit $mxcsr :: (load 4 from constant-pool)
+  ; CHECK:   [[MOV64rm:%[0-9]+]]:gr64 = MOV64rm $rip, 1, $noreg, @C4VERT, $noreg :: (dereferenceable load 8 from @C4VERT)
+  ; CHECK:   [[MOV64rm1:%[0-9]+]]:gr64 = MOV64rm $rip, 1, $noreg, @C2VERT, $noreg :: (dereferenceable load 8 from @C2VERT, !tbaa !2)
+  ; CHECK:   [[ADD64rr:%[0-9]+]]:gr64 = ADD64rr [[MOV64rm]], [[MOV64rm]], implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm]], 2, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri1:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm]], 3, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri2:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm]], 4, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri3:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm]], 5, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri4:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm]], 6, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri5:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm]], 7, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri6:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm]], 8, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri7:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm]], 9, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri8:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm]], 10, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri9:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm]], 11, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri10:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm]], 12, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri11:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm]], 13, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri12:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm]], 14, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri13:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm]], 15, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri14:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm]], 16, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri15:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm]], 17, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri16:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm]], 18, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri17:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm]], 19, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri18:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm]], 20, implicit-def dead $eflags
+  ; CHECK:   [[ADD64rr1:%[0-9]+]]:gr64 = ADD64rr [[MOV64rm1]], [[MOV64rm1]], implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri19:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm1]], 2, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri20:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm1]], 3, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri21:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm1]], 4, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri22:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm1]], 5, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri23:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm1]], 6, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri24:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm1]], 7, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri25:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm1]], 8, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri26:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm1]], 9, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri27:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm1]], 10, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri28:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm1]], 11, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri29:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm1]], 12, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri30:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm1]], 13, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri31:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm1]], 14, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri32:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm1]], 15, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri33:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm1]], 16, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri34:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm1]], 17, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri35:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm1]], 18, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri36:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm1]], 19, implicit-def dead $eflags
+  ; CHECK:   [[SHL64ri37:%[0-9]+]]:gr64 = SHL64ri [[MOV64rm1]], 20, implicit-def dead $eflags
+  ; CHECK:   [[MOV8ri:%[0-9]+]]:gr8 = MOV8ri 1
+  ; CHECK:   [[MOV32r0_:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
+  ; CHECK:   [[MOVSSrm_alt:%[0-9]+]]:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.1, $noreg :: (load 4 from constant-pool)
+  ; CHECK:   [[MOVSSrm_alt1:%[0-9]+]]:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.2, $noreg :: (load 4 from constant-pool)
+  ; CHECK: bb.1.for.body:
+  ; CHECK:   successors: %bb.2(0x40000000), %bb.3(0x40000000)
+  ; CHECK:   [[PHI:%[0-9]+]]:gr32 = PHI [[MOV32r0_]], %bb.0, %45, %bb.3
+  ; CHECK:   [[PHI1:%[0-9]+]]:gr8 = PHI [[MOV8ri]], %bb.0, %51, %bb.3
+  ; CHECK:   TEST8ri [[PHI1]], 1, implicit-def $eflags
+  ; CHECK:   [[CMOV64rr:%[0-9]+]]:gr64 = CMOV64rr [[COPY]], [[COPY1]], 5, implicit $eflags
+  ; CHECK:   JCC_1 %bb.3, 5, implicit $eflags
+  ; CHECK: bb.2.for.body:
+  ; CHECK:   successors: %bb.3(0x80000000)
+  ; CHECK:   liveins: $eflags
+  ; CHECK: bb.3.for.body:
+  ; CHECK:   successors: %bb.1(0x7c000000), %bb.4(0x04000000)
+  ; CHECK:   liveins: $eflags
+  ; CHECK:   [[PHI2:%[0-9]+]]:fr32 = PHI [[MOVSSrm_alt1]], %bb.2, [[MOVSSrm_alt]], %bb.1
+  ; CHECK:   [[MOVSSrm_alt2:%[0-9]+]]:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.3, $noreg :: (load 4 from constant-pool)
+  ; CHECK:   [[MOVSSrm_alt3:%[0-9]+]]:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.4, $noreg :: (load 4 from constant-pool)
+  ; CHECK:   %56:fr32 = nofpexcept ADDSSrr %0, killed [[PHI2]], implicit $mxcsr
+  ; CHECK:   [[MULSSrr:%[0-9]+]]:fr32 = MULSSrr %56, [[MOVSSrm_alt2]], implicit $mxcsr
+  ; CHECK:   [[CMOV64rr1:%[0-9]+]]:gr64 = CMOV64rr [[COPY1]], [[COPY]], 5, implicit $eflags
+  ; CHECK:   [[AND64rr:%[0-9]+]]:gr64 = AND64rr [[MOV64rm]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[SUB64rr:%[0-9]+]]:gr64 = SUB64rr [[AND64rr]], [[MOV64rm]], implicit-def $eflags
+  ; CHECK:   %61:fr32 = nofpexcept CVTSI2SSrr [[PHI]], implicit $mxcsr
+  ; CHECK:   %62:fr32 = nofpexcept ADDSSrr [[MULSSrr]], killed %61, implicit $mxcsr
+  ; CHECK:   %63:gr32 = nofpexcept CVTTSS2SIrr killed %62, implicit $mxcsr
+  ; CHECK:   [[CMOV32rr:%[0-9]+]]:gr32 = CMOV32rr [[PHI]], killed %63, 4, implicit $eflags
+  ; CHECK:   [[AND64rr1:%[0-9]+]]:gr64 = AND64rr [[ADD64rr]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[SUB64rr1:%[0-9]+]]:gr64 = SUB64rr [[AND64rr1]], [[ADD64rr]], implicit-def $eflags
+  ; CHECK:   %67:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr]], implicit $mxcsr
+  ; CHECK:   %68:fr32 = nofpexcept ADDSSrr [[MULSSrr]], killed %67, implicit $mxcsr
+  ; CHECK:   %69:gr32 = nofpexcept CVTTSS2SIrr killed %68, implicit $mxcsr
+  ; CHECK:   [[CMOV32rr1:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr]], killed %69, 4, implicit $eflags
+  ; CHECK:   [[AND64rr2:%[0-9]+]]:gr64 = AND64rr [[SHL64ri]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[SUB64rr2:%[0-9]+]]:gr64 = SUB64rr [[AND64rr2]], [[SHL64ri]], implicit-def $eflags
+  ; CHECK:   %73:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr1]], implicit $mxcsr
+  ; CHECK:   %74:fr32 = nofpexcept ADDSSrr [[MULSSrr]], killed %73, implicit $mxcsr
+  ; CHECK:   %75:gr32 = nofpexcept CVTTSS2SIrr killed %74, implicit $mxcsr
+  ; CHECK:   [[CMOV32rr2:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr1]], killed %75, 4, implicit $eflags
+  ; CHECK:   [[AND64rr3:%[0-9]+]]:gr64 = AND64rr [[SHL64ri1]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[SUB64rr3:%[0-9]+]]:gr64 = SUB64rr [[AND64rr3]], [[SHL64ri1]], implicit-def $eflags
+  ; CHECK:   %79:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr2]], implicit $mxcsr
+  ; CHECK:   %80:fr32 = nofpexcept ADDSSrr [[MULSSrr]], killed %79, implicit $mxcsr
+  ; CHECK:   %81:gr32 = nofpexcept CVTTSS2SIrr killed %80, implicit $mxcsr
+  ; CHECK:   [[CMOV32rr3:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr2]], killed %81, 4, implicit $eflags
+  ; CHECK:   [[AND64rr4:%[0-9]+]]:gr64 = AND64rr [[SHL64ri2]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[SUB64rr4:%[0-9]+]]:gr64 = SUB64rr [[AND64rr4]], [[SHL64ri2]], implicit-def $eflags
+  ; CHECK:   %85:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr3]], implicit $mxcsr
+  ; CHECK:   %86:fr32 = nofpexcept ADDSSrr [[MULSSrr]], killed %85, implicit $mxcsr
+  ; CHECK:   %87:gr32 = nofpexcept CVTTSS2SIrr killed %86, implicit $mxcsr
+  ; CHECK:   [[CMOV32rr4:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr3]], killed %87, 4, implicit $eflags
+  ; CHECK:   [[AND64rr5:%[0-9]+]]:gr64 = AND64rr [[SHL64ri3]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[SUB64rr5:%[0-9]+]]:gr64 = SUB64rr [[AND64rr5]], [[SHL64ri3]], implicit-def $eflags
+  ; CHECK:   %91:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr4]], implicit $mxcsr
+  ; CHECK:   %92:fr32 = nofpexcept ADDSSrr [[MULSSrr]], killed %91, implicit $mxcsr
+  ; CHECK:   %93:gr32 = nofpexcept CVTTSS2SIrr killed %92, implicit $mxcsr
+  ; CHECK:   [[CMOV32rr5:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr4]], killed %93, 4, implicit $eflags
+  ; CHECK:   [[AND64rr6:%[0-9]+]]:gr64 = AND64rr [[SHL64ri4]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[SUB64rr6:%[0-9]+]]:gr64 = SUB64rr [[AND64rr6]], [[SHL64ri4]], implicit-def $eflags
+  ; CHECK:   %97:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr5]], implicit $mxcsr
+  ; CHECK:   %98:fr32 = nofpexcept ADDSSrr [[MULSSrr]], killed %97, implicit $mxcsr
+  ; CHECK:   %99:gr32 = nofpexcept CVTTSS2SIrr killed %98, implicit $mxcsr
+  ; CHECK:   [[CMOV32rr6:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr5]], killed %99, 4, implicit $eflags
+  ; CHECK:   [[AND64rr7:%[0-9]+]]:gr64 = AND64rr [[SHL64ri5]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[SUB64rr7:%[0-9]+]]:gr64 = SUB64rr [[AND64rr7]], [[SHL64ri5]], implicit-def $eflags
+  ; CHECK:   %103:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr6]], implicit $mxcsr
+  ; CHECK:   %104:fr32 = nofpexcept ADDSSrr [[MULSSrr]], killed %103, implicit $mxcsr
+  ; CHECK:   %105:gr32 = nofpexcept CVTTSS2SIrr killed %104, implicit $mxcsr
+  ; CHECK:   [[CMOV32rr7:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr6]], killed %105, 4, implicit $eflags
+  ; CHECK:   [[AND64rr8:%[0-9]+]]:gr64 = AND64rr [[SHL64ri6]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[SUB64rr8:%[0-9]+]]:gr64 = SUB64rr [[AND64rr8]], [[SHL64ri6]], implicit-def $eflags
+  ; CHECK:   %109:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr7]], implicit $mxcsr
+  ; CHECK:   %110:fr32 = nofpexcept ADDSSrr [[MULSSrr]], killed %109, implicit $mxcsr
+  ; CHECK:   %111:gr32 = nofpexcept CVTTSS2SIrr killed %110, implicit $mxcsr
+  ; CHECK:   [[CMOV32rr8:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr7]], killed %111, 4, implicit $eflags
+  ; CHECK:   [[AND64rr9:%[0-9]+]]:gr64 = AND64rr [[SHL64ri7]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[SUB64rr9:%[0-9]+]]:gr64 = SUB64rr [[AND64rr9]], [[SHL64ri7]], implicit-def $eflags
+  ; CHECK:   %115:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr8]], implicit $mxcsr
+  ; CHECK:   %116:fr32 = nofpexcept ADDSSrr [[MULSSrr]], killed %115, implicit $mxcsr
+  ; CHECK:   %117:gr32 = nofpexcept CVTTSS2SIrr killed %116, implicit $mxcsr
+  ; CHECK:   [[CMOV32rr9:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr8]], killed %117, 4, implicit $eflags
+  ; CHECK:   [[AND64rr10:%[0-9]+]]:gr64 = AND64rr [[SHL64ri8]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[SUB64rr10:%[0-9]+]]:gr64 = SUB64rr [[AND64rr10]], [[SHL64ri8]], implicit-def $eflags
+  ; CHECK:   %121:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr9]], implicit $mxcsr
+  ; CHECK:   %122:fr32 = nofpexcept ADDSSrr [[MULSSrr]], killed %121, implicit $mxcsr
+  ; CHECK:   %123:gr32 = nofpexcept CVTTSS2SIrr killed %122, implicit $mxcsr
+  ; CHECK:   [[CMOV32rr10:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr9]], killed %123, 4, implicit $eflags
+  ; CHECK:   [[AND64rr11:%[0-9]+]]:gr64 = AND64rr [[SHL64ri9]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[SUB64rr11:%[0-9]+]]:gr64 = SUB64rr [[AND64rr11]], [[SHL64ri9]], implicit-def $eflags
+  ; CHECK:   %127:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr10]], implicit $mxcsr
+  ; CHECK:   %128:fr32 = nofpexcept ADDSSrr [[MULSSrr]], killed %127, implicit $mxcsr
+  ; CHECK:   %129:gr32 = nofpexcept CVTTSS2SIrr killed %128, implicit $mxcsr
+  ; CHECK:   [[CMOV32rr11:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr10]], killed %129, 4, implicit $eflags
+  ; CHECK:   [[AND64rr12:%[0-9]+]]:gr64 = AND64rr [[SHL64ri10]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[SUB64rr12:%[0-9]+]]:gr64 = SUB64rr [[AND64rr12]], [[SHL64ri10]], implicit-def $eflags
+  ; CHECK:   %133:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr11]], implicit $mxcsr
+  ; CHECK:   %134:fr32 = nofpexcept ADDSSrr [[MULSSrr]], killed %133, implicit $mxcsr
+  ; CHECK:   %135:gr32 = nofpexcept CVTTSS2SIrr killed %134, implicit $mxcsr
+  ; CHECK:   [[CMOV32rr12:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr11]], killed %135, 4, implicit $eflags
+  ; CHECK:   [[AND64rr13:%[0-9]+]]:gr64 = AND64rr [[SHL64ri11]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[SUB64rr13:%[0-9]+]]:gr64 = SUB64rr [[AND64rr13]], [[SHL64ri11]], implicit-def $eflags
+  ; CHECK:   %139:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr12]], implicit $mxcsr
+  ; CHECK:   %140:fr32 = nofpexcept ADDSSrr [[MULSSrr]], killed %139, implicit $mxcsr
+  ; CHECK:   %141:gr32 = nofpexcept CVTTSS2SIrr killed %140, implicit $mxcsr
+  ; CHECK:   [[CMOV32rr13:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr12]], killed %141, 4, implicit $eflags
+  ; CHECK:   [[AND64rr14:%[0-9]+]]:gr64 = AND64rr [[SHL64ri12]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[SUB64rr14:%[0-9]+]]:gr64 = SUB64rr [[AND64rr14]], [[SHL64ri12]], implicit-def $eflags
+  ; CHECK:   %145:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr13]], implicit $mxcsr
+  ; CHECK:   %146:fr32 = nofpexcept ADDSSrr [[MULSSrr]], killed %145, implicit $mxcsr
+  ; CHECK:   %147:gr32 = nofpexcept CVTTSS2SIrr killed %146, implicit $mxcsr
+  ; CHECK:   [[CMOV32rr14:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr13]], killed %147, 4, implicit $eflags
+  ; CHECK:   [[AND64rr15:%[0-9]+]]:gr64 = AND64rr [[SHL64ri13]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[SUB64rr15:%[0-9]+]]:gr64 = SUB64rr [[AND64rr15]], [[SHL64ri13]], implicit-def $eflags
+  ; CHECK:   %151:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr14]], implicit $mxcsr
+  ; CHECK:   %152:fr32 = nofpexcept ADDSSrr [[MULSSrr]], killed %151, implicit $mxcsr
+  ; CHECK:   %153:gr32 = nofpexcept CVTTSS2SIrr killed %152, implicit $mxcsr
+  ; CHECK:   [[CMOV32rr15:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr14]], killed %153, 4, implicit $eflags
+  ; CHECK:   [[AND64rr16:%[0-9]+]]:gr64 = AND64rr [[SHL64ri14]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[SUB64rr16:%[0-9]+]]:gr64 = SUB64rr [[AND64rr16]], [[SHL64ri14]], implicit-def $eflags
+  ; CHECK:   %157:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr15]], implicit $mxcsr
+  ; CHECK:   %158:fr32 = nofpexcept ADDSSrr [[MULSSrr]], killed %157, implicit $mxcsr
+  ; CHECK:   %159:gr32 = nofpexcept CVTTSS2SIrr killed %158, implicit $mxcsr
+  ; CHECK:   [[CMOV32rr16:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr15]], killed %159, 4, implicit $eflags
+  ; CHECK:   [[AND64rr17:%[0-9]+]]:gr64 = AND64rr [[SHL64ri15]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[SUB64rr17:%[0-9]+]]:gr64 = SUB64rr [[AND64rr17]], [[SHL64ri15]], implicit-def $eflags
+  ; CHECK:   %163:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr16]], implicit $mxcsr
+  ; CHECK:   %164:fr32 = nofpexcept ADDSSrr [[MULSSrr]], killed %163, implicit $mxcsr
+  ; CHECK:   %165:gr32 = nofpexcept CVTTSS2SIrr killed %164, implicit $mxcsr
+  ; CHECK:   [[CMOV32rr17:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr16]], killed %165, 4, implicit $eflags
+  ; CHECK:   [[AND64rr18:%[0-9]+]]:gr64 = AND64rr [[SHL64ri16]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[SUB64rr18:%[0-9]+]]:gr64 = SUB64rr [[AND64rr18]], [[SHL64ri16]], implicit-def $eflags
+  ; CHECK:   %169:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr17]], implicit $mxcsr
+  ; CHECK:   %170:fr32 = nofpexcept ADDSSrr [[MULSSrr]], killed %169, implicit $mxcsr
+  ; CHECK:   %171:gr32 = nofpexcept CVTTSS2SIrr killed %170, implicit $mxcsr
+  ; CHECK:   [[CMOV32rr18:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr17]], killed %171, 4, implicit $eflags
+  ; CHECK:   [[AND64rr19:%[0-9]+]]:gr64 = AND64rr [[SHL64ri17]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[SUB64rr19:%[0-9]+]]:gr64 = SUB64rr [[AND64rr19]], [[SHL64ri17]], implicit-def $eflags
+  ; CHECK:   %175:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr18]], implicit $mxcsr
+  ; CHECK:   %176:fr32 = nofpexcept ADDSSrr [[MULSSrr]], killed %175, implicit $mxcsr
+  ; CHECK:   %177:gr32 = nofpexcept CVTTSS2SIrr killed %176, implicit $mxcsr
+  ; CHECK:   [[CMOV32rr19:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr18]], killed %177, 4, implicit $eflags
+  ; CHECK:   [[AND64rr20:%[0-9]+]]:gr64 = AND64rr [[SHL64ri18]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[SUB64rr20:%[0-9]+]]:gr64 = SUB64rr [[AND64rr20]], [[SHL64ri18]], implicit-def $eflags
+  ; CHECK:   %181:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr19]], implicit $mxcsr
+  ; CHECK:   %182:fr32 = nofpexcept ADDSSrr [[MULSSrr]], killed %181, implicit $mxcsr
+  ; CHECK:   %183:gr32 = nofpexcept CVTTSS2SIrr killed %182, implicit $mxcsr
+  ; CHECK:   [[CMOV32rr20:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr19]], killed %183, 4, implicit $eflags
+  ; CHECK:   [[MULSSrr1:%[0-9]+]]:fr32 = MULSSrr %56, [[MOVSSrm_alt3]], implicit $mxcsr
+  ; CHECK:   [[AND64rr21:%[0-9]+]]:gr64 = AND64rr [[MOV64rm1]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[XOR64rr:%[0-9]+]]:gr64 = XOR64rr [[AND64rr21]], [[MOV64rm1]], implicit-def dead $eflags
+  ; CHECK:   [[AND64rr22:%[0-9]+]]:gr64 = AND64rr [[MOV64rm]], [[CMOV64rr1]], implicit-def dead $eflags
+  ; CHECK:   %189:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr20]], implicit $mxcsr
+  ; CHECK:   %190:fr32 = nofpexcept ADDSSrr [[MULSSrr1]], killed %189, implicit $mxcsr
+  ; CHECK:   %191:gr32 = nofpexcept CVTTSS2SIrr killed %190, implicit $mxcsr
+  ; CHECK:   [[OR64rr:%[0-9]+]]:gr64 = OR64rr [[XOR64rr]], killed [[AND64rr22]], implicit-def $eflags
+  ; CHECK:   [[CMOV32rr21:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr20]], killed %191, 4, implicit $eflags
+  ; CHECK:   [[AND64rr23:%[0-9]+]]:gr64 = AND64rr [[ADD64rr1]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[XOR64rr1:%[0-9]+]]:gr64 = XOR64rr [[AND64rr23]], [[ADD64rr1]], implicit-def dead $eflags
+  ; CHECK:   [[AND64rr24:%[0-9]+]]:gr64 = AND64rr [[ADD64rr]], [[CMOV64rr1]], implicit-def dead $eflags
+  ; CHECK:   %197:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr21]], implicit $mxcsr
+  ; CHECK:   %198:fr32 = nofpexcept ADDSSrr [[MULSSrr1]], killed %197, implicit $mxcsr
+  ; CHECK:   %199:gr32 = nofpexcept CVTTSS2SIrr killed %198, implicit $mxcsr
+  ; CHECK:   [[OR64rr1:%[0-9]+]]:gr64 = OR64rr [[XOR64rr1]], killed [[AND64rr24]], implicit-def $eflags
+  ; CHECK:   [[CMOV32rr22:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr21]], killed %199, 4, implicit $eflags
+  ; CHECK:   [[AND64rr25:%[0-9]+]]:gr64 = AND64rr [[SHL64ri19]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[XOR64rr2:%[0-9]+]]:gr64 = XOR64rr [[AND64rr25]], [[SHL64ri19]], implicit-def dead $eflags
+  ; CHECK:   [[AND64rr26:%[0-9]+]]:gr64 = AND64rr [[SHL64ri]], [[CMOV64rr1]], implicit-def dead $eflags
+  ; CHECK:   %205:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr22]], implicit $mxcsr
+  ; CHECK:   %206:fr32 = nofpexcept ADDSSrr [[MULSSrr1]], killed %205, implicit $mxcsr
+  ; CHECK:   %207:gr32 = nofpexcept CVTTSS2SIrr killed %206, implicit $mxcsr
+  ; CHECK:   [[OR64rr2:%[0-9]+]]:gr64 = OR64rr [[XOR64rr2]], killed [[AND64rr26]], implicit-def $eflags
+  ; CHECK:   [[CMOV32rr23:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr22]], killed %207, 4, implicit $eflags
+  ; CHECK:   [[AND64rr27:%[0-9]+]]:gr64 = AND64rr [[SHL64ri20]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[XOR64rr3:%[0-9]+]]:gr64 = XOR64rr [[AND64rr27]], [[SHL64ri20]], implicit-def dead $eflags
+  ; CHECK:   [[AND64rr28:%[0-9]+]]:gr64 = AND64rr [[SHL64ri1]], [[CMOV64rr1]], implicit-def dead $eflags
+  ; CHECK:   %213:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr23]], implicit $mxcsr
+  ; CHECK:   %214:fr32 = nofpexcept ADDSSrr [[MULSSrr1]], killed %213, implicit $mxcsr
+  ; CHECK:   %215:gr32 = nofpexcept CVTTSS2SIrr killed %214, implicit $mxcsr
+  ; CHECK:   [[OR64rr3:%[0-9]+]]:gr64 = OR64rr [[XOR64rr3]], killed [[AND64rr28]], implicit-def $eflags
+  ; CHECK:   [[CMOV32rr24:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr23]], killed %215, 4, implicit $eflags
+  ; CHECK:   [[AND64rr29:%[0-9]+]]:gr64 = AND64rr [[SHL64ri21]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[XOR64rr4:%[0-9]+]]:gr64 = XOR64rr [[AND64rr29]], [[SHL64ri21]], implicit-def dead $eflags
+  ; CHECK:   [[AND64rr30:%[0-9]+]]:gr64 = AND64rr [[SHL64ri2]], [[CMOV64rr1]], implicit-def dead $eflags
+  ; CHECK:   %221:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr24]], implicit $mxcsr
+  ; CHECK:   %222:fr32 = nofpexcept ADDSSrr [[MULSSrr1]], killed %221, implicit $mxcsr
+  ; CHECK:   %223:gr32 = nofpexcept CVTTSS2SIrr killed %222, implicit $mxcsr
+  ; CHECK:   [[OR64rr4:%[0-9]+]]:gr64 = OR64rr [[XOR64rr4]], killed [[AND64rr30]], implicit-def $eflags
+  ; CHECK:   [[CMOV32rr25:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr24]], killed %223, 4, implicit $eflags
+  ; CHECK:   [[AND64rr31:%[0-9]+]]:gr64 = AND64rr [[SHL64ri22]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[XOR64rr5:%[0-9]+]]:gr64 = XOR64rr [[AND64rr31]], [[SHL64ri22]], implicit-def dead $eflags
+  ; CHECK:   [[AND64rr32:%[0-9]+]]:gr64 = AND64rr [[SHL64ri3]], [[CMOV64rr1]], implicit-def dead $eflags
+  ; CHECK:   %229:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr25]], implicit $mxcsr
+  ; CHECK:   %230:fr32 = nofpexcept ADDSSrr [[MULSSrr1]], killed %229, implicit $mxcsr
+  ; CHECK:   %231:gr32 = nofpexcept CVTTSS2SIrr killed %230, implicit $mxcsr
+  ; CHECK:   [[OR64rr5:%[0-9]+]]:gr64 = OR64rr [[XOR64rr5]], killed [[AND64rr32]], implicit-def $eflags
+  ; CHECK:   [[CMOV32rr26:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr25]], killed %231, 4, implicit $eflags
+  ; CHECK:   [[AND64rr33:%[0-9]+]]:gr64 = AND64rr [[SHL64ri23]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[XOR64rr6:%[0-9]+]]:gr64 = XOR64rr [[AND64rr33]], [[SHL64ri23]], implicit-def dead $eflags
+  ; CHECK:   [[AND64rr34:%[0-9]+]]:gr64 = AND64rr [[SHL64ri4]], [[CMOV64rr1]], implicit-def dead $eflags
+  ; CHECK:   %237:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr26]], implicit $mxcsr
+  ; CHECK:   %238:fr32 = nofpexcept ADDSSrr [[MULSSrr1]], killed %237, implicit $mxcsr
+  ; CHECK:   %239:gr32 = nofpexcept CVTTSS2SIrr killed %238, implicit $mxcsr
+  ; CHECK:   [[OR64rr6:%[0-9]+]]:gr64 = OR64rr [[XOR64rr6]], killed [[AND64rr34]], implicit-def $eflags
+  ; CHECK:   [[CMOV32rr27:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr26]], killed %239, 4, implicit $eflags
+  ; CHECK:   [[AND64rr35:%[0-9]+]]:gr64 = AND64rr [[SHL64ri24]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[XOR64rr7:%[0-9]+]]:gr64 = XOR64rr [[AND64rr35]], [[SHL64ri24]], implicit-def dead $eflags
+  ; CHECK:   [[AND64rr36:%[0-9]+]]:gr64 = AND64rr [[SHL64ri5]], [[CMOV64rr1]], implicit-def dead $eflags
+  ; CHECK:   %245:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr27]], implicit $mxcsr
+  ; CHECK:   %246:fr32 = nofpexcept ADDSSrr [[MULSSrr1]], killed %245, implicit $mxcsr
+  ; CHECK:   %247:gr32 = nofpexcept CVTTSS2SIrr killed %246, implicit $mxcsr
+  ; CHECK:   [[OR64rr7:%[0-9]+]]:gr64 = OR64rr [[XOR64rr7]], killed [[AND64rr36]], implicit-def $eflags
+  ; CHECK:   [[CMOV32rr28:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr27]], killed %247, 4, implicit $eflags
+  ; CHECK:   [[AND64rr37:%[0-9]+]]:gr64 = AND64rr [[SHL64ri25]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[XOR64rr8:%[0-9]+]]:gr64 = XOR64rr [[AND64rr37]], [[SHL64ri25]], implicit-def dead $eflags
+  ; CHECK:   [[AND64rr38:%[0-9]+]]:gr64 = AND64rr [[SHL64ri6]], [[CMOV64rr1]], implicit-def dead $eflags
+  ; CHECK:   %253:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr28]], implicit $mxcsr
+  ; CHECK:   %254:fr32 = nofpexcept ADDSSrr [[MULSSrr1]], killed %253, implicit $mxcsr
+  ; CHECK:   %255:gr32 = nofpexcept CVTTSS2SIrr killed %254, implicit $mxcsr
+  ; CHECK:   [[OR64rr8:%[0-9]+]]:gr64 = OR64rr [[XOR64rr8]], killed [[AND64rr38]], implicit-def $eflags
+  ; CHECK:   [[CMOV32rr29:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr28]], killed %255, 4, implicit $eflags
+  ; CHECK:   [[AND64rr39:%[0-9]+]]:gr64 = AND64rr [[SHL64ri26]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[XOR64rr9:%[0-9]+]]:gr64 = XOR64rr [[AND64rr39]], [[SHL64ri26]], implicit-def dead $eflags
+  ; CHECK:   [[AND64rr40:%[0-9]+]]:gr64 = AND64rr [[SHL64ri7]], [[CMOV64rr1]], implicit-def dead $eflags
+  ; CHECK:   %261:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr29]], implicit $mxcsr
+  ; CHECK:   %262:fr32 = nofpexcept ADDSSrr [[MULSSrr1]], killed %261, implicit $mxcsr
+  ; CHECK:   %263:gr32 = nofpexcept CVTTSS2SIrr killed %262, implicit $mxcsr
+  ; CHECK:   [[OR64rr9:%[0-9]+]]:gr64 = OR64rr [[XOR64rr9]], killed [[AND64rr40]], implicit-def $eflags
+  ; CHECK:   [[CMOV32rr30:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr29]], killed %263, 4, implicit $eflags
+  ; CHECK:   [[AND64rr41:%[0-9]+]]:gr64 = AND64rr [[SHL64ri27]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[XOR64rr10:%[0-9]+]]:gr64 = XOR64rr [[AND64rr41]], [[SHL64ri27]], implicit-def dead $eflags
+  ; CHECK:   [[AND64rr42:%[0-9]+]]:gr64 = AND64rr [[SHL64ri8]], [[CMOV64rr1]], implicit-def dead $eflags
+  ; CHECK:   %269:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr30]], implicit $mxcsr
+  ; CHECK:   %270:fr32 = nofpexcept ADDSSrr [[MULSSrr1]], killed %269, implicit $mxcsr
+  ; CHECK:   %271:gr32 = nofpexcept CVTTSS2SIrr killed %270, implicit $mxcsr
+  ; CHECK:   [[OR64rr10:%[0-9]+]]:gr64 = OR64rr [[XOR64rr10]], killed [[AND64rr42]], implicit-def $eflags
+  ; CHECK:   [[CMOV32rr31:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr30]], killed %271, 4, implicit $eflags
+  ; CHECK:   [[AND64rr43:%[0-9]+]]:gr64 = AND64rr [[SHL64ri28]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[XOR64rr11:%[0-9]+]]:gr64 = XOR64rr [[AND64rr43]], [[SHL64ri28]], implicit-def dead $eflags
+  ; CHECK:   [[AND64rr44:%[0-9]+]]:gr64 = AND64rr [[SHL64ri9]], [[CMOV64rr1]], implicit-def dead $eflags
+  ; CHECK:   %277:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr31]], implicit $mxcsr
+  ; CHECK:   %278:fr32 = nofpexcept ADDSSrr [[MULSSrr1]], killed %277, implicit $mxcsr
+  ; CHECK:   %279:gr32 = nofpexcept CVTTSS2SIrr killed %278, implicit $mxcsr
+  ; CHECK:   [[OR64rr11:%[0-9]+]]:gr64 = OR64rr [[XOR64rr11]], killed [[AND64rr44]], implicit-def $eflags
+  ; CHECK:   [[CMOV32rr32:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr31]], killed %279, 4, implicit $eflags
+  ; CHECK:   [[AND64rr45:%[0-9]+]]:gr64 = AND64rr [[SHL64ri29]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[XOR64rr12:%[0-9]+]]:gr64 = XOR64rr [[AND64rr45]], [[SHL64ri29]], implicit-def dead $eflags
+  ; CHECK:   [[AND64rr46:%[0-9]+]]:gr64 = AND64rr [[SHL64ri10]], [[CMOV64rr1]], implicit-def dead $eflags
+  ; CHECK:   %285:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr32]], implicit $mxcsr
+  ; CHECK:   %286:fr32 = nofpexcept ADDSSrr [[MULSSrr1]], killed %285, implicit $mxcsr
+  ; CHECK:   %287:gr32 = nofpexcept CVTTSS2SIrr killed %286, implicit $mxcsr
+  ; CHECK:   [[OR64rr12:%[0-9]+]]:gr64 = OR64rr [[XOR64rr12]], killed [[AND64rr46]], implicit-def $eflags
+  ; CHECK:   [[CMOV32rr33:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr32]], killed %287, 4, implicit $eflags
+  ; CHECK:   [[AND64rr47:%[0-9]+]]:gr64 = AND64rr [[SHL64ri30]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[XOR64rr13:%[0-9]+]]:gr64 = XOR64rr [[AND64rr47]], [[SHL64ri30]], implicit-def dead $eflags
+  ; CHECK:   [[AND64rr48:%[0-9]+]]:gr64 = AND64rr [[SHL64ri11]], [[CMOV64rr1]], implicit-def dead $eflags
+  ; CHECK:   %293:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr33]], implicit $mxcsr
+  ; CHECK:   %294:fr32 = nofpexcept ADDSSrr [[MULSSrr1]], killed %293, implicit $mxcsr
+  ; CHECK:   %295:gr32 = nofpexcept CVTTSS2SIrr killed %294, implicit $mxcsr
+  ; CHECK:   [[OR64rr13:%[0-9]+]]:gr64 = OR64rr [[XOR64rr13]], killed [[AND64rr48]], implicit-def $eflags
+  ; CHECK:   [[CMOV32rr34:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr33]], killed %295, 4, implicit $eflags
+  ; CHECK:   [[AND64rr49:%[0-9]+]]:gr64 = AND64rr [[SHL64ri31]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[XOR64rr14:%[0-9]+]]:gr64 = XOR64rr [[AND64rr49]], [[SHL64ri31]], implicit-def dead $eflags
+  ; CHECK:   [[AND64rr50:%[0-9]+]]:gr64 = AND64rr [[SHL64ri12]], [[CMOV64rr1]], implicit-def dead $eflags
+  ; CHECK:   %301:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr34]], implicit $mxcsr
+  ; CHECK:   %302:fr32 = nofpexcept ADDSSrr [[MULSSrr1]], killed %301, implicit $mxcsr
+  ; CHECK:   %303:gr32 = nofpexcept CVTTSS2SIrr killed %302, implicit $mxcsr
+  ; CHECK:   [[OR64rr14:%[0-9]+]]:gr64 = OR64rr [[XOR64rr14]], killed [[AND64rr50]], implicit-def $eflags
+  ; CHECK:   [[CMOV32rr35:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr34]], killed %303, 4, implicit $eflags
+  ; CHECK:   [[AND64rr51:%[0-9]+]]:gr64 = AND64rr [[SHL64ri32]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[XOR64rr15:%[0-9]+]]:gr64 = XOR64rr [[AND64rr51]], [[SHL64ri32]], implicit-def dead $eflags
+  ; CHECK:   [[AND64rr52:%[0-9]+]]:gr64 = AND64rr [[SHL64ri13]], [[CMOV64rr1]], implicit-def dead $eflags
+  ; CHECK:   %309:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr35]], implicit $mxcsr
+  ; CHECK:   %310:fr32 = nofpexcept ADDSSrr [[MULSSrr1]], killed %309, implicit $mxcsr
+  ; CHECK:   %311:gr32 = nofpexcept CVTTSS2SIrr killed %310, implicit $mxcsr
+  ; CHECK:   [[OR64rr15:%[0-9]+]]:gr64 = OR64rr [[XOR64rr15]], killed [[AND64rr52]], implicit-def $eflags
+  ; CHECK:   [[CMOV32rr36:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr35]], killed %311, 4, implicit $eflags
+  ; CHECK:   [[AND64rr53:%[0-9]+]]:gr64 = AND64rr [[SHL64ri33]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[XOR64rr16:%[0-9]+]]:gr64 = XOR64rr [[AND64rr53]], [[SHL64ri33]], implicit-def dead $eflags
+  ; CHECK:   [[AND64rr54:%[0-9]+]]:gr64 = AND64rr [[SHL64ri14]], [[CMOV64rr1]], implicit-def dead $eflags
+  ; CHECK:   %317:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr36]], implicit $mxcsr
+  ; CHECK:   %318:fr32 = nofpexcept ADDSSrr [[MULSSrr1]], killed %317, implicit $mxcsr
+  ; CHECK:   %319:gr32 = nofpexcept CVTTSS2SIrr killed %318, implicit $mxcsr
+  ; CHECK:   [[OR64rr16:%[0-9]+]]:gr64 = OR64rr [[XOR64rr16]], killed [[AND64rr54]], implicit-def $eflags
+  ; CHECK:   [[CMOV32rr37:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr36]], killed %319, 4, implicit $eflags
+  ; CHECK:   [[AND64rr55:%[0-9]+]]:gr64 = AND64rr [[SHL64ri34]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[XOR64rr17:%[0-9]+]]:gr64 = XOR64rr [[AND64rr55]], [[SHL64ri34]], implicit-def dead $eflags
+  ; CHECK:   [[AND64rr56:%[0-9]+]]:gr64 = AND64rr [[SHL64ri15]], [[CMOV64rr1]], implicit-def dead $eflags
+  ; CHECK:   %325:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr37]], implicit $mxcsr
+  ; CHECK:   %326:fr32 = nofpexcept ADDSSrr [[MULSSrr1]], killed %325, implicit $mxcsr
+  ; CHECK:   %327:gr32 = nofpexcept CVTTSS2SIrr killed %326, implicit $mxcsr
+  ; CHECK:   [[OR64rr17:%[0-9]+]]:gr64 = OR64rr [[XOR64rr17]], killed [[AND64rr56]], implicit-def $eflags
+  ; CHECK:   [[CMOV32rr38:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr37]], killed %327, 4, implicit $eflags
+  ; CHECK:   [[AND64rr57:%[0-9]+]]:gr64 = AND64rr [[SHL64ri35]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[XOR64rr18:%[0-9]+]]:gr64 = XOR64rr [[AND64rr57]], [[SHL64ri35]], implicit-def dead $eflags
+  ; CHECK:   [[AND64rr58:%[0-9]+]]:gr64 = AND64rr [[SHL64ri16]], [[CMOV64rr1]], implicit-def dead $eflags
+  ; CHECK:   %333:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr38]], implicit $mxcsr
+  ; CHECK:   %334:fr32 = nofpexcept ADDSSrr [[MULSSrr1]], killed %333, implicit $mxcsr
+  ; CHECK:   %335:gr32 = nofpexcept CVTTSS2SIrr killed %334, implicit $mxcsr
+  ; CHECK:   [[OR64rr18:%[0-9]+]]:gr64 = OR64rr [[XOR64rr18]], killed [[AND64rr58]], implicit-def $eflags
+  ; CHECK:   [[CMOV32rr39:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr38]], killed %335, 4, implicit $eflags
+  ; CHECK:   [[AND64rr59:%[0-9]+]]:gr64 = AND64rr [[SHL64ri36]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[XOR64rr19:%[0-9]+]]:gr64 = XOR64rr [[AND64rr59]], [[SHL64ri36]], implicit-def dead $eflags
+  ; CHECK:   [[AND64rr60:%[0-9]+]]:gr64 = AND64rr [[SHL64ri17]], [[CMOV64rr1]], implicit-def dead $eflags
+  ; CHECK:   %341:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr39]], implicit $mxcsr
+  ; CHECK:   %342:fr32 = nofpexcept ADDSSrr [[MULSSrr1]], killed %341, implicit $mxcsr
+  ; CHECK:   %343:gr32 = nofpexcept CVTTSS2SIrr killed %342, implicit $mxcsr
+  ; CHECK:   [[OR64rr19:%[0-9]+]]:gr64 = OR64rr [[XOR64rr19]], killed [[AND64rr60]], implicit-def $eflags
+  ; CHECK:   [[CMOV32rr40:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr39]], killed %343, 4, implicit $eflags
+  ; CHECK:   [[AND64rr61:%[0-9]+]]:gr64 = AND64rr [[SHL64ri37]], [[CMOV64rr]], implicit-def dead $eflags
+  ; CHECK:   [[XOR64rr20:%[0-9]+]]:gr64 = XOR64rr [[AND64rr61]], [[SHL64ri37]], implicit-def dead $eflags
+  ; CHECK:   [[AND64rr62:%[0-9]+]]:gr64 = AND64rr [[SHL64ri18]], [[CMOV64rr1]], implicit-def dead $eflags
+  ; CHECK:   %349:fr32 = nofpexcept CVTSI2SSrr [[CMOV32rr40]], implicit $mxcsr
+  ; CHECK:   %350:fr32 = nofpexcept ADDSSrr [[MULSSrr1]], killed %349, implicit $mxcsr
+  ; CHECK:   %351:gr32 = nofpexcept CVTTSS2SIrr killed %350, implicit $mxcsr
+  ; CHECK:   [[OR64rr20:%[0-9]+]]:gr64 = OR64rr [[XOR64rr20]], killed [[AND64rr62]], implicit-def $eflags
+  ; CHECK:   [[CMOV32rr41:%[0-9]+]]:gr32 = CMOV32rr [[CMOV32rr40]], killed %351, 4, implicit $eflags
+  ; CHECK:   [[MOV32r0_1:%[0-9]+]]:gr32 = MOV32r0 implicit-def dead $eflags
+  ; CHECK:   TEST8ri [[PHI1]], 1, implicit-def $eflags
+  ; CHECK:   [[COPY2:%[0-9]+]]:gr8 = COPY [[MOV32r0_1]].sub_8bit
+  ; CHECK:   JCC_1 %bb.1, 5, implicit $eflags
+  ; CHECK:   JMP_1 %bb.4
+  ; CHECK: bb.4.for.end43:
+  ; CHECK:   $eax = COPY [[CMOV32rr41]]
+  ; CHECK:   RET 0, $eax
+  bb.0.entry:
+    successors: %bb.1(0x80000000)
+    liveins: $rdi, $rsi
+
+    %47:gr64 = COPY $rsi
+    %46:gr64 = COPY $rdi
+    %50:fr32 = nofpexcept CVTSI2SSrm $rip, 1, $noreg, @off, $noreg, implicit $mxcsr :: (dereferenceable load 4 from @off)
+    %0:fr32 = nofpexcept DIVSSrm %50, $rip, 1, $noreg, %const.0, $noreg, implicit $mxcsr :: (load 4 from constant-pool)
+    %1:gr64 = MOV64rm $rip, 1, $noreg, @C4VERT, $noreg :: (dereferenceable load 8 from @C4VERT)
+    %2:gr64 = MOV64rm $rip, 1, $noreg, @C2VERT, $noreg :: (dereferenceable load 8 from @C2VERT, !tbaa !2)
+    %3:gr64 = ADD64rr %1, %1, implicit-def dead $eflags
+    %4:gr64 = SHL64ri %1, 2, implicit-def dead $eflags
+    %5:gr64 = SHL64ri %1, 3, implicit-def dead $eflags
+    %6:gr64 = SHL64ri %1, 4, implicit-def dead $eflags
+    %7:gr64 = SHL64ri %1, 5, implicit-def dead $eflags
+    %8:gr64 = SHL64ri %1, 6, implicit-def dead $eflags
+    %9:gr64 = SHL64ri %1, 7, implicit-def dead $eflags
+    %10:gr64 = SHL64ri %1, 8, implicit-def dead $eflags
+    %11:gr64 = SHL64ri %1, 9, implicit-def dead $eflags
+    %12:gr64 = SHL64ri %1, 10, implicit-def dead $eflags
+    %13:gr64 = SHL64ri %1, 11, implicit-def dead $eflags
+    %14:gr64 = SHL64ri %1, 12, implicit-def dead $eflags
+    %15:gr64 = SHL64ri %1, 13, implicit-def dead $eflags
+    %16:gr64 = SHL64ri %1, 14, implicit-def dead $eflags
+    %17:gr64 = SHL64ri %1, 15, implicit-def dead $eflags
+    %18:gr64 = SHL64ri %1, 16, implicit-def dead $eflags
+    %19:gr64 = SHL64ri %1, 17, implicit-def dead $eflags
+    %20:gr64 = SHL64ri %1, 18, implicit-def dead $eflags
+    %21:gr64 = SHL64ri %1, 19, implicit-def dead $eflags
+    %22:gr64 = SHL64ri %1, 20, implicit-def dead $eflags
+    %23:gr64 = ADD64rr %2, %2, implicit-def dead $eflags
+    %24:gr64 = SHL64ri %2, 2, implicit-def dead $eflags
+    %25:gr64 = SHL64ri %2, 3, implicit-def dead $eflags
+    %26:gr64 = SHL64ri %2, 4, implicit-def dead $eflags
+    %27:gr64 = SHL64ri %2, 5, implicit-def dead $eflags
+    %28:gr64 = SHL64ri %2, 6, implicit-def dead $eflags
+    %29:gr64 = SHL64ri %2, 7, implicit-def dead $eflags
+    %30:gr64 = SHL64ri %2, 8, implicit-def dead $eflags
+    %31:gr64 = SHL64ri %2, 9, implicit-def dead $eflags
+    %32:gr64 = SHL64ri %2, 10, implicit-def dead $eflags
+    %33:gr64 = SHL64ri %2, 11, implicit-def dead $eflags
+    %34:gr64 = SHL64ri %2, 12, implicit-def dead $eflags
+    %35:gr64 = SHL64ri %2, 13, implicit-def dead $eflags
+    %36:gr64 = SHL64ri %2, 14, implicit-def dead $eflags
+    %37:gr64 = SHL64ri %2, 15, implicit-def dead $eflags
+    %38:gr64 = SHL64ri %2, 16, implicit-def dead $eflags
+    %39:gr64 = SHL64ri %2, 17, implicit-def dead $eflags
+    %40:gr64 = SHL64ri %2, 18, implicit-def dead $eflags
+    %41:gr64 = SHL64ri %2, 19, implicit-def dead $eflags
+    %42:gr64 = SHL64ri %2, 20, implicit-def dead $eflags
+    %49:gr8 = MOV8ri 1
+    %48:gr32 = MOV32r0 implicit-def dead $eflags
+    %53:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.1, $noreg :: (load 4 from constant-pool)
+    %54:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.2, $noreg :: (load 4 from constant-pool)
+    %354:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.3, $noreg :: (load 4 from constant-pool)
+    %355:fr32 = MOVSSrm_alt $rip, 1, $noreg, %const.4, $noreg :: (load 4 from constant-pool)
+
+  bb.1.for.body:
+    successors: %bb.3(0x40000000), %bb.4(0x40000000)
+
+    %43:gr32 = PHI %48, %bb.0, %45, %bb.4
+    %44:gr8 = PHI %49, %bb.0, %51, %bb.4
+    TEST8ri %44, 1, implicit-def $eflags
+    %52:gr64 = CMOV64rr %47, %46, 5, implicit $eflags
+    JCC_1 %bb.4, 5, implicit $eflags
+
+  bb.3.for.body:
+    successors: %bb.4(0x80000000)
+    liveins: $eflags
+
+
+  bb.4.for.body:
+    successors: %bb.1(0x7c000000), %bb.2(0x04000000)
+    liveins: $eflags
+
+    %55:fr32 = PHI %54, %bb.3, %53, %bb.1
+    %56:fr32 = nofpexcept ADDSSrr %0, killed %55, implicit $mxcsr
+    %57:fr32 = MULSSrr %56, %354, implicit $mxcsr
+    %58:gr64 = CMOV64rr %46, %47, 5, implicit $eflags
+    %59:gr64 = AND64rr %1, %52, implicit-def dead $eflags
+    %60:gr64 = SUB64rr %59, %1, implicit-def $eflags
+    %61:fr32 = nofpexcept CVTSI2SSrr %43, implicit $mxcsr
+    %62:fr32 = nofpexcept ADDSSrr %57, killed %61, implicit $mxcsr
+    %63:gr32 = nofpexcept CVTTSS2SIrr killed %62, implicit $mxcsr
+    %64:gr32 = CMOV32rr %43, killed %63, 4, implicit $eflags
+    %65:gr64 = AND64rr %3, %52, implicit-def dead $eflags
+    %66:gr64 = SUB64rr %65, %3, implicit-def $eflags
+    %67:fr32 = nofpexcept CVTSI2SSrr %64, implicit $mxcsr
+    %68:fr32 = nofpexcept ADDSSrr %57, killed %67, implicit $mxcsr
+    %69:gr32 = nofpexcept CVTTSS2SIrr killed %68, implicit $mxcsr
+    %70:gr32 = CMOV32rr %64, killed %69, 4, implicit $eflags
+    %71:gr64 = AND64rr %4, %52, implicit-def dead $eflags
+    %72:gr64 = SUB64rr %71, %4, implicit-def $eflags
+    %73:fr32 = nofpexcept CVTSI2SSrr %70, implicit $mxcsr
+    %74:fr32 = nofpexcept ADDSSrr %57, killed %73, implicit $mxcsr
+    %75:gr32 = nofpexcept CVTTSS2SIrr killed %74, implicit $mxcsr
+    %76:gr32 = CMOV32rr %70, killed %75, 4, implicit $eflags
+    %77:gr64 = AND64rr %5, %52, implicit-def dead $eflags
+    %78:gr64 = SUB64rr %77, %5, implicit-def $eflags
+    %79:fr32 = nofpexcept CVTSI2SSrr %76, implicit $mxcsr
+    %80:fr32 = nofpexcept ADDSSrr %57, killed %79, implicit $mxcsr
+    %81:gr32 = nofpexcept CVTTSS2SIrr killed %80, implicit $mxcsr
+    %82:gr32 = CMOV32rr %76, killed %81, 4, implicit $eflags
+    %83:gr64 = AND64rr %6, %52, implicit-def dead $eflags
+    %84:gr64 = SUB64rr %83, %6, implicit-def $eflags
+    %85:fr32 = nofpexcept CVTSI2SSrr %82, implicit $mxcsr
+    %86:fr32 = nofpexcept ADDSSrr %57, killed %85, implicit $mxcsr
+    %87:gr32 = nofpexcept CVTTSS2SIrr killed %86, implicit $mxcsr
+    %88:gr32 = CMOV32rr %82, killed %87, 4, implicit $eflags
+    %89:gr64 = AND64rr %7, %52, implicit-def dead $eflags
+    %90:gr64 = SUB64rr %89, %7, implicit-def $eflags
+    %91:fr32 = nofpexcept CVTSI2SSrr %88, implicit $mxcsr
+    %92:fr32 = nofpexcept ADDSSrr %57, killed %91, implicit $mxcsr
+    %93:gr32 = nofpexcept CVTTSS2SIrr killed %92, implicit $mxcsr
+    %94:gr32 = CMOV32rr %88, killed %93, 4, implicit $eflags
+    %95:gr64 = AND64rr %8, %52, implicit-def dead $eflags
+    %96:gr64 = SUB64rr %95, %8, implicit-def $eflags
+    %97:fr32 = nofpexcept CVTSI2SSrr %94, implicit $mxcsr
+    %98:fr32 = nofpexcept ADDSSrr %57, killed %97, implicit $mxcsr
+    %99:gr32 = nofpexcept CVTTSS2SIrr killed %98, implicit $mxcsr
+    %100:gr32 = CMOV32rr %94, killed %99, 4, implicit $eflags
+    %101:gr64 = AND64rr %9, %52, implicit-def dead $eflags
+    %102:gr64 = SUB64rr %101, %9, implicit-def $eflags
+    %103:fr32 = nofpexcept CVTSI2SSrr %100, implicit $mxcsr
+    %104:fr32 = nofpexcept ADDSSrr %57, killed %103, implicit $mxcsr
+    %105:gr32 = nofpexcept CVTTSS2SIrr killed %104, implicit $mxcsr
+    %106:gr32 = CMOV32rr %100, killed %105, 4, implicit $eflags
+    %107:gr64 = AND64rr %10, %52, implicit-def dead $eflags
+    %108:gr64 = SUB64rr %107, %10, implicit-def $eflags
+    %109:fr32 = nofpexcept CVTSI2SSrr %106, implicit $mxcsr
+    %110:fr32 = nofpexcept ADDSSrr %57, killed %109, implicit $mxcsr
+    %111:gr32 = nofpexcept CVTTSS2SIrr killed %110, implicit $mxcsr
+    %112:gr32 = CMOV32rr %106, killed %111, 4, implicit $eflags
+    %113:gr64 = AND64rr %11, %52, implicit-def dead $eflags
+    %114:gr64 = SUB64rr %113, %11, implicit-def $eflags
+    %115:fr32 = nofpexcept CVTSI2SSrr %112, implicit $mxcsr
+    %116:fr32 = nofpexcept ADDSSrr %57, killed %115, implicit $mxcsr
+    %117:gr32 = nofpexcept CVTTSS2SIrr killed %116, implicit $mxcsr
+    %118:gr32 = CMOV32rr %112, killed %117, 4, implicit $eflags
+    %119:gr64 = AND64rr %12, %52, implicit-def dead $eflags
+    %120:gr64 = SUB64rr %119, %12, implicit-def $eflags
+    %121:fr32 = nofpexcept CVTSI2SSrr %118, implicit $mxcsr
+    %122:fr32 = nofpexcept ADDSSrr %57, killed %121, implicit $mxcsr
+    %123:gr32 = nofpexcept CVTTSS2SIrr killed %122, implicit $mxcsr
+    %124:gr32 = CMOV32rr %118, killed %123, 4, implicit $eflags
+    %125:gr64 = AND64rr %13, %52, implicit-def dead $eflags
+    %126:gr64 = SUB64rr %125, %13, implicit-def $eflags
+    %127:fr32 = nofpexcept CVTSI2SSrr %124, implicit $mxcsr
+    %128:fr32 = nofpexcept ADDSSrr %57, killed %127, implicit $mxcsr
+    %129:gr32 = nofpexcept CVTTSS2SIrr killed %128, implicit $mxcsr
+    %130:gr32 = CMOV32rr %124, killed %129, 4, implicit $eflags
+    %131:gr64 = AND64rr %14, %52, implicit-def dead $eflags
+    %132:gr64 = SUB64rr %131, %14, implicit-def $eflags
+    %133:fr32 = nofpexcept CVTSI2SSrr %130, implicit $mxcsr
+    %134:fr32 = nofpexcept ADDSSrr %57, killed %133, implicit $mxcsr
+    %135:gr32 = nofpexcept CVTTSS2SIrr killed %134, implicit $mxcsr
+    %136:gr32 = CMOV32rr %130, killed %135, 4, implicit $eflags
+    %137:gr64 = AND64rr %15, %52, implicit-def dead $eflags
+    %138:gr64 = SUB64rr %137, %15, implicit-def $eflags
+    %139:fr32 = nofpexcept CVTSI2SSrr %136, implicit $mxcsr
+    %140:fr32 = nofpexcept ADDSSrr %57, killed %139, implicit $mxcsr
+    %141:gr32 = nofpexcept CVTTSS2SIrr killed %140, implicit $mxcsr
+    %142:gr32 = CMOV32rr %136, killed %141, 4, implicit $eflags
+    %143:gr64 = AND64rr %16, %52, implicit-def dead $eflags
+    %144:gr64 = SUB64rr %143, %16, implicit-def $eflags
+    %145:fr32 = nofpexcept CVTSI2SSrr %142, implicit $mxcsr
+    %146:fr32 = nofpexcept ADDSSrr %57, killed %145, implicit $mxcsr
+    %147:gr32 = nofpexcept CVTTSS2SIrr killed %146, implicit $mxcsr
+    %148:gr32 = CMOV32rr %142, killed %147, 4, implicit $eflags
+    %149:gr64 = AND64rr %17, %52, implicit-def dead $eflags
+    %150:gr64 = SUB64rr %149, %17, implicit-def $eflags
+    %151:fr32 = nofpexcept CVTSI2SSrr %148, implicit $mxcsr
+    %152:fr32 = nofpexcept ADDSSrr %57, killed %151, implicit $mxcsr
+    %153:gr32 = nofpexcept CVTTSS2SIrr killed %152, implicit $mxcsr
+    %154:gr32 = CMOV32rr %148, killed %153, 4, implicit $eflags
+    %155:gr64 = AND64rr %18, %52, implicit-def dead $eflags
+    %156:gr64 = SUB64rr %155, %18, implicit-def $eflags
+    %157:fr32 = nofpexcept CVTSI2SSrr %154, implicit $mxcsr
+    %158:fr32 = nofpexcept ADDSSrr %57, killed %157, implicit $mxcsr
+    %159:gr32 = nofpexcept CVTTSS2SIrr killed %158, implicit $mxcsr
+    %160:gr32 = CMOV32rr %154, killed %159, 4, implicit $eflags
+    %161:gr64 = AND64rr %19, %52, implicit-def dead $eflags
+    %162:gr64 = SUB64rr %161, %19, implicit-def $eflags
+    %163:fr32 = nofpexcept CVTSI2SSrr %160, implicit $mxcsr
+    %164:fr32 = nofpexcept ADDSSrr %57, killed %163, implicit $mxcsr
+    %165:gr32 = nofpexcept CVTTSS2SIrr killed %164, implicit $mxcsr
+    %166:gr32 = CMOV32rr %160, killed %165, 4, implicit $eflags
+    %167:gr64 = AND64rr %20, %52, implicit-def dead $eflags
+    %168:gr64 = SUB64rr %167, %20, implicit-def $eflags
+    %169:fr32 = nofpexcept CVTSI2SSrr %166, implicit $mxcsr
+    %170:fr32 = nofpexcept ADDSSrr %57, killed %169, implicit $mxcsr
+    %171:gr32 = nofpexcept CVTTSS2SIrr killed %170, implicit $mxcsr
+    %172:gr32 = CMOV32rr %166, killed %171, 4, implicit $eflags
+    %173:gr64 = AND64rr %21, %52, implicit-def dead $eflags
+    %174:gr64 = SUB64rr %173, %21, implicit-def $eflags
+    %175:fr32 = nofpexcept CVTSI2SSrr %172, implicit $mxcsr
+    %176:fr32 = nofpexcept ADDSSrr %57, killed %175, implicit $mxcsr
+    %177:gr32 = nofpexcept CVTTSS2SIrr killed %176, implicit $mxcsr
+    %178:gr32 = CMOV32rr %172, killed %177, 4, implicit $eflags
+    %179:gr64 = AND64rr %22, %52, implicit-def dead $eflags
+    %180:gr64 = SUB64rr %179, %22, implicit-def $eflags
+    %181:fr32 = nofpexcept CVTSI2SSrr %178, implicit $mxcsr
+    %182:fr32 = nofpexcept ADDSSrr %57, killed %181, implicit $mxcsr
+    %183:gr32 = nofpexcept CVTTSS2SIrr killed %182, implicit $mxcsr
+    %184:gr32 = CMOV32rr %178, killed %183, 4, implicit $eflags
+    %185:fr32 = MULSSrr %56, %355, implicit $mxcsr
+    %186:gr64 = AND64rr %2, %52, implicit-def dead $eflags
+    %187:gr64 = XOR64rr %186, %2, implicit-def dead $eflags
+    %188:gr64 = AND64rr %1, %58, implicit-def dead $eflags
+    %189:fr32 = nofpexcept CVTSI2SSrr %184, implicit $mxcsr
+    %190:fr32 = nofpexcept ADDSSrr %185, killed %189, implicit $mxcsr
+    %191:gr32 = nofpexcept CVTTSS2SIrr killed %190, implicit $mxcsr
+    %192:gr64 = OR64rr %187, killed %188, implicit-def $eflags
+    %193:gr32 = CMOV32rr %184, killed %191, 4, implicit $eflags
+    %194:gr64 = AND64rr %23, %52, implicit-def dead $eflags
+    %195:gr64 = XOR64rr %194, %23, implicit-def dead $eflags
+    %196:gr64 = AND64rr %3, %58, implicit-def dead $eflags
+    %197:fr32 = nofpexcept CVTSI2SSrr %193, implicit $mxcsr
+    %198:fr32 = nofpexcept ADDSSrr %185, killed %197, implicit $mxcsr
+    %199:gr32 = nofpexcept CVTTSS2SIrr killed %198, implicit $mxcsr
+    %200:gr64 = OR64rr %195, killed %196, implicit-def $eflags
+    %201:gr32 = CMOV32rr %193, killed %199, 4, implicit $eflags
+    %202:gr64 = AND64rr %24, %52, implicit-def dead $eflags
+    %203:gr64 = XOR64rr %202, %24, implicit-def dead $eflags
+    %204:gr64 = AND64rr %4, %58, implicit-def dead $eflags
+    %205:fr32 = nofpexcept CVTSI2SSrr %201, implicit $mxcsr
+    %206:fr32 = nofpexcept ADDSSrr %185, killed %205, implicit $mxcsr
+    %207:gr32 = nofpexcept CVTTSS2SIrr killed %206, implicit $mxcsr
+    %208:gr64 = OR64rr %203, killed %204, implicit-def $eflags
+    %209:gr32 = CMOV32rr %201, killed %207, 4, implicit $eflags
+    %210:gr64 = AND64rr %25, %52, implicit-def dead $eflags
+    %211:gr64 = XOR64rr %210, %25, implicit-def dead $eflags
+    %212:gr64 = AND64rr %5, %58, implicit-def dead $eflags
+    %213:fr32 = nofpexcept CVTSI2SSrr %209, implicit $mxcsr
+    %214:fr32 = nofpexcept ADDSSrr %185, killed %213, implicit $mxcsr
+    %215:gr32 = nofpexcept CVTTSS2SIrr killed %214, implicit $mxcsr
+    %216:gr64 = OR64rr %211, killed %212, implicit-def $eflags
+    %217:gr32 = CMOV32rr %209, killed %215, 4, implicit $eflags
+    %218:gr64 = AND64rr %26, %52, implicit-def dead $eflags
+    %219:gr64 = XOR64rr %218, %26, implicit-def dead $eflags
+    %220:gr64 = AND64rr %6, %58, implicit-def dead $eflags
+    %221:fr32 = nofpexcept CVTSI2SSrr %217, implicit $mxcsr
+    %222:fr32 = nofpexcept ADDSSrr %185, killed %221, implicit $mxcsr
+    %223:gr32 = nofpexcept CVTTSS2SIrr killed %222, implicit $mxcsr
+    %224:gr64 = OR64rr %219, killed %220, implicit-def $eflags
+    %225:gr32 = CMOV32rr %217, killed %223, 4, implicit $eflags
+    %226:gr64 = AND64rr %27, %52, implicit-def dead $eflags
+    %227:gr64 = XOR64rr %226, %27, implicit-def dead $eflags
+    %228:gr64 = AND64rr %7, %58, implicit-def dead $eflags
+    %229:fr32 = nofpexcept CVTSI2SSrr %225, implicit $mxcsr
+    %230:fr32 = nofpexcept ADDSSrr %185, killed %229, implicit $mxcsr
+    %231:gr32 = nofpexcept CVTTSS2SIrr killed %230, implicit $mxcsr
+    %232:gr64 = OR64rr %227, killed %228, implicit-def $eflags
+    %233:gr32 = CMOV32rr %225, killed %231, 4, implicit $eflags
+    %234:gr64 = AND64rr %28, %52, implicit-def dead $eflags
+    %235:gr64 = XOR64rr %234, %28, implicit-def dead $eflags
+    %236:gr64 = AND64rr %8, %58, implicit-def dead $eflags
+    %237:fr32 = nofpexcept CVTSI2SSrr %233, implicit $mxcsr
+    %238:fr32 = nofpexcept ADDSSrr %185, killed %237, implicit $mxcsr
+    %239:gr32 = nofpexcept CVTTSS2SIrr killed %238, implicit $mxcsr
+    %240:gr64 = OR64rr %235, killed %236, implicit-def $eflags
+    %241:gr32 = CMOV32rr %233, killed %239, 4, implicit $eflags
+    %242:gr64 = AND64rr %29, %52, implicit-def dead $eflags
+    %243:gr64 = XOR64rr %242, %29, implicit-def dead $eflags
+    %244:gr64 = AND64rr %9, %58, implicit-def dead $eflags
+    %245:fr32 = nofpexcept CVTSI2SSrr %241, implicit $mxcsr
+    %246:fr32 = nofpexcept ADDSSrr %185, killed %245, implicit $mxcsr
+    %247:gr32 = nofpexcept CVTTSS2SIrr killed %246, implicit $mxcsr
+    %248:gr64 = OR64rr %243, killed %244, implicit-def $eflags
+    %249:gr32 = CMOV32rr %241, killed %247, 4, implicit $eflags
+    %250:gr64 = AND64rr %30, %52, implicit-def dead $eflags
+    %251:gr64 = XOR64rr %250, %30, implicit-def dead $eflags
+    %252:gr64 = AND64rr %10, %58, implicit-def dead $eflags
+    %253:fr32 = nofpexcept CVTSI2SSrr %249, implicit $mxcsr
+    %254:fr32 = nofpexcept ADDSSrr %185, killed %253, implicit $mxcsr
+    %255:gr32 = nofpexcept CVTTSS2SIrr killed %254, implicit $mxcsr
+    %256:gr64 = OR64rr %251, killed %252, implicit-def $eflags
+    %257:gr32 = CMOV32rr %249, killed %255, 4, implicit $eflags
+    %258:gr64 = AND64rr %31, %52, implicit-def dead $eflags
+    %259:gr64 = XOR64rr %258, %31, implicit-def dead $eflags
+    %260:gr64 = AND64rr %11, %58, implicit-def dead $eflags
+    %261:fr32 = nofpexcept CVTSI2SSrr %257, implicit $mxcsr
+    %262:fr32 = nofpexcept ADDSSrr %185, killed %261, implicit $mxcsr
+    %263:gr32 = nofpexcept CVTTSS2SIrr killed %262, implicit $mxcsr
+    %264:gr64 = OR64rr %259, killed %260, implicit-def $eflags
+    %265:gr32 = CMOV32rr %257, killed %263, 4, implicit $eflags
+    %266:gr64 = AND64rr %32, %52, implicit-def dead $eflags
+    %267:gr64 = XOR64rr %266, %32, implicit-def dead $eflags
+    %268:gr64 = AND64rr %12, %58, implicit-def dead $eflags
+    %269:fr32 = nofpexcept CVTSI2SSrr %265, implicit $mxcsr
+    %270:fr32 = nofpexcept ADDSSrr %185, killed %269, implicit $mxcsr
+    %271:gr32 = nofpexcept CVTTSS2SIrr killed %270, implicit $mxcsr
+    %272:gr64 = OR64rr %267, killed %268, implicit-def $eflags
+    %273:gr32 = CMOV32rr %265, killed %271, 4, implicit $eflags
+    %274:gr64 = AND64rr %33, %52, implicit-def dead $eflags
+    %275:gr64 = XOR64rr %274, %33, implicit-def dead $eflags
+    %276:gr64 = AND64rr %13, %58, implicit-def dead $eflags
+    %277:fr32 = nofpexcept CVTSI2SSrr %273, implicit $mxcsr
+    %278:fr32 = nofpexcept ADDSSrr %185, killed %277, implicit $mxcsr
+    %279:gr32 = nofpexcept CVTTSS2SIrr killed %278, implicit $mxcsr
+    %280:gr64 = OR64rr %275, killed %276, implicit-def $eflags
+    %281:gr32 = CMOV32rr %273, killed %279, 4, implicit $eflags
+    %282:gr64 = AND64rr %34, %52, implicit-def dead $eflags
+    %283:gr64 = XOR64rr %282, %34, implicit-def dead $eflags
+    %284:gr64 = AND64rr %14, %58, implicit-def dead $eflags
+    %285:fr32 = nofpexcept CVTSI2SSrr %281, implicit $mxcsr
+    %286:fr32 = nofpexcept ADDSSrr %185, killed %285, implicit $mxcsr
+    %287:gr32 = nofpexcept CVTTSS2SIrr killed %286, implicit $mxcsr
+    %288:gr64 = OR64rr %283, killed %284, implicit-def $eflags
+    %289:gr32 = CMOV32rr %281, killed %287, 4, implicit $eflags
+    %290:gr64 = AND64rr %35, %52, implicit-def dead $eflags
+    %291:gr64 = XOR64rr %290, %35, implicit-def dead $eflags
+    %292:gr64 = AND64rr %15, %58, implicit-def dead $eflags
+    %293:fr32 = nofpexcept CVTSI2SSrr %289, implicit $mxcsr
+    %294:fr32 = nofpexcept ADDSSrr %185, killed %293, implicit $mxcsr
+    %295:gr32 = nofpexcept CVTTSS2SIrr killed %294, implicit $mxcsr
+    %296:gr64 = OR64rr %291, killed %292, implicit-def $eflags
+    %297:gr32 = CMOV32rr %289, killed %295, 4, implicit $eflags
+    %298:gr64 = AND64rr %36, %52, implicit-def dead $eflags
+    %299:gr64 = XOR64rr %298, %36, implicit-def dead $eflags
+    %300:gr64 = AND64rr %16, %58, implicit-def dead $eflags
+    %301:fr32 = nofpexcept CVTSI2SSrr %297, implicit $mxcsr
+    %302:fr32 = nofpexcept ADDSSrr %185, killed %301, implicit $mxcsr
+    %303:gr32 = nofpexcept CVTTSS2SIrr killed %302, implicit $mxcsr
+    %304:gr64 = OR64rr %299, killed %300, implicit-def $eflags
+    %305:gr32 = CMOV32rr %297, killed %303, 4, implicit $eflags
+    %306:gr64 = AND64rr %37, %52, implicit-def dead $eflags
+    %307:gr64 = XOR64rr %306, %37, implicit-def dead $eflags
+    %308:gr64 = AND64rr %17, %58, implicit-def dead $eflags
+    %309:fr32 = nofpexcept CVTSI2SSrr %305, implicit $mxcsr
+    %310:fr32 = nofpexcept ADDSSrr %185, killed %309, implicit $mxcsr
+    %311:gr32 = nofpexcept CVTTSS2SIrr killed %310, implicit $mxcsr
+    %312:gr64 = OR64rr %307, killed %308, implicit-def $eflags
+    %313:gr32 = CMOV32rr %305, killed %311, 4, implicit $eflags
+    %314:gr64 = AND64rr %38, %52, implicit-def dead $eflags
+    %315:gr64 = XOR64rr %314, %38, implicit-def dead $eflags
+    %316:gr64 = AND64rr %18, %58, implicit-def dead $eflags
+    %317:fr32 = nofpexcept CVTSI2SSrr %313, implicit $mxcsr
+    %318:fr32 = nofpexcept ADDSSrr %185, killed %317, implicit $mxcsr
+    %319:gr32 = nofpexcept CVTTSS2SIrr killed %318, implicit $mxcsr
+    %320:gr64 = OR64rr %315, killed %316, implicit-def $eflags
+    %321:gr32 = CMOV32rr %313, killed %319, 4, implicit $eflags
+    %322:gr64 = AND64rr %39, %52, implicit-def dead $eflags
+    %323:gr64 = XOR64rr %322, %39, implicit-def dead $eflags
+    %324:gr64 = AND64rr %19, %58, implicit-def dead $eflags
+    %325:fr32 = nofpexcept CVTSI2SSrr %321, implicit $mxcsr
+    %326:fr32 = nofpexcept ADDSSrr %185, killed %325, implicit $mxcsr
+    %327:gr32 = nofpexcept CVTTSS2SIrr killed %326, implicit $mxcsr
+    %328:gr64 = OR64rr %323, killed %324, implicit-def $eflags
+    %329:gr32 = CMOV32rr %321, killed %327, 4, implicit $eflags
+    %330:gr64 = AND64rr %40, %52, implicit-def dead $eflags
+    %331:gr64 = XOR64rr %330, %40, implicit-def dead $eflags
+    %332:gr64 = AND64rr %20, %58, implicit-def dead $eflags
+    %333:fr32 = nofpexcept CVTSI2SSrr %329, implicit $mxcsr
+    %334:fr32 = nofpexcept ADDSSrr %185, killed %333, implicit $mxcsr
+    %335:gr32 = nofpexcept CVTTSS2SIrr killed %334, implicit $mxcsr
+    %336:gr64 = OR64rr %331, killed %332, implicit-def $eflags
+    %337:gr32 = CMOV32rr %329, killed %335, 4, implicit $eflags
+    %338:gr64 = AND64rr %41, %52, implicit-def dead $eflags
+    %339:gr64 = XOR64rr %338, %41, implicit-def dead $eflags
+    %340:gr64 = AND64rr %21, %58, implicit-def dead $eflags
+    %341:fr32 = nofpexcept CVTSI2SSrr %337, implicit $mxcsr
+    %342:fr32 = nofpexcept ADDSSrr %185, killed %341, implicit $mxcsr
+    %343:gr32 = nofpexcept CVTTSS2SIrr killed %342, implicit $mxcsr
+    %344:gr64 = OR64rr %339, killed %340, implicit-def $eflags
+    %345:gr32 = CMOV32rr %337, killed %343, 4, implicit $eflags
+    %346:gr64 = AND64rr %42, %52, implicit-def dead $eflags
+    %347:gr64 = XOR64rr %346, %42, implicit-def dead $eflags
+    %348:gr64 = AND64rr %22, %58, implicit-def dead $eflags
+    %349:fr32 = nofpexcept CVTSI2SSrr %345, implicit $mxcsr
+    %350:fr32 = nofpexcept ADDSSrr %185, killed %349, implicit $mxcsr
+    %351:gr32 = nofpexcept CVTTSS2SIrr killed %350, implicit $mxcsr
+    %352:gr64 = OR64rr %347, killed %348, implicit-def $eflags
+    %45:gr32 = CMOV32rr %345, killed %351, 4, implicit $eflags
+    %353:gr32 = MOV32r0 implicit-def dead $eflags
+    TEST8ri %44, 1, implicit-def $eflags
+    %51:gr8 = COPY %353.sub_8bit
+    JCC_1 %bb.1, 5, implicit $eflags
+    JMP_1 %bb.2
+
+  bb.2.for.end43:
+    $eax = COPY %45
+    RET 0, $eax
+
+...