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Differential D93832

[AArch64] Handle any extend whilst lowering mull
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Authored by dmgreen on Dec 27 2020, 5:19 AM.

Details

Reviewers
RKSimon
efriedma
SjoerdMeijer
NickGuy
Commits
rG78d8a821e23e: [AArch64] Handle any extend whilst lowering mull
Summary

Demanded bits may turn a sext or zext into an anyext if the top bits are not needed. This currently prevents the lowering to instructions like mull, addl and addw. This patch fixes the mull generation by keeping it simple and treating them like zextends.

Diff Detail

Event Timeline

dmgreen created this revision.Dec 27 2020, 5:19 AM
Herald added subscribers: danielkiss, hiraditya, kristof.beyls. · View Herald TranscriptDec 27 2020, 5:19 AM
dmgreen requested review of this revision.Dec 27 2020, 5:19 AM
Herald added a project: Restricted Project. · View Herald TranscriptDec 27 2020, 5:19 AM
dmgreen mentioned this in D93834: [ARM] Handle any extend whilst lowering mull.Dec 27 2020, 5:29 AM
RKSimon accepted this revision.Dec 31 2020, 3:08 AM

LGTM

This revision is now accepted and ready to land.Dec 31 2020, 3:08 AM
Closed by commit rG78d8a821e23e: [AArch64] Handle any extend whilst lowering mull (authored by dmgreen). · Explain WhyJan 6 2021, 2:09 AM
This revision was automatically updated to reflect the committed changes.
dmgreen added a commit: rG78d8a821e23e: [AArch64] Handle any extend whilst lowering mull.

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
4 lines
test/
CodeGen/
AArch64/
167 lines
51 lines

Diff 313777

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 3,324 Lines • ▼ Show 20 Lines for (const SDValue &Elt : N->op_values()) {
} }
return false; return false;
} }
return true; return true;
} }
static SDValue skipExtensionForVectorMULL(SDNode *N, SelectionDAG &DAG) { static SDValue skipExtensionForVectorMULL(SDNode *N, SelectionDAG &DAG) {
if (N->getOpcode() == ISD::SIGN_EXTEND || N->getOpcode() == ISD::ZERO_EXTEND) if (N->getOpcode() == ISD::SIGN_EXTEND ||
N->getOpcode() == ISD::ZERO_EXTEND || N->getOpcode() == ISD::ANY_EXTEND)
return addRequiredExtensionForVectorMULL(N->getOperand(0), DAG, return addRequiredExtensionForVectorMULL(N->getOperand(0), DAG,
N->getOperand(0)->getValueType(0), N->getOperand(0)->getValueType(0),
N->getValueType(0), N->getValueType(0),
N->getOpcode()); N->getOpcode());
assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR"); assert(N->getOpcode() == ISD::BUILD_VECTOR && "expected BUILD_VECTOR");
EVT VT = N->getValueType(0); EVT VT = N->getValueType(0);
SDLoc dl(N); SDLoc dl(N);
Show All 13 Lines
static bool isSignExtended(SDNode *N, SelectionDAG &DAG) { static bool isSignExtended(SDNode *N, SelectionDAG &DAG) {
return N->getOpcode() == ISD::SIGN_EXTEND || return N->getOpcode() == ISD::SIGN_EXTEND ||
isExtendedBUILD_VECTOR(N, DAG, true); isExtendedBUILD_VECTOR(N, DAG, true);
} }
static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) { static bool isZeroExtended(SDNode *N, SelectionDAG &DAG) {
return N->getOpcode() == ISD::ZERO_EXTEND || return N->getOpcode() == ISD::ZERO_EXTEND ||
N->getOpcode() == ISD::ANY_EXTEND ||
isExtendedBUILD_VECTOR(N, DAG, false); isExtendedBUILD_VECTOR(N, DAG, false);
} }
static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) { static bool isAddSubSExt(SDNode *N, SelectionDAG &DAG) {
unsigned Opcode = N->getOpcode(); unsigned Opcode = N->getOpcode();
if (Opcode == ISD::ADD || Opcode == ISD::SUB) { if (Opcode == ISD::ADD || Opcode == ISD::SUB) {
SDNode *N0 = N->getOperand(0).getNode(); SDNode *N0 = N->getOperand(0).getNode();
SDNode *N1 = N->getOperand(1).getNode(); SDNode *N1 = N->getOperand(1).getNode();
▲ Show 20 Lines • Show All 13,573 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/aarch64-smull.ll

Show First 20 Lines • Show All 90 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret <2 x i64> %tmp5 ret <2 x i64> %tmp5
} }
define <8 x i16> @amull_v8i8_v8i16(<8 x i8>* %A, <8 x i8>* %B) nounwind { define <8 x i16> @amull_v8i8_v8i16(<8 x i8>* %A, <8 x i8>* %B) nounwind {
; CHECK-LABEL: amull_v8i8_v8i16: ; CHECK-LABEL: amull_v8i8_v8i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ldr d1, [x1] ; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: ushll v0.8h, v0.8b, #0 ; CHECK-NEXT: umull v0.8h, v0.8b, v1.8b
; CHECK-NEXT: ushll v1.8h, v1.8b, #0
; CHECK-NEXT: mul v0.8h, v0.8h, v1.8h
; CHECK-NEXT: bic v0.8h, #255, lsl #8 ; CHECK-NEXT: bic v0.8h, #255, lsl #8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp1 = load <8 x i8>, <8 x i8>* %A %tmp1 = load <8 x i8>, <8 x i8>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B %tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = zext <8 x i8> %tmp1 to <8 x i16> %tmp3 = zext <8 x i8> %tmp1 to <8 x i16>
%tmp4 = zext <8 x i8> %tmp2 to <8 x i16> %tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
%tmp5 = mul <8 x i16> %tmp3, %tmp4 %tmp5 = mul <8 x i16> %tmp3, %tmp4
%and = and <8 x i16> %tmp5, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> %and = and <8 x i16> %tmp5, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
ret <8 x i16> %and ret <8 x i16> %and
} }
define <4 x i32> @amull_v4i16_v4i32(<4 x i16>* %A, <4 x i16>* %B) nounwind { define <4 x i32> @amull_v4i16_v4i32(<4 x i16>* %A, <4 x i16>* %B) nounwind {
; CHECK-LABEL: amull_v4i16_v4i32: ; CHECK-LABEL: amull_v4i16_v4i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ldr d1, [x1] ; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: ushll v0.4s, v0.4h, #0 ; CHECK-NEXT: umull v0.4s, v0.4h, v1.4h
; CHECK-NEXT: ushll v1.4s, v1.4h, #0
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: movi v1.2d, #0x00ffff0000ffff ; CHECK-NEXT: movi v1.2d, #0x00ffff0000ffff
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp1 = load <4 x i16>, <4 x i16>* %A %tmp1 = load <4 x i16>, <4 x i16>* %A
%tmp2 = load <4 x i16>, <4 x i16>* %B %tmp2 = load <4 x i16>, <4 x i16>* %B
%tmp3 = zext <4 x i16> %tmp1 to <4 x i32> %tmp3 = zext <4 x i16> %tmp1 to <4 x i32>
%tmp4 = zext <4 x i16> %tmp2 to <4 x i32> %tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
%tmp5 = mul <4 x i32> %tmp3, %tmp4 %tmp5 = mul <4 x i32> %tmp3, %tmp4
%and = and <4 x i32> %tmp5, <i32 65535, i32 65535, i32 65535, i32 65535> %and = and <4 x i32> %tmp5, <i32 65535, i32 65535, i32 65535, i32 65535>
ret <4 x i32> %and ret <4 x i32> %and
} }
define <2 x i64> @amull_v2i32_v2i64(<2 x i32>* %A, <2 x i32>* %B) nounwind { define <2 x i64> @amull_v2i32_v2i64(<2 x i32>* %A, <2 x i32>* %B) nounwind {
; CHECK-LABEL: amull_v2i32_v2i64: ; CHECK-LABEL: amull_v2i32_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x0] ; CHECK-NEXT: ldr d0, [x0]
; CHECK-NEXT: ldr d1, [x1] ; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: ushll v0.2d, v0.2s, #0 ; CHECK-NEXT: umull v0.2d, v0.2s, v1.2s
; CHECK-NEXT: ushll v1.2d, v1.2s, #0
; CHECK-NEXT: fmov x10, d1
; CHECK-NEXT: fmov x11, d0
; CHECK-NEXT: mov x8, v1.d[1]
; CHECK-NEXT: mov x9, v0.d[1]
; CHECK-NEXT: mul x10, x11, x10
; CHECK-NEXT: mul x8, x9, x8
; CHECK-NEXT: fmov d0, x10
; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: movi v1.2d, #0x000000ffffffff ; CHECK-NEXT: movi v1.2d, #0x000000ffffffff
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp1 = load <2 x i32>, <2 x i32>* %A %tmp1 = load <2 x i32>, <2 x i32>* %A
%tmp2 = load <2 x i32>, <2 x i32>* %B %tmp2 = load <2 x i32>, <2 x i32>* %B
%tmp3 = zext <2 x i32> %tmp1 to <2 x i64> %tmp3 = zext <2 x i32> %tmp1 to <2 x i64>
%tmp4 = zext <2 x i32> %tmp2 to <2 x i64> %tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
%tmp5 = mul <2 x i64> %tmp3, %tmp4 %tmp5 = mul <2 x i64> %tmp3, %tmp4
▲ Show 20 Lines • Show All 107 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%tmp6 = mul <2 x i64> %tmp4, %tmp5 %tmp6 = mul <2 x i64> %tmp4, %tmp5
%tmp7 = add <2 x i64> %tmp1, %tmp6 %tmp7 = add <2 x i64> %tmp1, %tmp6
ret <2 x i64> %tmp7 ret <2 x i64> %tmp7
} }
define <8 x i16> @amlal_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { define <8 x i16> @amlal_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
; CHECK-LABEL: amlal_v8i8_v8i16: ; CHECK-LABEL: amlal_v8i8_v8i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ldr d1, [x1] ; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: ldr d2, [x2] ; CHECK-NEXT: ldr d2, [x2]
; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: umlal v0.8h, v1.8b, v2.8b
; CHECK-NEXT: ushll v1.8h, v1.8b, #0
; CHECK-NEXT: ushll v2.8h, v2.8b, #0
; CHECK-NEXT: mla v0.8h, v1.8h, v2.8h
; CHECK-NEXT: bic v0.8h, #255, lsl #8 ; CHECK-NEXT: bic v0.8h, #255, lsl #8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp1 = load <8 x i16>, <8 x i16>* %A %tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B %tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = load <8 x i8>, <8 x i8>* %C %tmp3 = load <8 x i8>, <8 x i8>* %C
%tmp4 = zext <8 x i8> %tmp2 to <8 x i16> %tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
%tmp5 = zext <8 x i8> %tmp3 to <8 x i16> %tmp5 = zext <8 x i8> %tmp3 to <8 x i16>
%tmp6 = mul <8 x i16> %tmp4, %tmp5 %tmp6 = mul <8 x i16> %tmp4, %tmp5
%tmp7 = add <8 x i16> %tmp1, %tmp6 %tmp7 = add <8 x i16> %tmp1, %tmp6
%and = and <8 x i16> %tmp7, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> %and = and <8 x i16> %tmp7, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
ret <8 x i16> %and ret <8 x i16> %and
} }
define <4 x i32> @amlal_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { define <4 x i32> @amlal_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
; CHECK-LABEL: amlal_v4i16_v4i32: ; CHECK-LABEL: amlal_v4i16_v4i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x1] ; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ldr d1, [x2] ; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: ldr q2, [x0] ; CHECK-NEXT: ldr d2, [x2]
; CHECK-NEXT: ushll v0.4s, v0.4h, #0 ; CHECK-NEXT: umlal v0.4s, v1.4h, v2.4h
; CHECK-NEXT: ushll v1.4s, v1.4h, #0 ; CHECK-NEXT: movi v1.2d, #0x00ffff0000ffff
; CHECK-NEXT: mla v2.4s, v0.4s, v1.4s ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: movi v0.2d, #0x00ffff0000ffff
; CHECK-NEXT: and v0.16b, v2.16b, v0.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp1 = load <4 x i32>, <4 x i32>* %A %tmp1 = load <4 x i32>, <4 x i32>* %A
%tmp2 = load <4 x i16>, <4 x i16>* %B %tmp2 = load <4 x i16>, <4 x i16>* %B
%tmp3 = load <4 x i16>, <4 x i16>* %C %tmp3 = load <4 x i16>, <4 x i16>* %C
%tmp4 = zext <4 x i16> %tmp2 to <4 x i32> %tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
%tmp5 = zext <4 x i16> %tmp3 to <4 x i32> %tmp5 = zext <4 x i16> %tmp3 to <4 x i32>
%tmp6 = mul <4 x i32> %tmp4, %tmp5 %tmp6 = mul <4 x i32> %tmp4, %tmp5
%tmp7 = add <4 x i32> %tmp1, %tmp6 %tmp7 = add <4 x i32> %tmp1, %tmp6
%and = and <4 x i32> %tmp7, <i32 65535, i32 65535, i32 65535, i32 65535> %and = and <4 x i32> %tmp7, <i32 65535, i32 65535, i32 65535, i32 65535>
ret <4 x i32> %and ret <4 x i32> %and
} }
define <2 x i64> @amlal_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { define <2 x i64> @amlal_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
; CHECK-LABEL: amlal_v2i32_v2i64: ; CHECK-LABEL: amlal_v2i32_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x1] ; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ldr d1, [x2] ; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: ldr q2, [x0] ; CHECK-NEXT: ldr d2, [x2]
; CHECK-NEXT: ushll v0.2d, v0.2s, #0 ; CHECK-NEXT: umlal v0.2d, v1.2s, v2.2s
; CHECK-NEXT: ushll v1.2d, v1.2s, #0
; CHECK-NEXT: fmov x10, d1
; CHECK-NEXT: fmov x11, d0
; CHECK-NEXT: mov x8, v1.d[1]
; CHECK-NEXT: mov x9, v0.d[1]
; CHECK-NEXT: mul x10, x11, x10
; CHECK-NEXT: mul x8, x9, x8
; CHECK-NEXT: fmov d0, x10
; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: add v0.2d, v2.2d, v0.2d
; CHECK-NEXT: movi v1.2d, #0x000000ffffffff ; CHECK-NEXT: movi v1.2d, #0x000000ffffffff
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp1 = load <2 x i64>, <2 x i64>* %A %tmp1 = load <2 x i64>, <2 x i64>* %A
%tmp2 = load <2 x i32>, <2 x i32>* %B %tmp2 = load <2 x i32>, <2 x i32>* %B
%tmp3 = load <2 x i32>, <2 x i32>* %C %tmp3 = load <2 x i32>, <2 x i32>* %C
%tmp4 = zext <2 x i32> %tmp2 to <2 x i64> %tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
%tmp5 = zext <2 x i32> %tmp3 to <2 x i64> %tmp5 = zext <2 x i32> %tmp3 to <2 x i64>
▲ Show 20 Lines • Show All 109 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%tmp6 = mul <2 x i64> %tmp4, %tmp5 %tmp6 = mul <2 x i64> %tmp4, %tmp5
%tmp7 = sub <2 x i64> %tmp1, %tmp6 %tmp7 = sub <2 x i64> %tmp1, %tmp6
ret <2 x i64> %tmp7 ret <2 x i64> %tmp7
} }
define <8 x i16> @amlsl_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind { define <8 x i16> @amlsl_v8i8_v8i16(<8 x i16>* %A, <8 x i8>* %B, <8 x i8>* %C) nounwind {
; CHECK-LABEL: amlsl_v8i8_v8i16: ; CHECK-LABEL: amlsl_v8i8_v8i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ldr d1, [x1] ; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: ldr d2, [x2] ; CHECK-NEXT: ldr d2, [x2]
; CHECK-NEXT: ldr q0, [x0] ; CHECK-NEXT: umlsl v0.8h, v1.8b, v2.8b
; CHECK-NEXT: ushll v1.8h, v1.8b, #0
; CHECK-NEXT: ushll v2.8h, v2.8b, #0
; CHECK-NEXT: mls v0.8h, v1.8h, v2.8h
; CHECK-NEXT: bic v0.8h, #255, lsl #8 ; CHECK-NEXT: bic v0.8h, #255, lsl #8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp1 = load <8 x i16>, <8 x i16>* %A %tmp1 = load <8 x i16>, <8 x i16>* %A
%tmp2 = load <8 x i8>, <8 x i8>* %B %tmp2 = load <8 x i8>, <8 x i8>* %B
%tmp3 = load <8 x i8>, <8 x i8>* %C %tmp3 = load <8 x i8>, <8 x i8>* %C
%tmp4 = zext <8 x i8> %tmp2 to <8 x i16> %tmp4 = zext <8 x i8> %tmp2 to <8 x i16>
%tmp5 = zext <8 x i8> %tmp3 to <8 x i16> %tmp5 = zext <8 x i8> %tmp3 to <8 x i16>
%tmp6 = mul <8 x i16> %tmp4, %tmp5 %tmp6 = mul <8 x i16> %tmp4, %tmp5
%tmp7 = sub <8 x i16> %tmp1, %tmp6 %tmp7 = sub <8 x i16> %tmp1, %tmp6
%and = and <8 x i16> %tmp7, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> %and = and <8 x i16> %tmp7, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
ret <8 x i16> %and ret <8 x i16> %and
} }
define <4 x i32> @amlsl_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind { define <4 x i32> @amlsl_v4i16_v4i32(<4 x i32>* %A, <4 x i16>* %B, <4 x i16>* %C) nounwind {
; CHECK-LABEL: amlsl_v4i16_v4i32: ; CHECK-LABEL: amlsl_v4i16_v4i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x1] ; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ldr d1, [x2] ; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: ldr q2, [x0] ; CHECK-NEXT: ldr d2, [x2]
; CHECK-NEXT: ushll v0.4s, v0.4h, #0 ; CHECK-NEXT: umlsl v0.4s, v1.4h, v2.4h
; CHECK-NEXT: ushll v1.4s, v1.4h, #0 ; CHECK-NEXT: movi v1.2d, #0x00ffff0000ffff
; CHECK-NEXT: mls v2.4s, v0.4s, v1.4s ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: movi v0.2d, #0x00ffff0000ffff
; CHECK-NEXT: and v0.16b, v2.16b, v0.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp1 = load <4 x i32>, <4 x i32>* %A %tmp1 = load <4 x i32>, <4 x i32>* %A
%tmp2 = load <4 x i16>, <4 x i16>* %B %tmp2 = load <4 x i16>, <4 x i16>* %B
%tmp3 = load <4 x i16>, <4 x i16>* %C %tmp3 = load <4 x i16>, <4 x i16>* %C
%tmp4 = zext <4 x i16> %tmp2 to <4 x i32> %tmp4 = zext <4 x i16> %tmp2 to <4 x i32>
%tmp5 = zext <4 x i16> %tmp3 to <4 x i32> %tmp5 = zext <4 x i16> %tmp3 to <4 x i32>
%tmp6 = mul <4 x i32> %tmp4, %tmp5 %tmp6 = mul <4 x i32> %tmp4, %tmp5
%tmp7 = sub <4 x i32> %tmp1, %tmp6 %tmp7 = sub <4 x i32> %tmp1, %tmp6
%and = and <4 x i32> %tmp7, <i32 65535, i32 65535, i32 65535, i32 65535> %and = and <4 x i32> %tmp7, <i32 65535, i32 65535, i32 65535, i32 65535>
ret <4 x i32> %and ret <4 x i32> %and
} }
define <2 x i64> @amlsl_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind { define <2 x i64> @amlsl_v2i32_v2i64(<2 x i64>* %A, <2 x i32>* %B, <2 x i32>* %C) nounwind {
; CHECK-LABEL: amlsl_v2i32_v2i64: ; CHECK-LABEL: amlsl_v2i32_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ldr d0, [x1] ; CHECK-NEXT: ldr q0, [x0]
; CHECK-NEXT: ldr d1, [x2] ; CHECK-NEXT: ldr d1, [x1]
; CHECK-NEXT: ldr q2, [x0] ; CHECK-NEXT: ldr d2, [x2]
; CHECK-NEXT: ushll v0.2d, v0.2s, #0 ; CHECK-NEXT: umlsl v0.2d, v1.2s, v2.2s
; CHECK-NEXT: ushll v1.2d, v1.2s, #0
; CHECK-NEXT: fmov x10, d1
; CHECK-NEXT: fmov x11, d0
; CHECK-NEXT: mov x8, v1.d[1]
; CHECK-NEXT: mov x9, v0.d[1]
; CHECK-NEXT: mul x10, x11, x10
; CHECK-NEXT: mul x8, x9, x8
; CHECK-NEXT: fmov d0, x10
; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: sub v0.2d, v2.2d, v0.2d
; CHECK-NEXT: movi v1.2d, #0x000000ffffffff ; CHECK-NEXT: movi v1.2d, #0x000000ffffffff
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp1 = load <2 x i64>, <2 x i64>* %A %tmp1 = load <2 x i64>, <2 x i64>* %A
%tmp2 = load <2 x i32>, <2 x i32>* %B %tmp2 = load <2 x i32>, <2 x i32>* %B
%tmp3 = load <2 x i32>, <2 x i32>* %C %tmp3 = load <2 x i32>, <2 x i32>* %C
%tmp4 = zext <2 x i32> %tmp2 to <2 x i64> %tmp4 = zext <2 x i32> %tmp2 to <2 x i64>
%tmp5 = zext <2 x i32> %tmp3 to <2 x i64> %tmp5 = zext <2 x i32> %tmp3 to <2 x i64>
▲ Show 20 Lines • Show All 99 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%tmp3 = zext <2 x i32> %arg to <2 x i64> %tmp3 = zext <2 x i32> %arg to <2 x i64>
%tmp4 = mul <2 x i64> %tmp3, <i64 1234, i64 1234> %tmp4 = mul <2 x i64> %tmp3, <i64 1234, i64 1234>
ret <2 x i64> %tmp4 ret <2 x i64> %tmp4
} }
define <8 x i16> @amull_extvec_v8i8_v8i16(<8 x i8> %arg) nounwind { define <8 x i16> @amull_extvec_v8i8_v8i16(<8 x i8> %arg) nounwind {
; CHECK-LABEL: amull_extvec_v8i8_v8i16: ; CHECK-LABEL: amull_extvec_v8i8_v8i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ushll v0.8h, v0.8b, #0 ; CHECK-NEXT: movi v1.8b, #12
; CHECK-NEXT: movi v1.8h, #12 ; CHECK-NEXT: umull v0.8h, v0.8b, v1.8b
; CHECK-NEXT: mul v0.8h, v0.8h, v1.8h
; CHECK-NEXT: bic v0.8h, #255, lsl #8 ; CHECK-NEXT: bic v0.8h, #255, lsl #8
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = zext <8 x i8> %arg to <8 x i16> %tmp3 = zext <8 x i8> %arg to <8 x i16>
%tmp4 = mul <8 x i16> %tmp3, <i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12> %tmp4 = mul <8 x i16> %tmp3, <i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12, i16 12>
%and = and <8 x i16> %tmp4, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> %and = and <8 x i16> %tmp4, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
ret <8 x i16> %and ret <8 x i16> %and
} }
define <4 x i32> @amull_extvec_v4i16_v4i32(<4 x i16> %arg) nounwind { define <4 x i32> @amull_extvec_v4i16_v4i32(<4 x i16> %arg) nounwind {
; CHECK-LABEL: amull_extvec_v4i16_v4i32: ; CHECK-LABEL: amull_extvec_v4i16_v4i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: mov w8, #1234 ; CHECK-NEXT: mov w8, #1234
; CHECK-NEXT: ushll v0.4s, v0.4h, #0 ; CHECK-NEXT: dup v1.4h, w8
; CHECK-NEXT: dup v1.4s, w8 ; CHECK-NEXT: umull v0.4s, v0.4h, v1.4h
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: movi v1.2d, #0x00ffff0000ffff ; CHECK-NEXT: movi v1.2d, #0x00ffff0000ffff
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = zext <4 x i16> %arg to <4 x i32> %tmp3 = zext <4 x i16> %arg to <4 x i32>
%tmp4 = mul <4 x i32> %tmp3, <i32 1234, i32 1234, i32 1234, i32 1234> %tmp4 = mul <4 x i32> %tmp3, <i32 1234, i32 1234, i32 1234, i32 1234>
%and = and <4 x i32> %tmp4, <i32 65535, i32 65535, i32 65535, i32 65535> %and = and <4 x i32> %tmp4, <i32 65535, i32 65535, i32 65535, i32 65535>
ret <4 x i32> %and ret <4 x i32> %and
} }
define <2 x i64> @amull_extvec_v2i32_v2i64(<2 x i32> %arg) nounwind { define <2 x i64> @amull_extvec_v2i32_v2i64(<2 x i32> %arg) nounwind {
; CHECK-LABEL: amull_extvec_v2i32_v2i64: ; CHECK-LABEL: amull_extvec_v2i32_v2i64:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ushll v0.2d, v0.2s, #0
; CHECK-NEXT: mov w8, #1234 ; CHECK-NEXT: mov w8, #1234
; CHECK-NEXT: fmov x10, d0 ; CHECK-NEXT: dup v1.2s, w8
; CHECK-NEXT: mov x9, v0.d[1] ; CHECK-NEXT: umull v0.2d, v0.2s, v1.2s
; CHECK-NEXT: mul x10, x10, x8
; CHECK-NEXT: mul x8, x9, x8
; CHECK-NEXT: fmov d0, x10
; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: movi v1.2d, #0x000000ffffffff ; CHECK-NEXT: movi v1.2d, #0x000000ffffffff
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%tmp3 = zext <2 x i32> %arg to <2 x i64> %tmp3 = zext <2 x i32> %arg to <2 x i64>
%tmp4 = mul <2 x i64> %tmp3, <i64 1234, i64 1234> %tmp4 = mul <2 x i64> %tmp3, <i64 1234, i64 1234>
%and = and <2 x i64> %tmp4, <i64 4294967295, i64 4294967295> %and = and <2 x i64> %tmp4, <i64 4294967295, i64 4294967295>
ret <2 x i64> %and ret <2 x i64> %and
} }
▲ Show 20 Lines • Show All 120 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
%arg2_ext = sext <4 x i32> %arg2 to <4 x i64> %arg2_ext = sext <4 x i32> %arg2 to <4 x i64>
%mul = mul <4 x i64> %arg1_ext, %arg2_ext %mul = mul <4 x i64> %arg1_ext, %arg2_ext
ret <4 x i64> %mul ret <4 x i64> %mul
} }
define <16 x i16> @amull2_i8(<16 x i8> %arg1, <16 x i8> %arg2) { define <16 x i16> @amull2_i8(<16 x i8> %arg1, <16 x i8> %arg2) {
; CHECK-LABEL: amull2_i8: ; CHECK-LABEL: amull2_i8:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ushll2 v2.8h, v0.16b, #0 ; CHECK-NEXT: umull v2.8h, v0.8b, v1.8b
; CHECK-NEXT: ushll v0.8h, v0.8b, #0 ; CHECK-NEXT: umull2 v1.8h, v0.16b, v1.16b
; CHECK-NEXT: ushll2 v3.8h, v1.16b, #0 ; CHECK-NEXT: bic v2.8h, #255, lsl #8
; CHECK-NEXT: ushll v1.8h, v1.8b, #0
; CHECK-NEXT: mul v0.8h, v0.8h, v1.8h
; CHECK-NEXT: mul v1.8h, v2.8h, v3.8h
; CHECK-NEXT: bic v1.8h, #255, lsl #8 ; CHECK-NEXT: bic v1.8h, #255, lsl #8
; CHECK-NEXT: bic v0.8h, #255, lsl #8 ; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%arg1_ext = zext <16 x i8> %arg1 to <16 x i16> %arg1_ext = zext <16 x i8> %arg1 to <16 x i16>
%arg2_ext = zext <16 x i8> %arg2 to <16 x i16> %arg2_ext = zext <16 x i8> %arg2 to <16 x i16>
%mul = mul <16 x i16> %arg1_ext, %arg2_ext %mul = mul <16 x i16> %arg1_ext, %arg2_ext
%and = and <16 x i16> %mul, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255> %and = and <16 x i16> %mul, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
ret <16 x i16> %and ret <16 x i16> %and
} }
define <8 x i32> @amull2_i16(<8 x i16> %arg1, <8 x i16> %arg2) { define <8 x i32> @amull2_i16(<8 x i16> %arg1, <8 x i16> %arg2) {
; CHECK-LABEL: amull2_i16: ; CHECK-LABEL: amull2_i16:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ushll2 v2.4s, v0.8h, #0 ; CHECK-NEXT: umull v2.4s, v0.4h, v1.4h
; CHECK-NEXT: ushll v0.4s, v0.4h, #0 ; CHECK-NEXT: umull2 v0.4s, v0.8h, v1.8h
; CHECK-NEXT: ushll2 v3.4s, v1.8h, #0 ; CHECK-NEXT: movi v3.2d, #0x00ffff0000ffff
; CHECK-NEXT: ushll v1.4s, v1.4h, #0 ; CHECK-NEXT: and v1.16b, v0.16b, v3.16b
; CHECK-NEXT: movi v4.2d, #0x00ffff0000ffff ; CHECK-NEXT: and v0.16b, v2.16b, v3.16b
; CHECK-NEXT: mul v0.4s, v0.4s, v1.4s
; CHECK-NEXT: mul v1.4s, v2.4s, v3.4s
; CHECK-NEXT: and v1.16b, v1.16b, v4.16b
; CHECK-NEXT: and v0.16b, v0.16b, v4.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%arg1_ext = zext <8 x i16> %arg1 to <8 x i32> %arg1_ext = zext <8 x i16> %arg1 to <8 x i32>
%arg2_ext = zext <8 x i16> %arg2 to <8 x i32> %arg2_ext = zext <8 x i16> %arg2 to <8 x i32>
%mul = mul <8 x i32> %arg1_ext, %arg2_ext %mul = mul <8 x i32> %arg1_ext, %arg2_ext
%and = and <8 x i32> %mul, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535> %and = and <8 x i32> %mul, <i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535, i32 65535>
ret <8 x i32> %and ret <8 x i32> %and
} }
define <4 x i64> @amull2_i32(<4 x i32> %arg1, <4 x i32> %arg2) { define <4 x i64> @amull2_i32(<4 x i32> %arg1, <4 x i32> %arg2) {
; CHECK-LABEL: amull2_i32: ; CHECK-LABEL: amull2_i32:
; CHECK: // %bb.0: ; CHECK: // %bb.0:
; CHECK-NEXT: ushll2 v2.2d, v0.4s, #0 ; CHECK-NEXT: umull v2.2d, v0.2s, v1.2s
; CHECK-NEXT: ushll v0.2d, v0.2s, #0 ; CHECK-NEXT: umull2 v0.2d, v0.4s, v1.4s
; CHECK-NEXT: ushll2 v3.2d, v1.4s, #0 ; CHECK-NEXT: movi v3.2d, #0x000000ffffffff
; CHECK-NEXT: ushll v1.2d, v1.2s, #0 ; CHECK-NEXT: and v1.16b, v0.16b, v3.16b
; CHECK-NEXT: fmov x10, d1 ; CHECK-NEXT: and v0.16b, v2.16b, v3.16b
; CHECK-NEXT: fmov x11, d0
; CHECK-NEXT: fmov x13, d3
; CHECK-NEXT: fmov x14, d2
; CHECK-NEXT: mov x8, v1.d[1]
; CHECK-NEXT: mov x9, v0.d[1]
; CHECK-NEXT: mul x10, x11, x10
; CHECK-NEXT: mov x11, v3.d[1]
; CHECK-NEXT: mov x12, v2.d[1]
; CHECK-NEXT: mul x13, x14, x13
; CHECK-NEXT: mul x8, x9, x8
; CHECK-NEXT: fmov d0, x10
; CHECK-NEXT: mul x9, x12, x11
; CHECK-NEXT: fmov d1, x13
; CHECK-NEXT: movi v2.2d, #0x000000ffffffff
; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: mov v1.d[1], x9
; CHECK-NEXT: and v1.16b, v1.16b, v2.16b
; CHECK-NEXT: and v0.16b, v0.16b, v2.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%arg1_ext = zext <4 x i32> %arg1 to <4 x i64> %arg1_ext = zext <4 x i32> %arg1 to <4 x i64>
%arg2_ext = zext <4 x i32> %arg2 to <4 x i64> %arg2_ext = zext <4 x i32> %arg2 to <4 x i64>
%mul = mul <4 x i64> %arg1_ext, %arg2_ext %mul = mul <4 x i64> %arg1_ext, %arg2_ext
%and = and <4 x i64> %mul, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295> %and = and <4 x i64> %mul, <i64 4294967295, i64 4294967295, i64 4294967295, i64 4294967295>
ret <4 x i64> %and ret <4 x i64> %and
} }

llvm/test/CodeGen/AArch64/lowerMUL-newload.ll

Show All 15 Linesentry:
%v4 = add <4 x i32> %v3, %v2 %v4 = add <4 x i32> %v3, %v2
%v5 = trunc <4 x i32> %v4 to <4 x i16> %v5 = trunc <4 x i32> %v4 to <4 x i16>
ret <4 x i16> %v5 ret <4 x i16> %v5
} }
define <4 x i32> @mlai16_and(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2) { define <4 x i32> @mlai16_and(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2) {
; CHECK-LABEL: mlai16_and: ; CHECK-LABEL: mlai16_and:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ushll v0.4s, v0.4h, #0
; CHECK-NEXT: ushll v1.4s, v1.4h, #0
; CHECK-NEXT: ushll v2.4s, v2.4h, #0 ; CHECK-NEXT: ushll v2.4s, v2.4h, #0
; CHECK-NEXT: mla v2.4s, v1.4s, v0.4s ; CHECK-NEXT: umlal v2.4s, v1.4h, v0.4h
; CHECK-NEXT: movi v0.2d, #0x00ffff0000ffff ; CHECK-NEXT: movi v0.2d, #0x00ffff0000ffff
; CHECK-NEXT: and v0.16b, v2.16b, v0.16b ; CHECK-NEXT: and v0.16b, v2.16b, v0.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%v0 = sext <4 x i16> %vec0 to <4 x i32> %v0 = sext <4 x i16> %vec0 to <4 x i32>
%v1 = sext <4 x i16> %vec1 to <4 x i32> %v1 = sext <4 x i16> %vec1 to <4 x i32>
%v2 = sext <4 x i16> %vec2 to <4 x i32> %v2 = sext <4 x i16> %vec2 to <4 x i32>
%v3 = mul <4 x i32> %v1, %v0 %v3 = mul <4 x i32> %v1, %v0
▲ Show 20 Lines • Show All 50 Lines • ▼ Show 20 Linesentry:
%v4 = mul <4 x i32> %v3, %v2 %v4 = mul <4 x i32> %v3, %v2
%v5 = trunc <4 x i32> %v4 to <4 x i16> %v5 = trunc <4 x i32> %v4 to <4 x i16>
ret <4 x i16> %v5 ret <4 x i16> %v5
} }
define <4 x i32> @addmuli16_and(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2) { define <4 x i32> @addmuli16_and(<4 x i16> %vec0, <4 x i16> %vec1, <4 x i16> %vec2) {
; CHECK-LABEL: addmuli16_and: ; CHECK-LABEL: addmuli16_and:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ushll v0.4s, v0.4h, #0 ; CHECK-NEXT: umull v1.4s, v1.4h, v2.4h
; CHECK-NEXT: ushll v1.4s, v1.4h, #0 ; CHECK-NEXT: umlal v1.4s, v0.4h, v2.4h
; CHECK-NEXT: ushll v2.4s, v2.4h, #0 ; CHECK-NEXT: movi v0.2d, #0x00ffff0000ffff
; CHECK-NEXT: add v0.4s, v1.4s, v0.4s ; CHECK-NEXT: and v0.16b, v1.16b, v0.16b
; CHECK-NEXT: mul v0.4s, v0.4s, v2.4s
; CHECK-NEXT: movi v1.2d, #0x00ffff0000ffff
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%v0 = sext <4 x i16> %vec0 to <4 x i32> %v0 = sext <4 x i16> %vec0 to <4 x i32>
%v1 = sext <4 x i16> %vec1 to <4 x i32> %v1 = sext <4 x i16> %vec1 to <4 x i32>
%v2 = sext <4 x i16> %vec2 to <4 x i32> %v2 = sext <4 x i16> %vec2 to <4 x i32>
%v3 = add <4 x i32> %v1, %v0 %v3 = add <4 x i32> %v1, %v0
%v4 = mul <4 x i32> %v3, %v2 %v4 = mul <4 x i32> %v3, %v2
%v5 = and <4 x i32> %v4, <i32 65535, i32 65535, i32 65535, i32 65535> %v5 = and <4 x i32> %v4, <i32 65535, i32 65535, i32 65535, i32 65535>
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Linesentry:
%v4 = add <2 x i64> %v3, %v2 %v4 = add <2 x i64> %v3, %v2
%v5 = trunc <2 x i64> %v4 to <2 x i32> %v5 = trunc <2 x i64> %v4 to <2 x i32>
ret <2 x i32> %v5 ret <2 x i32> %v5
} }
define <2 x i64> @mlai32_and(<2 x i32> %vec0, <2 x i32> %vec1, <2 x i32> %vec2) { define <2 x i64> @mlai32_and(<2 x i32> %vec0, <2 x i32> %vec1, <2 x i32> %vec2) {
; CHECK-LABEL: mlai32_and: ; CHECK-LABEL: mlai32_and:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ushll v0.2d, v0.2s, #0 ; CHECK-NEXT: ushll v2.2d, v2.2s, #0
; CHECK-NEXT: ushll v1.2d, v1.2s, #0 ; CHECK-NEXT: umlal v2.2d, v1.2s, v0.2s
; CHECK-NEXT: fmov x10, d0 ; CHECK-NEXT: movi v0.2d, #0x000000ffffffff
; CHECK-NEXT: fmov x11, d1 ; CHECK-NEXT: and v0.16b, v2.16b, v0.16b
; CHECK-NEXT: mov x8, v0.d[1]
; CHECK-NEXT: mov x9, v1.d[1]
; CHECK-NEXT: mul x10, x11, x10
; CHECK-NEXT: mul x8, x9, x8
; CHECK-NEXT: fmov d1, x10
; CHECK-NEXT: ushll v0.2d, v2.2s, #0
; CHECK-NEXT: mov v1.d[1], x8
; CHECK-NEXT: add v0.2d, v1.2d, v0.2d
; CHECK-NEXT: movi v1.2d, #0x000000ffffffff
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%v0 = sext <2 x i32> %vec0 to <2 x i64> %v0 = sext <2 x i32> %vec0 to <2 x i64>
%v1 = sext <2 x i32> %vec1 to <2 x i64> %v1 = sext <2 x i32> %vec1 to <2 x i64>
%v2 = sext <2 x i32> %vec2 to <2 x i64> %v2 = sext <2 x i32> %vec2 to <2 x i64>
%v3 = mul <2 x i64> %v1, %v0 %v3 = mul <2 x i64> %v1, %v0
%v4 = add <2 x i64> %v3, %v2 %v4 = add <2 x i64> %v3, %v2
%v5 = and <2 x i64> %v4, <i64 4294967295, i64 4294967295> %v5 = and <2 x i64> %v4, <i64 4294967295, i64 4294967295>
▲ Show 20 Lines • Show All 48 Lines • ▼ Show 20 Linesentry:
%v4 = mul <2 x i64> %v3, %v2 %v4 = mul <2 x i64> %v3, %v2
%v5 = trunc <2 x i64> %v4 to <2 x i32> %v5 = trunc <2 x i64> %v4 to <2 x i32>
ret <2 x i32> %v5 ret <2 x i32> %v5
} }
define <2 x i64> @addmuli32_and(<2 x i32> %vec0, <2 x i32> %vec1, <2 x i32> %vec2) { define <2 x i64> @addmuli32_and(<2 x i32> %vec0, <2 x i32> %vec1, <2 x i32> %vec2) {
; CHECK-LABEL: addmuli32_and: ; CHECK-LABEL: addmuli32_and:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: ushll v0.2d, v0.2s, #0 ; CHECK-NEXT: umull v1.2d, v1.2s, v2.2s
; CHECK-NEXT: ushll v1.2d, v1.2s, #0 ; CHECK-NEXT: umlal v1.2d, v0.2s, v2.2s
; CHECK-NEXT: ushll v2.2d, v2.2s, #0 ; CHECK-NEXT: movi v0.2d, #0x000000ffffffff
; CHECK-NEXT: add v0.2d, v1.2d, v0.2d ; CHECK-NEXT: and v0.16b, v1.16b, v0.16b
; CHECK-NEXT: fmov x9, d2
; CHECK-NEXT: fmov x11, d0
; CHECK-NEXT: mov x8, v2.d[1]
; CHECK-NEXT: mov x10, v0.d[1]
; CHECK-NEXT: mul x9, x11, x9
; CHECK-NEXT: mul x8, x10, x8
; CHECK-NEXT: fmov d0, x9
; CHECK-NEXT: mov v0.d[1], x8
; CHECK-NEXT: movi v1.2d, #0x000000ffffffff
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%v0 = sext <2 x i32> %vec0 to <2 x i64> %v0 = sext <2 x i32> %vec0 to <2 x i64>
%v1 = sext <2 x i32> %vec1 to <2 x i64> %v1 = sext <2 x i32> %vec1 to <2 x i64>
%v2 = sext <2 x i32> %vec2 to <2 x i64> %v2 = sext <2 x i32> %vec2 to <2 x i64>
%v3 = add <2 x i64> %v1, %v0 %v3 = add <2 x i64> %v1, %v0
%v4 = mul <2 x i64> %v3, %v2 %v4 = mul <2 x i64> %v3, %v2
%v5 = and <2 x i64> %v4, <i64 4294967295, i64 4294967295> %v5 = and <2 x i64> %v4, <i64 4294967295, i64 4294967295>
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