[RISCV] Update V instructions constraints to conform to v1.0

[HsiangKai]

Summary

Upgrade RISC-V V extension to v1.0-08a0b46.
Update instruction constraints to conform to v1.0.

[craig.topper]

llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h

96

Were we missing test coverage for the constraint removed here?

99

Same here?

99

Why wouldn't VMConstraint apply to SlideUp and Vrgather? I thought that was a general rule.

[craig.topper]

llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h

93

These enum values aren't used. Just the ones in X86InstrFormats.td are used and now they aren't in sync.

[HsiangKai]

Address @craig.topper's comments.

[HsiangKai]

Rebase on D93784.

[craig.topper]

LGTM

[HsiangKai]

Rebase.

[frasercrmck]

LGTM

llvm/lib/Target/RISCV/RISCVInstrFormats.td

 def WidenCvt     : RISCVVConstraint<!or(VS2Constraint.Value,
                                         VMConstraint.Value,
                                         OneInput.Value)>;
 def Narrow       : RISCVVConstraint<!or(VS2Constraint.Value,
                                         VMConstraint.Value)>;
 def NarrowCvt    : RISCVVConstraint<!or(VS2Constraint.Value,
                                         VMConstraint.Value,
                                         OneInput.Value)>;
-def Vmadc        : RISCVVConstraint<!or(VS2Constraint.Value,
-                                        VS1Constraint.Value)>;
 def Iota         : RISCVVConstraint<!or(VS2Constraint.Value,
                                         VMConstraint.Value,
                                         OneInput.Value)>;
 def SlideUp      : RISCVVConstraint<!or(VS2Constraint.Value,
                                         VMConstraint.Value)>;
 def Vrgather     : RISCVVConstraint<!or(VS2Constraint.Value,
                                         VS1Constraint.Value,
                                         VMConstraint.Value)>;

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

 defm VSEXT_VF8 : VALU_MV_VS2<"vsext.vf8", 0b010010, 0b00011>;
 defm VZEXT_VF4 : VALU_MV_VS2<"vzext.vf4", 0b010010, 0b00100>;
 defm VSEXT_VF4 : VALU_MV_VS2<"vsext.vf4", 0b010010, 0b00101>;
 defm VZEXT_VF2 : VALU_MV_VS2<"vzext.vf2", 0b010010, 0b00110>;
 defm VSEXT_VF2 : VALU_MV_VS2<"vsext.vf2", 0b010010, 0b00111>;
 
 // Vector Integer Add-with-Carry / Subtract-with-Borrow Instructions
 defm VADC_V : VALUm_IV_V_X_I<"vadc", 0b010000>;
-let Constraints = "@earlyclobber $vd", RVVConstraint = Vmadc in {
+let RVVConstraint = NoConstraint in {
 defm VMADC_V : VALUm_IV_V_X_I<"vmadc", 0b010001>;
 defm VMADC_V : VALUNoVm_IV_V_X_I<"vmadc", 0b010001>;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = Vmadc
+} // RVVConstraint = NoConstraint
 defm VSBC_V : VALUm_IV_V_X<"vsbc", 0b010010>;
-let Constraints = "@earlyclobber $vd", RVVConstraint = Vmadc in {
+let RVVConstraint = NoConstraint in {
 defm VMSBC_V : VALUm_IV_V_X<"vmsbc", 0b010011>;
 defm VMSBC_V : VALUNoVm_IV_V_X<"vmsbc", 0b010011>;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = Vmadc
+} // RVVConstraint = NoConstraint
 
 // Vector Bitwise Logical Instructions
 defm VAND_V : VALU_IV_V_X_I<"vand", 0b001001>;
 defm VOR_V : VALU_IV_V_X_I<"vor", 0b001010>;
 defm VXOR_V : VALU_IV_V_X_I<"vxor", 0b001011>;
 
 def : InstAlias<"vnot.v $vd, $vs$vm",
                 (VXOR_VI VR:$vd, VR:$vs, -1, VMaskOp:$vm)>;
def VPOPC_M : RVInstV<0b010000, 0b10000, OPMVV, (outs GPR:$vd),
                         "vpopc.m", "$vd, $vs2$vm">;
 
 // vfirst find-first-set mask bit
 def VFIRST_M : RVInstV<0b010000, 0b10001, OPMVV, (outs GPR:$vd),
                         (ins VR:$vs2, VMaskOp:$vm),
                         "vfirst.m", "$vd, $vs2$vm">;
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
 
+let Constraints = "@earlyclobber $vd", RVVConstraint = Iota in {
 // vmsbf.m set-before-first mask bit
 defm VMSBF_M : VALU_MV_VS2<"vmsbf.m", 0b010100, 0b00001>;
-
 // vmsif.m set-including-first mask bit
 defm VMSIF_M : VALU_MV_VS2<"vmsif.m", 0b010100, 0b00011>;
-
 // vmsof.m set-only-first mask bit
 defm VMSOF_M : VALU_MV_VS2<"vmsof.m", 0b010100, 0b00010>;
-
 // Vector Iota Instruction
-let Constraints = "@earlyclobber $vd", RVVConstraint = Iota in {
 defm VIOTA_M : VALU_MV_VS2<"viota.m", 0b010100, 0b10000>;
 } // Constraints = "@earlyclobber $vd", RVVConstraint = Iota
 
 // Vector Element Index Instruction
 let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
 def VID_V : RVInstV<0b010100, 0b10001, OPMVV, (outs VR:$vd),
                       (ins VMaskOp:$vm), "vid.v", "$vd$vm"> {
   let vs2 = 0;

 
 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0, vm = 1
 } // Predicates = [HasStdExtV, HasStdExtF]
 
 let Predicates = [HasStdExtV] in {
 // Vector Slide Instructions
 let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in {
 defm VSLIDEUP_V : VALU_IV_X_I<"vslideup", 0b001110, uimm5>;
-} // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp
-defm VSLIDEDOWN_V : VALU_IV_X_I<"vslidedown", 0b001111, uimm5>;
-
-let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in {
 defm VSLIDE1UP_V : VALU_MV_X<"vslide1up", 0b001110>;
 } // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp
+defm VSLIDEDOWN_V : VALU_IV_X_I<"vslidedown", 0b001111, uimm5>;
 defm VSLIDE1DOWN_V : VALU_MV_X<"vslide1down", 0b001111>;
 } // Predicates = [HasStdExtV]
 
 let Predicates = [HasStdExtV, HasStdExtF] in {
 let Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp in {
 defm VFSLIDE1UP_V : VALU_FV_F<"vfslide1up", 0b001110>;
 } // Constraints = "@earlyclobber $vd", RVVConstraint = SlideUp
 defm VFSLIDE1DOWN_V : VALU_FV_F<"vfslide1down", 0b001111>;

llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h

enum RVVConstraintType {
 
   // Illegal instructions:
   //
   // * The destination vector register group for a masked vector instruction
   // cannot overlap the source mask register (v0), unless the destination vector
   // register is being written with a mask value (e.g., comparisons) or the
   // scalar result of a reduction.
   //
-  // * Widening: The destination vector register group cannot overlap a source
-  // vector register group of a different EEW
+  // * Widening: The destination EEW is greater than the source EEW, the source
+  // EMUL is at least 1. The destination vector register group cannot overlap
+  // with the source vector register groups besides the highest-numbered part of
+  // the destination register group.
+  //
+  // * Narrowing: The destination EEW is smaller than the source EEW. The
+  // destination vector register group cannot overlap with the source vector
+  // register groups besides the lowest-numbered part of the source register
+  // group.
   //
-  // * Narrowing: The destination vector register group cannot overlap the
-  // first source vector register group
+  // * vmsbf.m/vmsif.m/vmsof.m: The destination register cannot overlap the
+  // source register and, if masked, cannot overlap the mask register ('v0').
   //
-  // * For vadc and vsbc, an illegal instruction exception is raised if the
-  // destination vector register is v0.
-  //
-  // * For vmadc and vmsbc, an illegal instruction exception is raised if the
-  // destination vector register overlaps a source vector register group.
-  //
-  // * viota: An illegal instruction exception is raised if the destination
-  // vector register group overlaps the source vector mask register. If the
-  // instruction is masked, an illegal instruction exception is issued if the
-  // destination vector register group overlaps v0.
+  // * viota: The destination register cannot overlap the source register and,
+  // if masked, cannot overlap the mask register ('v0').
   //
   // * v[f]slide[1]up: The destination vector register group for vslideup cannot
   // overlap the source vector register group.
   //
   // * vrgather: The destination vector register group cannot overlap with the
   // source vector register groups.
   //
   // * vcompress: The destination vector register group cannot overlap the
   // source vector register group or the source mask register
   WidenV = VS2Constraint | VS1Constraint | VMConstraint,
   WidenW = VS1Constraint | VMConstraint,
   WidenCvt = VS2Constraint | VMConstraint | OneInput,
-  Narrow = VS2Constraint | VMConstraint,
-  NarrowCvt = VS2Constraint | VMConstraint | OneInput,
-  Vmadc = VS2Constraint | VS1Constraint,
+  Narrow = VMConstraint,
+  NarrowCvt = VMConstraint | OneInput,
   Iota = VS2Constraint | VMConstraint | OneInput,
-  SlideUp = VS2Constraint | VMConstraint,
-  Vrgather = VS2Constraint | VS1Constraint | VMConstraint,
+  SlideUp = VS2Constraint,
+  Vrgather = VS2Constraint | VS1Constraint,
   Vcompress = VS2Constraint | VS1Constraint,
 };
 
 // RISC-V Specific Machine Operand Flags
 enum {
   MO_None = 0,
   MO_CALL = 1,
   MO_PLT = 2,

llvm/test/MC/RISCV/rvv/invalid.s

 vfwsub.wf v0, v2, fa0, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vfwsub.wf v0, v2, fa0, v0.t
 
 vadc.vvm v0, v2, v4, v0
 # CHECK-ERROR: The destination vector register group cannot be V0.
 # CHECK-ERROR-LABEL: vadc.vvm v0, v2, v4, v0
 
-vmadc.vvm v2, v2, v4, v0
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vmadc.vvm v2, v2, v4, v0
-
-vmadc.vvm v4, v2, v4, v0
-# CHECK-ERROR: The destination vector register group cannot overlap the source vector register group.
-# CHECK-ERROR-LABEL: vmadc.vvm v4, v2, v4, v0
-
 vadd.vv v0, v2, v4, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vadd.vv v0, v2, v4, v0.t
 
 vadd.vx v0, v2, a0, v0.t
 # CHECK-ERROR: The destination vector register group cannot overlap the mask register.
 # CHECK-ERROR-LABEL: vadd.vx v0, v2, a0, v0.t