[ARM] Turn pred_cast(xor(x, -1)) into xor(pred_cast(x), -1)

[dmgreen]

Summary

This folds a not (an xor -1) though a predicate_cast, so that it can be turned into a VPNOT and potentially be folded away as an "else" predicate inside a VPT block.

[simon_tatham]

llvm/lib/Target/ARM/ARMISelLowering.cpp

13855

VPT predicates are only 16 bits wide, so I think we could legally apply this to any constant XOR that has the bottom 16 bits set, not just 0xFFFFFFFF.

In case somebody wrote out pred ^ 0xFFFF longhand in source code, would it be better to do that?

[dmgreen]

llvm/lib/Target/ARM/ARMISelLowering.cpp

13855

Thanks for taking a look. Long story short, the rest of llvm will like to convert xor i32 x, 0xffff to xor i32 x, -1 as it represents a not and is simpler to deal with. Because we tell it that the demanded bits of a PRED_CAST are the lower bits, it will do that transform for us and here we only need to check for a full mask.

There is a isBitwiseNot helper function though, which will do this for us. I'll change it to use that and add an extra test.

[dmgreen]

Use isBitwiseNot and add an extra test.

[simon_tatham]

llvm/test/CodeGen/Thumb2/mve-pred-constfold.ll

107

(Incidentally, it's a shame this one couldn't have ended up removing the VPNOT completely and just swapping round the operands of the VPSEL!)

[avieira]

Accidentally linked my commit of https://reviews.llvm.org/D92236 to this revision. Apologies.

llvm/lib/Target/ARM/ARMISelLowering.cpp

PerformPREDICATE_CASTCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
   // PREDICATE_CAST(PREDICATE_CAST(x)) == PREDICATE_CAST(x)
   if (Op->getOpcode() == ARMISD::PREDICATE_CAST) {
     // If the valuetypes are the same, we can remove the cast entirely.
     if (Op->getOperand(0).getValueType() == VT)
       return Op->getOperand(0);
     return DCI.DAG.getNode(ARMISD::PREDICATE_CAST, dl, VT, Op->getOperand(0));
   }
 
+  // Turn pred_cast(xor x, -1) into xor(pred_cast x, -1), in order to produce
+  // more VPNOT which might get folded as else predicates.
+  if (Op.getValueType() == MVT::i32 && isBitwiseNot(Op)) {
+    SDValue X =
+        DCI.DAG.getNode(ARMISD::PREDICATE_CAST, dl, VT, Op->getOperand(0));
+    SDValue C = DCI.DAG.getNode(ARMISD::PREDICATE_CAST, dl, VT,
+                                DCI.DAG.getConstant(65535, dl, MVT::i32));
+    return DCI.DAG.getNode(ISD::XOR, dl, VT, X, C);
+  }
+
   // Only the bottom 16 bits of the source register are used.
   if (Op.getValueType() == MVT::i32) {
     APInt DemandedMask = APInt::getLowBitsSet(32, 16);
     const TargetLowering &TLI = DCI.DAG.getTargetLoweringInfo();
     if (TLI.SimplifyDemandedBits(Op, DemandedMask, DCI))
       return SDValue(N, 0);
   }
   return SDValue();

llvm/test/CodeGen/Thumb2/mve-pred-constfold.ll

 
 
 define arm_aapcs_vfpcc void @const(<8 x i16> %acc0, <8 x i16> %acc1, i32* nocapture %px, i16 signext %p0) {
 ; CHECK-LABEL: const:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r4, r6, r7, lr}
 ; CHECK-NEXT:    push {r4, r6, r7, lr}
 ; CHECK-NEXT:    vmsr p0, r1
-; CHECK-NEXT:    mvns r1, r1
-; CHECK-NEXT:    vpstt
+; CHECK-NEXT:    vpsttee
 ; CHECK-NEXT:    vaddvt.s16 r12, q1
 ; CHECK-NEXT:    vaddvt.s16 r2, q0
-; CHECK-NEXT:    vmsr p0, r1
-; CHECK-NEXT:    vpstt
-; CHECK-NEXT:    vaddvt.s16 r4, q1
-; CHECK-NEXT:    vaddvt.s16 r6, q0
+; CHECK-NEXT:    vaddve.s16 r4, q1
+; CHECK-NEXT:    vaddve.s16 r6, q0
 ; CHECK-NEXT:    stm.w r0, {r2, r6, r12}
 ; CHECK-NEXT:    str r4, [r0, #12]
 ; CHECK-NEXT:    pop {r4, r6, r7, pc}
 entry:
   %0 = zext i16 %p0 to i32
   %1 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %0)
   %2 = tail call i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16> %acc0, i32 0, <8 x i1> %1)
   %3 = xor i16 %p0, -1
entry:
   ret void
 }
 
 
 
 define arm_aapcs_vfpcc <4 x i32> @xorvpnot_i32(<4 x i32> %acc0, i16 signext %p0) {
 ; CHECK-LABEL: xorvpnot_i32:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    mvns r0, r0
-; CHECK-NEXT:    vmov.i32 q1, #0x0
 ; CHECK-NEXT:    vmsr p0, r0
+; CHECK-NEXT:    vmov.i32 q1, #0x0
+; CHECK-NEXT:    vpnot
 ; CHECK-NEXT:    vpsel q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %l3 = xor i16 %p0, -1
   %l4 = zext i16 %l3 to i32
   %l5 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %l4)
   %l6 = select <4 x i1> %l5, <4 x i32> %acc0, <4 x i32> zeroinitializer
   ret <4 x i32> %l6
 }
 
 define arm_aapcs_vfpcc <8 x i16> @xorvpnot_i16(<8 x i16> %acc0, i16 signext %p0) {
 ; CHECK-LABEL: xorvpnot_i16:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    mvns r0, r0
-; CHECK-NEXT:    vmov.i32 q1, #0x0
 ; CHECK-NEXT:    vmsr p0, r0
+; CHECK-NEXT:    vmov.i32 q1, #0x0
+; CHECK-NEXT:    vpnot
 ; CHECK-NEXT:    vpsel q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %l3 = xor i16 %p0, -1
   %l4 = zext i16 %l3 to i32
   %l5 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %l4)
   %l6 = select <8 x i1> %l5, <8 x i16> %acc0, <8 x i16> zeroinitializer
   ret <8 x i16> %l6
 }
 
 define arm_aapcs_vfpcc <16 x i8> @xorvpnot_i8(<16 x i8> %acc0, i16 signext %p0) {
 ; CHECK-LABEL: xorvpnot_i8:
 ; CHECK:       @ %bb.0: @ %entry
-; CHECK-NEXT:    mvns r0, r0
-; CHECK-NEXT:    vmov.i32 q1, #0x0
 ; CHECK-NEXT:    vmsr p0, r0
+; CHECK-NEXT:    vmov.i32 q1, #0x0
+; CHECK-NEXT:    vpnot
 ; CHECK-NEXT:    vpsel q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %l3 = xor i16 %p0, -1
   %l4 = zext i16 %l3 to i32
   %l5 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %l4)
   %l6 = select <16 x i1> %l5, <16 x i8> %acc0, <16 x i8> zeroinitializer
   ret <16 x i8> %l6
 }
 
+define arm_aapcs_vfpcc <16 x i8> @xorvpnot_i8_2(<16 x i8> %acc0, i32 %p0) {
+; CHECK-LABEL: xorvpnot_i8_2:
+; CHECK:       @ %bb.0: @ %entry
+; CHECK-NEXT:    vmsr p0, r0
+; CHECK-NEXT:    vmov.i32 q1, #0x0
+; CHECK-NEXT:    vpnot
+; CHECK-NEXT:    vpsel q0, q0, q1
+; CHECK-NEXT:    bx lr
+entry:
+  %l3 = xor i32 %p0, 65535
+  %l5 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %l3)
+  %l6 = select <16 x i1> %l5, <16 x i8> %acc0, <16 x i8> zeroinitializer
+  ret <16 x i8> %l6
+}
+
 
 
 declare i32 @llvm.arm.mve.pred.v2i.v4i1(<4 x i1>)
 declare i32 @llvm.arm.mve.pred.v2i.v8i1(<8 x i1>)
 declare i32 @llvm.arm.mve.pred.v2i.v16i1(<16 x i1>)
 
 declare <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32)
 declare <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32)
 declare <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32)
 
 declare i32 @llvm.arm.mve.addv.predicated.v4i32.v4i1(<4 x i32>, i32, <4 x i1>)
 declare i32 @llvm.arm.mve.addv.predicated.v8i16.v8i1(<8 x i16>, i32, <8 x i1>)
 declare i32 @llvm.arm.mve.addv.predicated.v16i8.v16i1(<16 x i8>, i32, <16 x i1>)