[ARM] PREDICATE_CAST demanded bits

[dmgreen]

Summary

The PREDICATE_CAST node is used to model moves between MVE predicate registers and gpr's, and eventually become a VMSR p0, rn. When moving to a predicate only the bottom 16 bits of the sources register are demanded. This adds a simple fold for that, allowing it to potentially remove instructions like uxth.

llvm/lib/Target/ARM/ARMISelLowering.cpp

PerformPREDICATE_CASTCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
   // PREDICATE_CAST(PREDICATE_CAST(x)) == PREDICATE_CAST(x)
   if (Op->getOpcode() == ARMISD::PREDICATE_CAST) {
     // If the valuetypes are the same, we can remove the cast entirely.
     if (Op->getOperand(0).getValueType() == VT)
       return Op->getOperand(0);
     return DCI.DAG.getNode(ARMISD::PREDICATE_CAST, dl, VT, Op->getOperand(0));
   }
 
+  // Only the bottom 16 bits of the source register are used.
+  if (Op.getValueType() == MVT::i32) {
+    APInt DemandedMask = APInt::getLowBitsSet(32, 16);
+    const TargetLowering &TLI = DCI.DAG.getTargetLoweringInfo();
+    if (TLI.SimplifyDemandedBits(Op, DemandedMask, DCI))
+      return SDValue(N, 0);
+  }
   return SDValue();
 }
 
 static SDValue
 PerformVECTOR_REG_CASTCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI,
                               const ARMSubtarget *ST) {
   EVT VT = N->getValueType(0);
   SDValue Op = N->getOperand(0);

llvm/test/CodeGen/Thumb2/mve-pred-bitcast.ll

 ; CHECK-LE-NEXT:    push {r4, r6, r7, lr}
 ; CHECK-LE-NEXT:    .setfp r7, sp, #8
 ; CHECK-LE-NEXT:    add r7, sp, #8
 ; CHECK-LE-NEXT:    .pad #16
 ; CHECK-LE-NEXT:    sub sp, #16
 ; CHECK-LE-NEXT:    mov r4, sp
 ; CHECK-LE-NEXT:    bfc r4, #0, #4
 ; CHECK-LE-NEXT:    mov sp, r4
-; CHECK-LE-NEXT:    uxth r0, r0
 ; CHECK-LE-NEXT:    sub.w r4, r7, #8
-; CHECK-LE-NEXT:    vmov.i32 q1, #0x0
 ; CHECK-LE-NEXT:    vmsr p0, r0
+; CHECK-LE-NEXT:    vmov.i32 q1, #0x0
 ; CHECK-LE-NEXT:    vpsel q0, q0, q1
 ; CHECK-LE-NEXT:    mov sp, r4
 ; CHECK-LE-NEXT:    pop {r4, r6, r7, pc}
 ;
 ; CHECK-BE-LABEL: bitcast_to_v16i1:
 ; CHECK-BE:       @ %bb.0: @ %entry
 ; CHECK-BE-NEXT:    .save {r4, r6, r7, lr}
 ; CHECK-BE-NEXT:    push {r4, r6, r7, lr}
 ; CHECK-BE-NEXT:    .setfp r7, sp, #8
 ; CHECK-BE-NEXT:    add r7, sp, #8
 ; CHECK-BE-NEXT:    .pad #16
 ; CHECK-BE-NEXT:    sub sp, #16
 ; CHECK-BE-NEXT:    mov r4, sp
 ; CHECK-BE-NEXT:    bfc r4, #0, #4
 ; CHECK-BE-NEXT:    mov sp, r4
 ; CHECK-BE-NEXT:    vrev64.8 q1, q0
 ; CHECK-BE-NEXT:    vmov.i32 q0, #0x0
-; CHECK-BE-NEXT:    uxth r0, r0
 ; CHECK-BE-NEXT:    sub.w r4, r7, #8
 ; CHECK-BE-NEXT:    vrev32.8 q0, q0
 ; CHECK-BE-NEXT:    vmsr p0, r0
 ; CHECK-BE-NEXT:    vpsel q1, q1, q0
 ; CHECK-BE-NEXT:    vrev64.8 q0, q1
 ; CHECK-BE-NEXT:    mov sp, r4
 ; CHECK-BE-NEXT:    pop {r4, r6, r7, pc}
 entry:

llvm/test/CodeGen/Thumb2/mve-pred-constfold.ll

 }
 
 
 define arm_aapcs_vfpcc void @const(<8 x i16> %acc0, <8 x i16> %acc1, i32* nocapture %px, i16 signext %p0) {
 ; CHECK-LABEL: const:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    .save {r4, r6, r7, lr}
 ; CHECK-NEXT:    push {r4, r6, r7, lr}
-; CHECK-NEXT:    uxth r2, r1
+; CHECK-NEXT:    vmsr p0, r1
 ; CHECK-NEXT:    mvns r1, r1
-; CHECK-NEXT:    vmsr p0, r2
-; CHECK-NEXT:    uxth r1, r1
 ; CHECK-NEXT:    vpstt
 ; CHECK-NEXT:    vaddvt.s16 r12, q1
 ; CHECK-NEXT:    vaddvt.s16 r2, q0
 ; CHECK-NEXT:    vmsr p0, r1
 ; CHECK-NEXT:    vpstt
 ; CHECK-NEXT:    vaddvt.s16 r4, q1
 ; CHECK-NEXT:    vaddvt.s16 r6, q0
 ; CHECK-NEXT:    stm.w r0, {r2, r6, r12}

 
 
 
 define arm_aapcs_vfpcc <4 x i32> @xorvpnot_i32(<4 x i32> %acc0, i16 signext %p0) {
 ; CHECK-LABEL: xorvpnot_i32:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    mvns r0, r0
 ; CHECK-NEXT:    vmov.i32 q1, #0x0
-; CHECK-NEXT:    uxth r0, r0
 ; CHECK-NEXT:    vmsr p0, r0
 ; CHECK-NEXT:    vpsel q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %l3 = xor i16 %p0, -1
   %l4 = zext i16 %l3 to i32
   %l5 = tail call <4 x i1> @llvm.arm.mve.pred.i2v.v4i1(i32 %l4)
   %l6 = select <4 x i1> %l5, <4 x i32> %acc0, <4 x i32> zeroinitializer
   ret <4 x i32> %l6
 }
 
 define arm_aapcs_vfpcc <8 x i16> @xorvpnot_i16(<8 x i16> %acc0, i16 signext %p0) {
 ; CHECK-LABEL: xorvpnot_i16:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    mvns r0, r0
 ; CHECK-NEXT:    vmov.i32 q1, #0x0
-; CHECK-NEXT:    uxth r0, r0
 ; CHECK-NEXT:    vmsr p0, r0
 ; CHECK-NEXT:    vpsel q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %l3 = xor i16 %p0, -1
   %l4 = zext i16 %l3 to i32
   %l5 = tail call <8 x i1> @llvm.arm.mve.pred.i2v.v8i1(i32 %l4)
   %l6 = select <8 x i1> %l5, <8 x i16> %acc0, <8 x i16> zeroinitializer
   ret <8 x i16> %l6
 }
 
 define arm_aapcs_vfpcc <16 x i8> @xorvpnot_i8(<16 x i8> %acc0, i16 signext %p0) {
 ; CHECK-LABEL: xorvpnot_i8:
 ; CHECK:       @ %bb.0: @ %entry
 ; CHECK-NEXT:    mvns r0, r0
 ; CHECK-NEXT:    vmov.i32 q1, #0x0
-; CHECK-NEXT:    uxth r0, r0
 ; CHECK-NEXT:    vmsr p0, r0
 ; CHECK-NEXT:    vpsel q0, q0, q1
 ; CHECK-NEXT:    bx lr
 entry:
   %l3 = xor i16 %p0, -1
   %l4 = zext i16 %l3 to i32
   %l5 = tail call <16 x i1> @llvm.arm.mve.pred.i2v.v16i1(i32 %l4)
   %l6 = select <16 x i1> %l5, <16 x i8> %acc0, <16 x i8> zeroinitializer