[PowerPC] Add `hasSideEffects=0` for PLXVP and PSTXVP instructions definition

[NeHuang]

Summary

In this patch, we set hasSideEffects=0 for PLXVP and PSTXVP instructions definition in the td file.

[bsaleil]

Why do we need these flags for PLXVP and PSTXVP ? Please, add a test case showing why this is required.

[steven.zhang]

I think, this patch isn't needed any more as we have already specified the match pattern for these instructions and tblgen will infer the sideeffects from the pattern. See what we get from tblgen now(we didn't have the sideeffect bit):

{ 1191,       3,      1,      4,      39,     0|(1ULL<<MCID::MayLoad), 0x0ULL, nullptr, nullptr, OperandInfo158 },  // Inst #1191 = LXVP

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

let Predicates = [MMA] in {
   def : Pat<(v4i32 (PPCAccExtractVsx acc:$v, (i64 3))),
             Extracts.Vec3>;
   def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, (i64 0))),
             (v4i32 (EXTRACT_SUBREG $v, sub_vsx0))>;
   def : Pat<(v4i32 (PPCPairExtractVsx vsrpevenrc:$v, (i64 1))),
             (v4i32 (EXTRACT_SUBREG $v, sub_vsx1))>;
 }
 
-let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops] in {
+let mayLoad = 1, mayStore = 0, hasSideEffects = 0, Predicates = [PairedVectorMemops] in {
   def LXVP : DQForm_XTp5_RA17_MEM<6, 0, (outs vsrprc:$XTp),
                                   (ins memrix16:$DQ_RA), "lxvp $XTp, $DQ_RA",
                                   IIC_LdStLFD, []>;
   def LXVPX : XForm_XTp5_XAB5<31, 333, (outs vsrprc:$XTp), (ins memrr:$src),
                               "lxvpx $XTp, $src", IIC_LdStLFD,
                               []>;
 }
 
-let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops] in {
+let mayLoad = 0, mayStore = 1, hasSideEffects = 0, Predicates = [PairedVectorMemops] in {
   def STXVP : DQForm_XTp5_RA17_MEM<6, 1, (outs), (ins vsrprc:$XTp,
                                    memrix16:$DQ_RA), "stxvp $XTp, $DQ_RA",
                                    IIC_LdStLFD, []>;
   def STXVPX : XForm_XTp5_XAB5<31, 461, (outs), (ins vsrprc:$XTp, memrr:$dst),
                                "stxvpx $XTp, $dst", IIC_LdStLFD,
                                []>;
 }
 
-let mayLoad = 1, mayStore = 0, Predicates = [PairedVectorMemops, PrefixInstrs] in {
+let mayLoad = 1, mayStore = 0, hasSideEffects = 0, Predicates = [PairedVectorMemops, PrefixInstrs] in {
   defm PLXVP :
     8LS_DForm_R_XTp5_SI34_MEM_p<1, 58, (outs vsrprc:$XTp), (ins memri34:$D_RA),
                                 (ins memri34_pcrel:$D_RA), "plxvp $XTp, $D_RA",
                                 IIC_LdStLFD>;
 }
 
-let mayLoad = 0, mayStore = 1, Predicates = [PairedVectorMemops, PrefixInstrs] in {
+let mayLoad = 0, mayStore = 1, hasSideEffects = 0, Predicates = [PairedVectorMemops, PrefixInstrs] in {
   defm PSTXVP :
     8LS_DForm_R_XTp5_SI34_MEM_p<1, 62, (outs), (ins vsrprc:$XTp, memri34:$D_RA),
                                 (ins vsrprc:$XTp, memri34_pcrel:$D_RA),
                                 "pstxvp $XTp, $D_RA", IIC_LdStLFD>;
 }
 
 let Predicates = [PairedVectorMemops] in {
   // Intrinsics for Paired Vector Loads.