[PowerPC] Correct the bit-width definition for some imm operand in td.

[Esme]

Summary

The imm operand of some instructions are not defined accurately in td.
This is a small patch to correct these definitions.

[Esme]

Added test cases.

[qiucf]

(Not relevant question) Do we have intrinsics, or any exploitation in library for darn?

llvm/lib/Target/PowerPC/PPCInstrInfo.td

1900

L is two bits?

2435

sync only uses 2 bits for L? (9th-10th bit)

[nemanjai]

In D91603#2407503, @qiucf wrote:

(Not relevant question) Do we have intrinsics, or any exploitation in library for darn?

No, asm only. But if you know of a user for them and/or have the time to add them, we should match the ones GCC provided (https://gcc.gnu.org/onlinedocs/gcc-10.2.0/gcc/Basic-PowerPC-Built-in-Functions-Available-on-ISA-3_002e0.html#Basic-PowerPC-Built-in-Functions-Available-on-ISA-3_002e0):

long long __builtin_darn (void);
long long __builtin_darn_raw (void);
int __builtin_darn_32 (void);

[nemanjai]

llvm/lib/Target/PowerPC/PPCInstrInfo.td

1900

Changed in ISA 3.1 to 3 bits. Bit 8 was reserved before and a value larger than 0b11 had no meaning, so specifying it as 3 bits should be fine.

2435

I agree. The instruction format only allows 2 bits in the encoding here. The extra values added in ISA3.0 do not appear to have been used anywhere as doing so would have caused errors.

[steven.zhang]

This LGTM now as we have posted the follow up patch https://reviews.llvm.org/D92465 for darn intrinsic Nemanjai mentioned. But please hold on for several days to see if @nemanjai has more comments.

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
   def MADDLD8 : VAForm_1a<51, 
                        (outs g8rc :$RT), (ins g8rc:$RA, g8rc:$RB, g8rc:$RC),
                        "maddld $RT, $RA, $RB, $RC", IIC_IntMulHD,
                        [(set i64:$RT, (add_without_simm16 (mul_without_simm16 i64:$RA, i64:$RB), i64:$RC))]>,
                        isPPC64;
   def SETB8 : XForm_44<31, 128, (outs g8rc:$RT), (ins crrc:$BFA),
                        "setb $RT, $BFA", IIC_IntGeneral>, isPPC64;
 }
-def DARN : XForm_45<31, 755, (outs g8rc:$RT), (ins i32imm:$L),
+def DARN : XForm_45<31, 755, (outs g8rc:$RT), (ins u2imm:$L),
                      "darn $RT, $L", IIC_LdStLD>, isPPC64;
 def ADDPCIS : DXForm<19, 2, (outs g8rc:$RT), (ins i32imm:$D),
                      "addpcis $RT, $D", IIC_BrB, []>, isPPC64;
 def MODSD : XForm_8<31, 777, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
                         "modsd $rT, $rA, $rB", IIC_IntDivW,
                         [(set i64:$rT, (srem i64:$rA, i64:$rB))]>;
 def MODUD : XForm_8<31, 265, (outs g8rc:$rT), (ins g8rc:$rA, g8rc:$rB),
                         "modud $rT, $rA, $rB", IIC_IntDivW,

llvm/lib/Target/PowerPC/PPCInstrInfo.td

def DCBST  : DCB_Form<54, 0, (outs), (ins memrr:$dst), "dcbst $dst",
                       PPC970_DGroup_Single;
 def DCBZ   : DCB_Form<1014, 0, (outs), (ins memrr:$dst), "dcbz $dst",
                       IIC_LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
                       PPC970_DGroup_Single;
 def DCBZL  : DCB_Form<1014, 1, (outs), (ins memrr:$dst), "dcbzl $dst",
                       IIC_LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
                       PPC970_DGroup_Single;
 
-def DCBF   : DCB_Form_hint<86, (outs), (ins u5imm:$TH, memrr:$dst),
+def DCBF   : DCB_Form_hint<86, (outs), (ins u3imm:$TH, memrr:$dst),
                       "dcbf $dst, $TH", IIC_LdStDCBF, []>,
                       PPC970_DGroup_Single;
 
 let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in {
 def DCBT   : DCB_Form_hint<278, (outs), (ins u5imm:$TH, memrr:$dst),
                       "dcbt $dst, $TH", IIC_LdStDCBF, []>,
                       PPC970_DGroup_Single;
 def DCBTST : DCB_Form_hint<246, (outs), (ins u5imm:$TH, memrr:$dst),
def : Pat<(pre_store f64:$rS, iPTR:$ptrreg, iPTR:$ptroff),
           (STFDUX $rS, $ptrreg, $ptroff)>;
 }
 
 // Store Multiple
 let mayStore = 1, mayLoad = 0, hasSideEffects = 0 in
 def STMW : DForm_1<47, (outs), (ins gprc:$rS, memri:$dst),
                    "stmw $rS, $dst", IIC_LdStLMW, []>;
 
-def SYNC : XForm_24_sync<31, 598, (outs), (ins i32imm:$L),
+def SYNC : XForm_24_sync<31, 598, (outs), (ins u2imm:$L),
                         "sync $L", IIC_LdStSync, []>;
 
 let isCodeGenOnly = 1 in {
   def MSYNC : XForm_24_sync<31, 598, (outs), (ins),
                            "msync", IIC_LdStSync, []> {
     let L = 0;
   }
 }
def STSWI : XForm_base_r3xo_memOp<31, 725, (outs),
                                   "stswi $RT, $A, $B", IIC_LdStLoad, []>;
 
 def ISYNC : XLForm_2_ext<19, 150, 0, 0, 0, (outs), (ins),
                          "isync", IIC_SprISYNC, []>;
 
 def ICBI : XForm_1a<31, 982, (outs), (ins memrr:$src),
                     "icbi $src", IIC_LdStICBI, []>;
 
-def WAIT : XForm_24_sync<31, 30, (outs), (ins i32imm:$L),
+def WAIT : XForm_24_sync<31, 30, (outs), (ins u2imm:$L),
                          "wait $L", IIC_LdStLoad, []>;
 
 def MBAR : XForm_mbar<31, 854, (outs), (ins u5imm:$MO),
                          "mbar $MO", IIC_LdStLoad>, Requires<[IsBookE]>;
 
 def MTSR: XForm_sr<31, 210, (outs), (ins gprc:$RS, u4imm:$SR),
             "mtsr $SR, $RS", IIC_SprMTSR>;
 
 def MFSR: XForm_sr<31, 595, (outs gprc:$RS), (ins u4imm:$SR),
             "mfsr $RS, $SR", IIC_SprMFSR>;
 
 def MTSRIN: XForm_srin<31, 242, (outs), (ins gprc:$RS, gprc:$RB),
             "mtsrin $RS, $RB", IIC_SprMTSR>;
 
 def MFSRIN: XForm_srin<31, 659, (outs gprc:$RS), (ins gprc:$RB),
             "mfsrin $RS, $RB", IIC_SprMFSR>;
 
-def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, i32imm:$L),
+def MTMSR: XForm_mtmsr<31, 146, (outs), (ins gprc:$RS, u1imm:$L),
                     "mtmsr $RS, $L", IIC_SprMTMSR>;
 
 def WRTEE: XForm_mtmsr<31, 131, (outs), (ins gprc:$RS),
                     "wrtee $RS", IIC_SprMTMSR>, Requires<[IsBookE]> {
   let L = 0;
 }
 
 def WRTEEI: I<31, (outs), (ins i1imm:$E), "wrteei $E", IIC_SprMTMSR>,

 def : InstAlias<"dci 0", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
 def : InstAlias<"dccci", (DCCCI R0, R0)>, Requires<[IsPPC4xx]>;
 def : InstAlias<"ici 0", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
 def : InstAlias<"iccci", (ICCCI R0, R0)>, Requires<[IsPPC4xx]>;
 
 def MFMSR : XForm_rs<31, 83, (outs gprc:$RT), (ins),
                   "mfmsr $RT", IIC_SprMFMSR, []>;
 
-def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, i32imm:$L),
+def MTMSRD : XForm_mtmsr<31, 178, (outs), (ins gprc:$RS, u1imm:$L),
                     "mtmsrd $RS, $L", IIC_SprMTMSRD>;
 
 def MCRFS : XLForm_3<63, 64, (outs crrc:$BF), (ins crrc:$BFA),
                      "mcrfs $BF, $BFA", IIC_BrMCR>;
 
 // If W is 0 and BF is 7, the 60:63 bits will be set, we should set the
 // implicit-def RM.
 def MTFSFI : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
                       "mtfsfi $BF, $U, $W", IIC_IntMFFS>;
 let Defs = [CR1] in
 def MTFSFI_rec : XLForm_4<63, 134, (outs crrc:$BF), (ins i32imm:$U, i32imm:$W),
                        "mtfsfi. $BF, $U, $W", IIC_IntMFFS>, isRecordForm;
 
 def : InstAlias<"mtfsfi $BF, $U", (MTFSFI crrc:$BF, i32imm:$U, 0)>;
 def : InstAlias<"mtfsfi. $BF, $U", (MTFSFI_rec crrc:$BF, i32imm:$U, 0)>;
 
 let Predicates = [HasFPU] in {
 let Defs = [RM] in {
 def MTFSF : XFLForm_1<63, 711, (outs),
-                      (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
+                      (ins i32imm:$FLM, f8rc:$FRB, u1imm:$L, i32imm:$W),
                       "mtfsf $FLM, $FRB, $L, $W", IIC_IntMFFS, []>;
 let Defs = [CR1] in
 def MTFSF_rec : XFLForm_1<63, 711, (outs),
-                       (ins i32imm:$FLM, f8rc:$FRB, i32imm:$L, i32imm:$W),
+                       (ins i32imm:$FLM, f8rc:$FRB, u1imm:$L, i32imm:$W),
                        "mtfsf. $FLM, $FRB, $L, $W", IIC_IntMFFS, []>, isRecordForm;
 }
 
 def : InstAlias<"mtfsf $FLM, $FRB", (MTFSF i32imm:$FLM, f8rc:$FRB, 0, 0)>;
 def : InstAlias<"mtfsf. $FLM, $FRB", (MTFSF_rec i32imm:$FLM, f8rc:$FRB, 0, 0)>;
 }
 
 def SLBIE : XForm_16b<31, 434, (outs), (ins gprc:$RB),

llvm/test/MC/PowerPC/ppc64-errors.s

 # CHECK: error: invalid operand for instruction
 # CHECK-NEXT: add 3, symbol@tls, 4
               add 3, symbol@tls, 4
 
 # CHECK: error: invalid operand for instruction
 # CHECK-NEXT: subf 3, 4, symbol@tls
               subf 3, 4, symbol@tls
 
+# Unsigned 1-bit immediate operands
+
+# CHECK: error: invalid operand for instruction
+# CHECK-NEXT: mtmsr 1, 2
+              mtmsr 1, 2
+
+# CHECK: error: invalid operand for instruction
+# CHECK-NEXT: mtmsrd 1, 2
+              mtmsrd 1, 2
+
+# CHECK: error: invalid operand for instruction
+# CHECK-NEXT: mtfsf 1, 2, 2, 1
+              mtfsf 1, 2, 2, 1
+
+# CHECK: error: invalid operand for instruction
+# CHECK-NEXT: mtfsf. 1, 2, 2, 1
+              mtfsf. 1, 2, 2, 1
+
+# Unsigned 2-bit immediate operands
+
+# CHECK: error: invalid operand for instruction
+# CHECK-NEXT: darn 1, 4
+              darn 1, 4
+
+# CHECK: error: invalid operand for instruction
+# CHECK-NEXT: wait 4
+              wait 4
+
+# CHECK: error: invalid operand for instruction
+# CHECK-NEXT: sync 4
+              sync 4
+
+# Unsigned 3-bit immediate operands
+
+# CHECK: error: invalid operand for instruction
+# CHECK-NEXT: dcbf 0, 1, 8
+              dcbf 0, 1, 8
+
 # Signed 16-bit immediate operands
 
 # CHECK: error: invalid operand for instruction
 # CHECK-NEXT: addi 1, 0, -32769
               addi 1, 0, -32769
 
 # CHECK: error: invalid operand for instruction
 # CHECK-NEXT: addi 1, 0, 32768