[PowerPC] Implement intrinsic for DARN instruction

[qiucf]

Summary

Instruction darn was introduced in ISA 3.0. It means 'Deliver A Random Number'.

The immediate number L means:

• L=0, the generated random number is 32-bit (higher 32-bits are all-zero)
• L=1, the generated random number is 'conditioned' (processed by hardware to reduce bias)
• L=2, the generated random number is not conditioned, directly from noise source

GCC implements them in three separate intrinsics. (__builtin_darn, __builtin_darn_32 and __builtin_darn_raw)

This patch also addresses Bugzilla PR39800.

[steven.zhang]

LGTM.

[qiucf]

In D92465#2438602, @steven.zhang wrote:

LGTM.

Thanks for reviewing! Maybe we need a predicate to guard it to prevent generating it on P8 or earlier targets? And as I see for other intrinsics (for example, dcbfps), if current platform doesn't support it, llc would crash and say LLVM ERROR: Cannot select: intrinsic %llvm.ppc.dcbfps. This is expected, but is there some way to express normal error to user instead of internal crash?

[steven.zhang]

In D92465#2438652, @qiucf wrote:

In D92465#2438602, @steven.zhang wrote:

LGTM.

Thanks for reviewing! Maybe we need a predicate to guard it to prevent generating it on P8 or earlier targets? And as I see for other intrinsics (for example, dcbfps), if current platform doesn't support it, llc would crash and say LLVM ERROR: Cannot select: intrinsic %llvm.ppc.dcbfps. This is expected, but is there some way to express normal error to user instead of internal crash?

Yes, it should be guarded. But please leave the LLVM ERROR alone as it is by design I think.

clang/include/clang/Basic/BuiltinsPPC.def

 BUILTIN(__builtin_divdeu, "ULLiULLiULLi", "")
 BUILTIN(__builtin_bpermd, "SLLiSLLiSLLi", "")
 BUILTIN(__builtin_pdepd, "ULLiULLiULLi", "")
 BUILTIN(__builtin_pextd, "ULLiULLiULLi", "")
 BUILTIN(__builtin_cfuged, "ULLiULLiULLi", "")
 BUILTIN(__builtin_cntlzdm, "ULLiULLiULLi", "")
 BUILTIN(__builtin_cnttzdm, "ULLiULLiULLi", "")
 
+// Generate random number
+BUILTIN(__builtin_darn, "LLi", "")
+BUILTIN(__builtin_darn_raw, "LLi", "")
+BUILTIN(__builtin_darn_32, "i", "")
+
 // Vector int128 (un)pack
 BUILTIN(__builtin_unpack_vector_int128, "ULLiV1LLLii", "")
 BUILTIN(__builtin_pack_vector_int128, "V1LLLiULLiULLi", "")
 
 // Set the floating point rounding mode
 BUILTIN(__builtin_setrnd, "di", "")
 
 // Get content from current FPSCR

clang/test/CodeGen/builtins-ppc.c

 void test_builtin_ppc_flm() {
   volatile double res;
   // CHECK: call double @llvm.ppc.readflm()
   res = __builtin_readflm();
 
   // CHECK: call double @llvm.ppc.setflm(double %1)
   res = __builtin_setflm(res);
 }
+
+void test_builtin_ppc_darn() {
+  volatile long res;
+  volatile int x;
+  // CHECK: call i64 @llvm.ppc.darn()
+  res = __builtin_darn();
+
+  // CHECK: call i64 @llvm.ppc.darnraw()
+  res = __builtin_darn_raw();
+
+  // CHECK: call i32 @llvm.ppc.darn32()
+  x = __builtin_darn_32();
+}

llvm/include/llvm/IR/IntrinsicsPowerPC.td

def int_ppc_divweu : GCCBuiltin<"__builtin_divweu">,
                                  [IntrNoMem]>;
   def int_ppc_divde : GCCBuiltin<"__builtin_divde">,
                       Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],
                                 [IntrNoMem]>;
   def int_ppc_divdeu : GCCBuiltin<"__builtin_divdeu">,
                        Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],
                                  [IntrNoMem]>;
 
+  // Generate a random number
+  def int_ppc_darn : GCCBuiltin<"__builtin_darn">,
+                     Intrinsic<[llvm_i64_ty], [], [IntrNoMem]>;
+  def int_ppc_darnraw : GCCBuiltin<"__builtin_darn_raw">,
+                     Intrinsic<[llvm_i64_ty], [], [IntrNoMem]>;
+  def int_ppc_darn32 : GCCBuiltin<"__builtin_darn_32">,
+                     Intrinsic<[llvm_i32_ty], [], [IntrNoMem]>;
+
   // Bit permute doubleword
   def int_ppc_bpermd : GCCBuiltin<"__builtin_bpermd">,
                        Intrinsic<[llvm_i64_ty], [llvm_i64_ty, llvm_i64_ty],
                                  [IntrNoMem]>;
 
   // Parallel Bits Deposit/Extract Doubleword Builtins.
   def int_ppc_pdepd
       : GCCBuiltin<"__builtin_pdepd">,

llvm/lib/Target/PowerPC/PPCInstr64Bit.td

 // 64-bits atomic loads and stores
 def : Pat<(atomic_load_64 iaddrX4:$src), (LD  memrix:$src)>;
 def : Pat<(atomic_load_64 xaddrX4:$src),  (LDX memrr:$src)>;
 
 def : Pat<(atomic_store_64 iaddrX4:$ptr, i64:$val), (STD  g8rc:$val, memrix:$ptr)>;
 def : Pat<(atomic_store_64 xaddrX4:$ptr,  i64:$val), (STDX g8rc:$val, memrr:$ptr)>;
 
 let Predicates = [IsISA3_0] in {
+// DARN (deliver random number)
+// L=0 for 32-bit, L=1 for conditioned random, L=2 for raw random
+def : Pat<(int_ppc_darn32), (EXTRACT_SUBREG (DARN 0), sub_32)>;
+def : Pat<(int_ppc_darn), (DARN 1)>;
+def : Pat<(int_ppc_darnraw), (DARN 2)>;
 
 class X_L1_RA5_RB5<bits<6> opcode, bits<10> xo, string opc, RegisterOperand ty,
                    InstrItinClass itin, list<dag> pattern>
   : X_L1_RS5_RS5<opcode, xo, (outs), (ins ty:$rA, ty:$rB, u1imm:$L),
                  !strconcat(opc, " $rA, $rB, $L"), itin, pattern>;
 
 let Interpretation64Bit = 1, isCodeGenOnly = 1 in {
 def CP_COPY8   : X_L1_RA5_RB5<31, 774, "copy"  , g8rc, IIC_LdStCOPY, []>;

llvm/test/CodeGen/PowerPC/builtins-ppc-p9-darn.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -verify-machineinstrs -mtriple powerpc64le -mcpu=pwr9 | FileCheck %s
+
+define i64 @raw() {
+; CHECK-LABEL: raw:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    darn 3, 2
+; CHECK-NEXT:    blr
+entry:
+  %0 = call i64 @llvm.ppc.darnraw()
+  ret i64 %0
+}
+
+define i64 @conditioned() {
+; CHECK-LABEL: conditioned:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    darn 3, 1
+; CHECK-NEXT:    blr
+entry:
+  %0 = call i64 @llvm.ppc.darn()
+  ret i64 %0
+}
+
+define signext i32 @word() {
+; CHECK-LABEL: word:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    darn 3, 0
+; CHECK-NEXT:    extsw 3, 3
+; CHECK-NEXT:    blr
+entry:
+  %0 = call i32 @llvm.ppc.darn32()
+  ret i32 %0
+}
+
+declare i64 @llvm.ppc.darn()
+declare i64 @llvm.ppc.darnraw()
+declare i32 @llvm.ppc.darn32()