riscv_sllw/srlw only reads the lower 32 bits of the first operand.
And the lower 5 bits of the second operands. Whether the upper
32 bits of the input are sign bits or not doesn't matter.
Also use ineg and not to shorten the patterns.
Paths
| Differential D90668
[RISCV] Remove assertsexti32 from inputs to riscv_sllw/srlw nodes in B extension isel patterns. ClosedPublic Authored by craig.topper on Nov 2 2020, 9:58 PM.
Details Summary riscv_sllw/srlw only reads the lower 32 bits of the first operand. Also use ineg and not to shorten the patterns.
Diff Detail
Event TimelineThis revision is now accepted and ready to land.Nov 4 2020, 6:58 AM This revision was landed with ongoing or failed builds.Nov 4 2020, 10:35 AM Closed by commit rG0122a4ea661d: [RISCV] Remove assertsexti32 from inputs to riscv_sllw/srlw nodes in B… (authored by craig.topper). · Explain Why This revision was automatically updated to reflect the committed changes.
Revision Contents
Diff 302901 llvm/lib/Target/RISCV/RISCVInstrInfoB.td
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