Page MenuHomePhabricator

[RISCV] Remove assertsexti32 from inputs to riscv_sllw/srlw nodes in B extension isel patterns.

Authored by craig.topper on Nov 2 2020, 9:58 PM.



riscv_sllw/srlw only reads the lower 32 bits of the first operand.
And the lower 5 bits of the second operands. Whether the upper
32 bits of the input are sign bits or not doesn't matter.

Also use ineg and not to shorten the patterns.

Diff Detail

Event Timeline

craig.topper created this revision.Nov 2 2020, 9:58 PM
Herald added a project: Restricted Project. · View Herald TranscriptNov 2 2020, 9:58 PM
craig.topper requested review of this revision.Nov 2 2020, 9:58 PM
This revision is now accepted and ready to land.Nov 4 2020, 6:58 AM
This revision was landed with ongoing or failed builds.Nov 4 2020, 10:35 AM
This revision was automatically updated to reflect the committed changes.