[RISCV] Make SelectRORIW handle the commutability of OR.

[craig.topper]

Summary

The SHL and SRL could be in opposite order so account for that.

[frasercrmck]

LGTM.

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

 // and VC3 a 32 bit mask of (32 - VC1) leading ones.
 
 bool RISCVDAGToDAGISel::SelectRORIW(SDValue N, SDValue &RS1, SDValue &Shamt) {
   if (N.getOpcode() == ISD::SIGN_EXTEND_INREG &&
       Subtarget->getXLenVT() == MVT::i64 &&
       cast<VTSDNode>(N.getOperand(1))->getVT() == MVT::i32) {
     if (N.getOperand(0).getOpcode() == ISD::OR) {
       SDValue Or = N.getOperand(0);
-      if (Or.getOperand(0).getOpcode() == ISD::SHL &&
-          Or.getOperand(1).getOpcode() == ISD::SRL) {
-        SDValue Shl = Or.getOperand(0);
-        SDValue Srl = Or.getOperand(1);
+
+      // OR is commutable so canonicalize SHL to LHS.
+      if (Srl.getOpcode() == ISD::SHL)
+        std::swap(Shl, Srl);
+
+      if (Shl.getOpcode() == ISD::SHL && Srl.getOpcode() == ISD::SRL) {
         if (Srl.getOperand(0).getOpcode() == ISD::AND) {
           SDValue And = Srl.getOperand(0);
           if (And.getOperand(0) == Shl.getOperand(0) &&
               isa<ConstantSDNode>(Srl.getOperand(1)) &&
               isa<ConstantSDNode>(Shl.getOperand(1)) &&
               isa<ConstantSDNode>(And.getOperand(1))) {
             uint32_t VC1 = Srl.getConstantOperandVal(1);
             uint32_t VC2 = Shl.getConstantOperandVal(1);

llvm/test/CodeGen/RISCV/rv64Zbbp.ll

 ; RV64I-NEXT:    slli a1, a0, 1
 ; RV64I-NEXT:    srliw a0, a0, 31
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: rori_i32_fshr:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    slli a1, a0, 1
-; RV64IB-NEXT:    srliw a0, a0, 31
-; RV64IB-NEXT:    or a0, a0, a1
-; RV64IB-NEXT:    sext.w a0, a0
+; RV64IB-NEXT:    roriw a0, a0, 31
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBB-LABEL: rori_i32_fshr:
 ; RV64IBB:       # %bb.0:
-; RV64IBB-NEXT:    slli a1, a0, 1
-; RV64IBB-NEXT:    srliw a0, a0, 31
-; RV64IBB-NEXT:    or a0, a0, a1
-; RV64IBB-NEXT:    sext.w a0, a0
+; RV64IBB-NEXT:    roriw a0, a0, 31
 ; RV64IBB-NEXT:    ret
 ;
 ; RV64IBP-LABEL: rori_i32_fshr:
 ; RV64IBP:       # %bb.0:
-; RV64IBP-NEXT:    slli a1, a0, 1
-; RV64IBP-NEXT:    srliw a0, a0, 31
-; RV64IBP-NEXT:    or a0, a0, a1
-; RV64IBP-NEXT:    sext.w a0, a0
+; RV64IBP-NEXT:    roriw a0, a0, 31
 ; RV64IBP-NEXT:    ret
   %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 31)
   ret i32 %1
 }
 
 ; This test is similar to the type legalized version of the fshl/fshr tests, but
 ; instead of having the same input to both shifts it has different inputs. Make
 ; sure we don't match it as a roriw.