[RISCV] Check all 64-bits of the mask in SelectRORIW.

[craig.topper]

Summary

We need to ensure the upper 32 bits of the mask need to be zero.
So that the srl shifts zeroes into the lower 32 bits.

[luismarques]

Overall LGTM. See inline comment before committing.

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

436

Shouldn't this be updated too?

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

 //===-- RISCVISelDAGToDAG.cpp - A dag to dag inst selector for RISCV ------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //

 // We first check that it is the right node tree:
 //
 //  (SIGN_EXTEND_INREG (OR (SHL (AsserSext RS1, i32), VC2),
 //                         (SRL (AND (AssertSext RS2, i32), VC3), VC1)))
 //
 // Then we check that the constant operands respect these constraints:
 //
 // VC2 == 32 - VC1
 // VC3 == maskLeadingOnes<uint32_t>(VC2)
 //
 // being VC1 the Shamt we need, VC2 the complementary of Shamt over 32
 // and VC3 a 32 bit mask of (32 - VC1) leading ones.
 
 bool RISCVDAGToDAGISel::SelectRORIW(SDValue N, SDValue &RS1, SDValue &Shamt) {
   if (N.getOpcode() == ISD::SIGN_EXTEND_INREG &&
       Subtarget->getXLenVT() == MVT::i64 &&
       cast<VTSDNode>(N.getOperand(1))->getVT() == MVT::i32) {
     if (N.getOperand(0).getOpcode() == ISD::OR) {
       SDValue Or = N.getOperand(0);
       if (Or.getOperand(0).getOpcode() == ISD::SHL &&
           Or.getOperand(1).getOpcode() == ISD::SRL) {
         SDValue Shl = Or.getOperand(0);
         SDValue Srl = Or.getOperand(1);
         if (Srl.getOperand(0).getOpcode() == ISD::AND) {
           SDValue And = Srl.getOperand(0);
           if (And.getOperand(0) == Shl.getOperand(0) &&
               isa<ConstantSDNode>(Srl.getOperand(1)) &&
               isa<ConstantSDNode>(Shl.getOperand(1)) &&
               isa<ConstantSDNode>(And.getOperand(1))) {
-            uint32_t VC1 = Srl.getConstantOperandVal(1);
-            uint32_t VC2 = Shl.getConstantOperandVal(1);
-            uint32_t VC3 = And.getConstantOperandVal(1);
+            uint64_t VC1 = Srl.getConstantOperandVal(1);
+            uint64_t VC2 = Shl.getConstantOperandVal(1);
+            uint64_t VC3 = And.getConstantOperandVal(1);
+            // The mask needs to be 0xffffffff, but SimplifyDemandedBits may
+            // have removed lower bits that aren't necessary due to the right
+            // shift.
             if (VC2 == (32 - VC1) &&
-                VC3 == maskLeadingOnes<uint32_t>(VC2)) {
+                (VC3 | maskTrailingOnes<uint64_t>(VC1)) == 0xffffffff) {
               RS1 = Shl.getOperand(0);
               Shamt = CurDAG->getTargetConstant(VC1, SDLoc(N),
                                               Srl.getOperand(1).getValueType());
               return true;
             }
           }
         }
       }

llvm/test/CodeGen/RISCV/rv64Zbbp.ll

; RV64IBP-NEXT:    ret
   %b = lshr i32 %y, 1
   %c = or i32 %a, %b
   ret i32 %c
 }
 
 ; This is similar to the type legalized roriw pattern, but the and mask is more
 ; than 32 bits so the lshr doesn't shift zeroes into the lower 32 bits. Make
 ; sure we don't match it to roriw.
-; FIXME: We are currently truncating the mask to 32-bits before checking.
 define i64 @roriw_bug(i64 %x) nounwind {
 ; RV64I-LABEL: roriw_bug:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a1, a0, 31
 ; RV64I-NEXT:    andi a0, a0, -2
 ; RV64I-NEXT:    srli a2, a0, 1
 ; RV64I-NEXT:    or a1, a1, a2
 ; RV64I-NEXT:    sext.w a1, a1
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: roriw_bug:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    andi a1, a0, -2
-; RV64IB-NEXT:    roriw a0, a0, 1
-; RV64IB-NEXT:    xor a0, a1, a0
+; RV64IB-NEXT:    slli a1, a0, 31
+; RV64IB-NEXT:    andi a0, a0, -2
+; RV64IB-NEXT:    srli a2, a0, 1
+; RV64IB-NEXT:    or a1, a1, a2
+; RV64IB-NEXT:    sext.w a1, a1
+; RV64IB-NEXT:    xor a0, a0, a1
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBB-LABEL: roriw_bug:
 ; RV64IBB:       # %bb.0:
-; RV64IBB-NEXT:    andi a1, a0, -2
-; RV64IBB-NEXT:    roriw a0, a0, 1
-; RV64IBB-NEXT:    xor a0, a1, a0
+; RV64IBB-NEXT:    slli a1, a0, 31
+; RV64IBB-NEXT:    andi a0, a0, -2
+; RV64IBB-NEXT:    srli a2, a0, 1
+; RV64IBB-NEXT:    or a1, a1, a2
+; RV64IBB-NEXT:    sext.w a1, a1
+; RV64IBB-NEXT:    xor a0, a0, a1
 ; RV64IBB-NEXT:    ret
 ;
 ; RV64IBP-LABEL: roriw_bug:
 ; RV64IBP:       # %bb.0:
-; RV64IBP-NEXT:    andi a1, a0, -2
-; RV64IBP-NEXT:    roriw a0, a0, 1
-; RV64IBP-NEXT:    xor a0, a1, a0
+; RV64IBP-NEXT:    slli a1, a0, 31
+; RV64IBP-NEXT:    andi a0, a0, -2
+; RV64IBP-NEXT:    srli a2, a0, 1
+; RV64IBP-NEXT:    or a1, a1, a2
+; RV64IBP-NEXT:    sext.w a1, a1
+; RV64IBP-NEXT:    xor a0, a0, a1
 ; RV64IBP-NEXT:    ret
   %a = shl i64 %x, 31
   %b = and i64 %x, 18446744073709551614
   %c = lshr i64 %b, 1
   %d = or i64 %a, %c
   %e = shl i64 %d, 32
   %f = ashr i64 %e, 32
   %g = xor i64 %b, %f ; to increase the use count on %b to disable SimplifyDemandedBits.