[RISCV] When matching RORIW, make sure the same input is given to both shifts.

[craig.topper]

Summary

The code is looking for (sext_inreg (or (shl X, C2), (shr (and Y, C3), C1))).
We need to ensure X and Y are the same.

[frasercrmck]

The comment at the top of SelectRORIW says

//  (SIGN_EXTEND_INREG (OR (SHL (AsserSext RS1, i32), VC2),
//                         (SRL (AND (AssertSext RS2, i32), VC3), VC1)))

should it make it apparent that RS1 must equal RS2?

LGTM otherwise.

llvm/test/CodeGen/RISCV/rv64Zbbp.ll

346

You could fix up the typo versio here, and has a roriw below.

[luismarques]

LGTM. Good nitpicking feedback by @frasercrmck! :-)

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

 //===-- RISCVISelDAGToDAG.cpp - A dag to dag inst selector for RISCV ------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (N.getOpcode() == ISD::SIGN_EXTEND_INREG &&
     if (N.getOperand(0).getOpcode() == ISD::OR) {
       SDValue Or = N.getOperand(0);
       if (Or.getOperand(0).getOpcode() == ISD::SHL &&
           Or.getOperand(1).getOpcode() == ISD::SRL) {
         SDValue Shl = Or.getOperand(0);
         SDValue Srl = Or.getOperand(1);
         if (Srl.getOperand(0).getOpcode() == ISD::AND) {
           SDValue And = Srl.getOperand(0);
-          if (isa<ConstantSDNode>(Srl.getOperand(1)) &&
+          if (And.getOperand(0) == Shl.getOperand(0) &&
+              isa<ConstantSDNode>(Srl.getOperand(1)) &&
               isa<ConstantSDNode>(Shl.getOperand(1)) &&
               isa<ConstantSDNode>(And.getOperand(1))) {
             uint32_t VC1 = Srl.getConstantOperandVal(1);
             uint32_t VC2 = Shl.getConstantOperandVal(1);
             uint32_t VC3 = And.getConstantOperandVal(1);
             if (VC2 == (32 - VC1) &&
                 VC3 == maskLeadingOnes<uint32_t>(VC2)) {
               RS1 = Shl.getOperand(0);

llvm/test/CodeGen/RISCV/rv64Zbbp.ll

 ; RV64IBP-NEXT:    srliw a0, a0, 31
 ; RV64IBP-NEXT:    or a0, a0, a1
 ; RV64IBP-NEXT:    sext.w a0, a0
 ; RV64IBP-NEXT:    ret
   %1 = tail call i32 @llvm.fshr.i32(i32 %a, i32 %a, i32 31)
   ret i32 %1
 }
 
 ; This test is similar to the type legalized versio of the fshl/fshr tests, but
 ; instead of having the same input to both shifts it has different inputs. Make
 ; sure we don't match it has a roriw.
-; FIXME: We're currently missing a check that the inputs are the same.
 define signext i32 @not_rori_i32(i32 signext %x, i32 signext %y) nounwind {
 ; RV64I-LABEL: not_rori_i32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a0, a0, 31
 ; RV64I-NEXT:    srliw a1, a1, 1
 ; RV64I-NEXT:    or a0, a0, a1
 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IB-LABEL: not_rori_i32:
 ; RV64IB:       # %bb.0:
-; RV64IB-NEXT:    roriw a0, a0, 1
+; RV64IB-NEXT:    slli a0, a0, 31
+; RV64IB-NEXT:    srliw a1, a1, 1
+; RV64IB-NEXT:    or a0, a0, a1
+; RV64IB-NEXT:    sext.w a0, a0
 ; RV64IB-NEXT:    ret
 ;
 ; RV64IBB-LABEL: not_rori_i32:
 ; RV64IBB:       # %bb.0:
-; RV64IBB-NEXT:    roriw a0, a0, 1
+; RV64IBB-NEXT:    slli a0, a0, 31
+; RV64IBB-NEXT:    srliw a1, a1, 1
+; RV64IBB-NEXT:    or a0, a0, a1
+; RV64IBB-NEXT:    sext.w a0, a0
 ; RV64IBB-NEXT:    ret
 ;
 ; RV64IBP-LABEL: not_rori_i32:
 ; RV64IBP:       # %bb.0:
-; RV64IBP-NEXT:    roriw a0, a0, 1
+; RV64IBP-NEXT:    slli a0, a0, 31
+; RV64IBP-NEXT:    srliw a1, a1, 1
+; RV64IBP-NEXT:    or a0, a0, a1
+; RV64IBP-NEXT:    sext.w a0, a0
 ; RV64IBP-NEXT:    ret
   %a = shl i32 %x, 31
   %b = lshr i32 %y, 1
   %c = or i32 %a, %b
   ret i32 %c
 }
 
 define i64 @rori_i64_fshl(i64 %a) nounwind {