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[RISCV] When matching RORIW, make sure the same input is given to both shifts.
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Authored by craig.topper on Nov 1 2020, 9:55 PM.

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Summary

The code is looking for (sext_inreg (or (shl X, C2), (shr (and Y, C3), C1))).
We need to ensure X and Y are the same.

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craig.topper created this revision.Nov 1 2020, 9:55 PM
Herald added a project: Restricted Project. · View Herald TranscriptNov 1 2020, 9:55 PM
craig.topper requested review of this revision.Nov 1 2020, 9:55 PM

The comment at the top of SelectRORIW says

//  (SIGN_EXTEND_INREG (OR (SHL (AsserSext RS1, i32), VC2),
//                         (SRL (AND (AssertSext RS2, i32), VC3), VC1)))

should it make it apparent that RS1 must equal RS2?

LGTM otherwise.

llvm/test/CodeGen/RISCV/rv64Zbbp.ll
346

You could fix up the typo versio here, and has a roriw below.

luismarques accepted this revision.Nov 2 2020, 3:33 AM

LGTM. Good nitpicking feedback by @frasercrmck! :-)

This revision is now accepted and ready to land.Nov 2 2020, 3:33 AM
This revision was landed with ongoing or failed builds.Nov 2 2020, 9:14 AM
This revision was automatically updated to reflect the committed changes.