[RISCV] Remove include of RISCVRegisterInfo.h from RISCVBaseInfo.h

[craig.topper]

Summary

RISCVRegisterInfo.h is part of the CodeGen layer. The Utils library is intended to be shared with the MC layer so shouldn't use files from the CodeGen layer.

The register enum names are already available from RISCVMCTargetDesc.h. It appears what was coming from this include was a transitive include of the Register class which I've replaced with MCRegister. Register has a constructor from MCRegister so it should be convertible.

[HsiangKai]

LGTM.

[craig.topper]

Forgot to put the Differential Revision tag. This was commited as rG22c38376345670c1883963e5e1cccd597a15b3a5

[RKSimon]

@craig.topper This is causing a MSVC build failure in RISCVTargetLowering::getRegForInlineAsmConstraint

if (Subtarget.hasStdExtF() || Subtarget.hasStdExtD()) {
  std::pair<Register, Register> FReg =
      StringSwitch<std::pair<Register, Register>>(Constraint.lower())
          .Cases("{f0}", "{ft0}", {RISCV::F0_F, RISCV::F0_D})
          .Cases("{f1}", "{ft1}", {RISCV::F1_F, RISCV::F1_D})

with this build failure:

E:\llvm\llvm-project\llvm\include\llvm/Support/type_traits.h(180): error C2338: inconsistent behavior between llvm:: and std:: implementation of is_trivially_copyable
E:\llvm\llvm-project\llvm\include\llvm/ADT/Optional.h(216): note: see reference to class template instantiation 'llvm::is_trivially_copyable<T>' being compiled
        with
        [
            T=std::pair<llvm::Register,llvm::Register>
        ]
E:\llvm\llvm-project\llvm\include\llvm/ADT/StringSwitch.h(48): note: see reference to class template instantiation 'llvm::Optional<T>' being compiled
        with
        [
            T=std::pair<llvm::Register,llvm::Register>
        ]
E:\llvm\llvm-project\llvm\lib\Target\RISCV\RISCVISelLowering.cpp(2725): note: see reference to class template instantiation 'llvm::StringSwitch<std::pair<llvm::Register,llvm::Register>,T>' being compiled
        with
        [
            T=std::pair<llvm::Register,llvm::Register>
        ]
E:\llvm\llvm-project\llvm\include\llvm/ADT/Optional.h(216): error C2976: 'llvm::optional_detail::OptionalStorage': too few template arguments
E:\llvm\llvm-project\llvm\include\llvm/ADT/Optional.h(36): note: see declaration of 'llvm::optional_detail::OptionalStorage'

[RKSimon]

It looks like this only happens on my EXPENSIVE_CHECKS MSVC (vs2019) build

[RKSimon]

D86126 might solve this

[craig.topper]

In D90322#2364239, @RKSimon wrote:

@craig.topper This is causing a MSVC build failure in RISCVTargetLowering::getRegForInlineAsmConstraint

if (Subtarget.hasStdExtF() || Subtarget.hasStdExtD()) {
  std::pair<Register, Register> FReg =
      StringSwitch<std::pair<Register, Register>>(Constraint.lower())
          .Cases("{f0}", "{ft0}", {RISCV::F0_F, RISCV::F0_D})
          .Cases("{f1}", "{ft1}", {RISCV::F1_F, RISCV::F1_D})

with this build failure:

E:\llvm\llvm-project\llvm\include\llvm/Support/type_traits.h(180): error C2338: inconsistent behavior between llvm:: and std:: implementation of is_trivially_copyable
E:\llvm\llvm-project\llvm\include\llvm/ADT/Optional.h(216): note: see reference to class template instantiation 'llvm::is_trivially_copyable<T>' being compiled
        with
        [
            T=std::pair<llvm::Register,llvm::Register>
        ]
E:\llvm\llvm-project\llvm\include\llvm/ADT/StringSwitch.h(48): note: see reference to class template instantiation 'llvm::Optional<T>' being compiled
        with
        [
            T=std::pair<llvm::Register,llvm::Register>
        ]
E:\llvm\llvm-project\llvm\lib\Target\RISCV\RISCVISelLowering.cpp(2725): note: see reference to class template instantiation 'llvm::StringSwitch<std::pair<llvm::Register,llvm::Register>,T>' being compiled
        with
        [
            T=std::pair<llvm::Register,llvm::Register>
        ]
E:\llvm\llvm-project\llvm\include\llvm/ADT/Optional.h(216): error C2976: 'llvm::optional_detail::OptionalStorage': too few template arguments
E:\llvm\llvm-project\llvm\include\llvm/ADT/Optional.h(36): note: see declaration of 'llvm::optional_detail::OptionalStorage'

I'm having trouble finding the connect to my patch. RISCVISelLowering.cpp has its own include of RISCVRegisterInfo.h. And it doesn't appear to call either getSCSPReg() or getBPReg().

Does using unsigned instead of Register in getRegForInlineAsmConstraint fix it? The Register from the std::pair is turned back into an unsigned for the return value of the function anyway.

llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h

 //===-- RISCVBaseInfo.h - Top level definitions for RISCV MC ----*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file contains small standalone enum definitions for the RISCV target
 // useful for the compiler back-end and the MC libraries.
 //
 //===----------------------------------------------------------------------===//
 #ifndef LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
 #define LLVM_LIB_TARGET_RISCV_MCTARGETDESC_RISCVBASEINFO_H
 
-#include "RISCVRegisterInfo.h"
 #include "MCTargetDesc/RISCVMCTargetDesc.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/ADT/StringSwitch.h"
 #include "llvm/MC/MCInstrDesc.h"
 #include "llvm/MC/SubtargetFeature.h"
 
 namespace llvm {
 

 // Returns the target ABI, or else a StringError if the requested ABIName is
 // not supported for the given TT and FeatureBits combination.
 ABI computeTargetABI(const Triple &TT, FeatureBitset FeatureBits,
                      StringRef ABIName);
 
 ABI getTargetABI(StringRef ABIName);
 
 // Returns the register used to hold the stack pointer after realignment.
-Register getBPReg();
+MCRegister getBPReg();
 
 // Returns the register holding shadow call stack pointer.
-Register getSCSPReg();
+MCRegister getSCSPReg();
 
 } // namespace RISCVABI
 
 namespace RISCVFeatures {
 
 // Validates if the given combination of features are valid for the target
 // triple. Exits with report_fatal_error if not.
 void validate(const Triple &TT, const FeatureBitset &FeatureBits);
 
 } // namespace RISCVFeatures
 
 } // namespace llvm
 
 #endif

llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.cpp

auto TargetABI = StringSwitch<ABI>(ABIName)
                        .Case("lp64d", ABI_LP64D)
                        .Default(ABI_Unknown);
   return TargetABI;
 }
 
 // To avoid the BP value clobbered by a function call, we need to choose a
 // callee saved register to save the value. RV32E only has X8 and X9 as callee
 // saved registers and X8 will be used as fp. So we choose X9 as bp.
-Register getBPReg() { return RISCV::X9; }
+MCRegister getBPReg() { return RISCV::X9; }
 
 // Returns the register holding shadow call stack pointer.
-Register getSCSPReg() { return RISCV::X18; }
+MCRegister getSCSPReg() { return RISCV::X18; }
 
 } // namespace RISCVABI
 
 namespace RISCVFeatures {
 
 void validate(const Triple &TT, const FeatureBitset &FeatureBits) {
   if (TT.isArch64Bit() && FeatureBits[RISCV::FeatureRV32E])
     report_fatal_error("RV32E can't be enabled for an RV64 target");
 }
 
 } // namespace RISCVFeatures
 
 } // namespace llvm