[DebugInfo][InstrRef][4/4] Support using DBG_INSTR_REF through all* backend passes

[jmorse]

Summary

This patch does some cleanup to ensure that a clang stage2 build succeeds when using only DBG_INSTR_REF variable locations (plus the exceptions noted in the previous patch). There are still passes that will need updating, however most variable locations now survive most passes.

The most significant change is in LiveDebugVariables: because there are no DBG_VALUEs referring to virtual registers (which is now asserted), we can get away with just unlinking debug instructions from blocks, then linking them back in after regalloc finishes. This avoids the interval splitting and other operations. Debug instructions are stored with their slot and block, then re-inserted in the order they were removed.

Other passes need a tweak or two to correctly identify debug instructions now that DBG_PHIs can be generated during SelectionDAG.

Parameter variable locations are emitted by directly constructing a DBG_VALUE to be inserted later during SelectionDAGBuilder; I've added a helper lambda there to emit a DBG_INSTR_REF when we're using instruction referencing.

X86InstrInfo.cpp needs to un-set an instruction number: X86 usually creates subtract instructions instead of CMPs, then mutates them to be CMPs later on if no-one uses the result. That causes any debug users referring to the subs register def to now refer to a register use; which is an erronous behaviour.

Finally, I've deleted a bunch of DBG_VALUE %vreg's from the tests for other instruction referencing behaviour: they shouldn't be generated by SelectionDAG now, and shouldn't be in test cases for instruction referencing. None of them affect the tested behaviours, those all involve DBG_INSTR_REFs.

[djtodoro]

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

5518

MIB.addReg(Reg, RegState::Debug);

[Orlando]

Hi,

Full disclosure: I've not looked at the instruction-referencing work for a little while and I don't remember all the details of the full patch-set. That said, I think this patch LGTM by itself.

I've left some comments inline and there is an inline comment from @djtodoro. Does anyone else have any comments (and should this patch have some reviewers assigned to it)? If not I will tentatively accept this soon.

Thanks,
Orlando

llvm/lib/CodeGen/LiveDebugVariables.cpp

1893–1894

nit: maybe it's just me but "insert in front of it" feels a bit ambiguous in this scenario, perhaps "insert before it" is clearer?

1903

nit: putting the declaration in the if feels better to me, but it doesn't really matter much.

if (MachineInstr *Pos = Slots->getInstructionFromIndex(Idx)) {

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

5705

Shouldn't the MakeVRegDbgValue parameter Indirect here be IsIndirect rather than IsDbgDeclare, or are IsIndirect and IsDbgDeclare equivalent at this point? I'm just looking at the removed code in the diff so could be missing something.

llvm/lib/Target/X86/X86InstrInfo.cpp

4186

Is this covered by any of the tests?

[jmorse]

Revisions:

• Adjusted LiveDebugVariables to handle DBG_VALUE_LISTs in the "normal" way under instruction referencing, we don't attempt currently handle them with instr-ref right now
• Fixed up an "isIndirect" issue, see inline comments
• Added a test for SUB -> CMP peephole optimisation.

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

5705

I think this hinged on an assumption that I made in the past, that DbgDeclares only ever pointed at memory operands or something. That assumption turned out to be false, there was an assertion left hanging that D101594 cleared up.

Switched to passing IsIndirect in for all these things.

llvm/lib/Target/X86/X86InstrInfo.cpp

4186

Added x86-drop-compare-inst.mir to cover this.

[jmorse]

Shoe-horn in a collection of tiny adjustments: in register coalescing and liveintervals I've switched a few "isDebugValue" tests to be "isDebugInstr" instead. In all the modified cases, the code is seeking to avoid interpreting debug instructions or debug uses of a register -- I don't believe it matters whether it's a DBG_VALUE, DBG_VALUE_LIST, or DBG_PHI. Making these tests agnostic as to the instruction kind protects against codegen-changes-with-debugging-enabled.

[Orlando]

LGTM, thanks.

llvm/lib/CodeGen/LiveDebugVariables.cpp

 #include "llvm/CodeGen/LiveIntervals.h"
 #include "llvm/CodeGen/MachineBasicBlock.h"
 #include "llvm/CodeGen/MachineDominators.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineOperand.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/Passes.h"
 #include "llvm/CodeGen/SlotIndexes.h"
 #include "llvm/CodeGen/TargetInstrInfo.h"
 #include "llvm/CodeGen/TargetOpcodes.h"
+#include "llvm/CodeGen/TargetPassConfig.h"
 #include "llvm/CodeGen/TargetRegisterInfo.h"
 #include "llvm/CodeGen/TargetSubtargetInfo.h"
 #include "llvm/CodeGen/VirtRegMap.h"
 #include "llvm/Config/llvm-config.h"
 #include "llvm/IR/DebugInfoMetadata.h"
 #include "llvm/IR/DebugLoc.h"
 #include "llvm/IR/Function.h"
 #include "llvm/IR/Metadata.h"
 #include "llvm/InitializePasses.h"
 #include "llvm/MC/MCRegisterInfo.h"
 #include "llvm/Pass.h"
 #include "llvm/Support/Casting.h"
 #include "llvm/Support/CommandLine.h"
 #include "llvm/Support/Debug.h"
 #include "llvm/Support/raw_ostream.h"
+#include "llvm/Target/TargetMachine.h"
 #include <algorithm>
 #include <cassert>
 #include <iterator>
 #include <memory>
 #include <utility>
 
 using namespace llvm;
 

 /// Implementation of the LiveDebugVariables pass.
 class LDVImpl {
   LiveDebugVariables &pass;
   LocMap::Allocator allocator;
   MachineFunction *MF = nullptr;
   LiveIntervals *LIS;
   const TargetRegisterInfo *TRI;
 
-  using StashedInstrRef =
-      std::tuple<unsigned, unsigned, const DILocalVariable *,
-                 const DIExpression *, DebugLoc>;
-
   /// Position and VReg of a PHI instruction during register allocation.
   struct PHIValPos {
     SlotIndex SI;    /// Slot where this PHI occurs.
     Register Reg;    /// VReg this PHI occurs in.
     unsigned SubReg; /// Qualifiying subregister for Reg.
   };
 
   /// Map from debug instruction number to PHI position during allocation.
   std::map<unsigned, PHIValPos> PHIValToPos;
   /// Index of, for each VReg, which debug instruction numbers and corresponding
   /// PHIs are sensitive to splitting. Each VReg may have multiple PHI defs,
   /// at different positions.
   DenseMap<Register, std::vector<unsigned>> RegToPHIIdx;
 
-  std::map<SlotIndex, std::vector<StashedInstrRef>> StashedInstrReferences;
+  /// Record for any debug instructions unlinked from their blocks during
+  /// regalloc. Stores the instr and it's location, so that they can be
+  /// re-inserted after regalloc is over.
+  struct InstrPos {
+    MachineInstr *MI;       ///< Debug instruction, unlinked from it's block.
+    SlotIndex Idx;          ///< Slot position where MI should be re-inserted.
+    MachineBasicBlock *MBB; ///< Block that MI was in.
+  };
+
+  /// Collection of stored debug instructions, preserved until after regalloc.
+  SmallVector<InstrPos, 32> StashedDebugInstrs;
 
   /// Whether emitDebugValues is called.
   bool EmitDone = false;
 
   /// Whether the machine function is modified during the pass.
   bool ModifiedMF = false;
 
   /// All allocated UserValue instances.
class LDVImpl {
   /// Add DBG_VALUE instruction to our maps.
   ///
   /// \param MI DBG_VALUE instruction
   /// \param Idx Last valid SLotIndex before instruction.
   ///
   /// \returns True if the DBG_VALUE instruction should be deleted.
   bool handleDebugValue(MachineInstr &MI, SlotIndex Idx);
 
-  /// Track a DBG_INSTR_REF. This needs to be removed from the MachineFunction
-  /// during regalloc -- but there's no need to maintain live ranges, as we
-  /// refer to a value rather than a location.
+  /// Track variable location debug instructions while using the instruction
+  /// referencing implementation. Such debug instructions do not need to be
+  /// updated during regalloc because they identify instructions rather than
+  /// register locations. However, they needs to be removed from the
+  /// MachineFunction during regalloc, then re-inserted later, to avoid
+  /// disrupting the allocator.
   ///
-  /// \param MI DBG_INSTR_REF instruction
+  /// \param MI Any DBG_VALUE / DBG_INSTR_REF / DBG_PHI instruction
   /// \param Idx Last valid SlotIndex before instruction
   ///
-  /// \returns True if the DBG_VALUE instruction should be deleted.
-  bool handleDebugInstrRef(MachineInstr &MI, SlotIndex Idx);
+  /// \returns Iterator to continue processing from after unlinking.
+  MachineBasicBlock::iterator handleDebugInstr(MachineInstr &MI, SlotIndex Idx);
 
   /// Add DBG_LABEL instruction to UserLabel.
   ///
   /// \param MI DBG_LABEL instruction
   /// \param Idx Last valid SlotIndex before instruction.
   ///
   /// \returns True if the DBG_LABEL instruction should be deleted.
   bool handleDebugLabel(MachineInstr &MI, SlotIndex Idx);
 
   /// Collect and erase all DBG_VALUE instructions, adding a UserValue def
   /// for each instruction.
   ///
   /// \param mf MachineFunction to be scanned.
+  /// \param InstrRef Whether to operate in instruction referencing mode. If
+  ///        true, most of LiveDebugVariables doesn't run.
   ///
   /// \returns True if any debug values were found.
-  bool collectDebugValues(MachineFunction &mf);
+  bool collectDebugValues(MachineFunction &mf, bool InstrRef);
 
   /// Compute the live intervals of all user values after collecting all
   /// their def points.
   void computeIntervals();
 
 public:
   LDVImpl(LiveDebugVariables *ps) : pass(*ps) {}
 
-  bool runOnMachineFunction(MachineFunction &mf);
+  bool runOnMachineFunction(MachineFunction &mf, bool InstrRef);
 
   /// Release all memory.
   void clear() {
     MF = nullptr;
     PHIValToPos.clear();
     RegToPHIIdx.clear();
-    StashedInstrReferences.clear();
+    StashedDebugInstrs.clear();
     userValues.clear();
     userLabels.clear();
     virtRegToEqClass.clear();
     userVarMap.clear();
     // Make sure we call emitDebugValues if the machine function was modified.
     assert((!ModifiedMF || EmitDone) &&
            "Dbg values are not emitted in LDV");
     EmitDone = false;
else {
     // all MOs are undef, so that DbgVariableValue can correctly adjust the
     // expression while removing the duplicated undefs.
     SmallVector<MachineOperand, 4> UndefMOs(MI.getNumDebugOperands(), MO);
     UV->addDef(Idx, UndefMOs, false, IsList, *Expr);
   }
   return true;
 }
 
-bool LDVImpl::handleDebugInstrRef(MachineInstr &MI, SlotIndex Idx) {
-  assert(MI.isDebugRef());
-  unsigned InstrNum = MI.getOperand(0).getImm();
-  unsigned OperandNum = MI.getOperand(1).getImm();
-  auto *Var = MI.getDebugVariable();
-  auto *Expr = MI.getDebugExpression();
-  auto &DL = MI.getDebugLoc();
-  StashedInstrRef Stashed =
-      std::make_tuple(InstrNum, OperandNum, Var, Expr, DL);
-  StashedInstrReferences[Idx].push_back(Stashed);
-  return true;
+MachineBasicBlock::iterator LDVImpl::handleDebugInstr(MachineInstr &MI,
+                                                      SlotIndex Idx) {
+  assert(MI.isDebugValue() || MI.isDebugRef() || MI.isDebugPHI());
+
+  // In instruction referencing mode, there should be no DBG_VALUE instructions
+  // that refer to virtual registers. They might still refer to constants.
+  if (MI.isDebugValue())
+    assert(!MI.getOperand(0).isReg() || !MI.getOperand(0).getReg().isVirtual());
+
+  // Unlink the instruction, store it in the debug instructions collection.
+  auto NextInst = std::next(MI.getIterator());
+  auto *MBB = MI.getParent();
+  MI.removeFromParent();
+  StashedDebugInstrs.push_back({&MI, Idx, MBB});
+  return NextInst;
 }
 
 bool LDVImpl::handleDebugLabel(MachineInstr &MI, SlotIndex Idx) {
   // DBG_LABEL label
   if (MI.getNumOperands() != 1 || !MI.getOperand(0).isMetadata()) {
     LLVM_DEBUG(dbgs() << "Can't handle " << MI);
     return false;
   }
for (auto const &L : userLabels) {
     }
   }
   if (!Found)
     userLabels.push_back(std::make_unique<UserLabel>(Label, DL, Idx));
 
   return true;
 }
 
-bool LDVImpl::collectDebugValues(MachineFunction &mf) {
+bool LDVImpl::collectDebugValues(MachineFunction &mf, bool InstrRef) {
   bool Changed = false;
   for (MachineBasicBlock &MBB : mf) {
     for (MachineBasicBlock::iterator MBBI = MBB.begin(), MBBE = MBB.end();
          MBBI != MBBE;) {
       // Use the first debug instruction in the sequence to get a SlotIndex
       // for following consecutive debug instructions.
       if (!MBBI->isDebugOrPseudoInstr()) {
         ++MBBI;
         continue;
       }
       // Debug instructions has no slot index. Use the previous
       // non-debug instruction's SlotIndex as its SlotIndex.
       SlotIndex Idx =
           MBBI == MBB.begin()
               ? LIS->getMBBStartIdx(&MBB)
               : LIS->getInstructionIndex(*std::prev(MBBI)).getRegSlot();
       // Handle consecutive debug instructions with the same slot index.
       do {
-        // Only handle DBG_VALUE in handleDebugValue(). Skip all other
-        // kinds of debug instructions.
-        if ((MBBI->isDebugValue() && handleDebugValue(*MBBI, Idx)) ||
-            (MBBI->isDebugRef() && handleDebugInstrRef(*MBBI, Idx)) ||
+        // In instruction referencing mode, pass each instr to handleDebugInstr
+        // to be unlinked. Ignore DBG_VALUE_LISTs -- they refer to vregs, and
+        // need to go through the normal live interval splitting process.
+        if (InstrRef && (MBBI->isNonListDebugValue() || MBBI->isDebugPHI() ||
+                         MBBI->isDebugRef())) {
+          MBBI = handleDebugInstr(*MBBI, Idx);
+          Changed = true;
+        // In normal debug mode, use the dedicated DBG_VALUE / DBG_LABEL handler
+        // to track things through register allocation, and erase the instr.
+        } else if ((MBBI->isDebugValue() && handleDebugValue(*MBBI, Idx)) ||
                    (MBBI->isDebugLabel() && handleDebugLabel(*MBBI, Idx))) {
           MBBI = MBB.erase(MBBI);
           Changed = true;
         } else
           ++MBBI;
       } while (MBBI != MBBE && MBBI->isDebugOrPseudoInstr());
     }
   }
   return Changed;
void LDVImpl::computeIntervals() {
   LS.initialize(*MF);
 
   for (unsigned i = 0, e = userValues.size(); i != e; ++i) {
     userValues[i]->computeIntervals(MF->getRegInfo(), *TRI, *LIS, LS);
     userValues[i]->mapVirtRegs(this);
   }
 }
 
-bool LDVImpl::runOnMachineFunction(MachineFunction &mf) {
+bool LDVImpl::runOnMachineFunction(MachineFunction &mf, bool InstrRef) {
   clear();
   MF = &mf;
   LIS = &pass.getAnalysis<LiveIntervals>();
   TRI = mf.getSubtarget().getRegisterInfo();
   LLVM_DEBUG(dbgs() << "********** COMPUTING LIVE DEBUG VARIABLES: "
                     << mf.getName() << " **********\n");
 
-  bool Changed = collectDebugValues(mf);
+  bool Changed = collectDebugValues(mf, InstrRef);
   computeIntervals();
   LLVM_DEBUG(print(dbgs()));
 
   // Collect the set of VReg / SlotIndexs where PHIs occur; index the sensitive
   // VRegs too, for when we're notified of a range split.
   SlotIndexes *Slots = LIS->getSlotIndexes();
   for (const auto &PHIIt : MF->DebugPHIPositions) {
     const MachineFunction::DebugPHIRegallocPos &Position = PHIIt.second;

 
 bool LiveDebugVariables::runOnMachineFunction(MachineFunction &mf) {
   if (!EnableLDV)
     return false;
   if (!mf.getFunction().getSubprogram()) {
     removeDebugInstrs(mf);
     return false;
   }
+
+  // Have we been asked to track variable locations using instruction
+  // referencing?
+  bool InstrRef = false;
+  auto *TPC = getAnalysisIfAvailable<TargetPassConfig>();
+  if (TPC) {
+    auto &TM = TPC->getTM<TargetMachine>();
+    InstrRef = TM.Options.ValueTrackingVariableLocations;
+  }
+
   if (!pImpl)
     pImpl = new LDVImpl(this);
-  return static_cast<LDVImpl*>(pImpl)->runOnMachineFunction(mf);
+  return static_cast<LDVImpl *>(pImpl)->runOnMachineFunction(mf, InstrRef);
 }
 
 void LiveDebugVariables::releaseMemory() {
   if (pImpl)
     static_cast<LDVImpl*>(pImpl)->clear();
 }
 
 LiveDebugVariables::~LiveDebugVariables() {
for (auto &It : PHIValToPos) {
     }
     // If there was no mapping for a value ID, it's optimized out. Create no
     // DBG_PHI, and any variables using this value will become optimized out.
   }
   MF->DebugPHIPositions.clear();
 
   LLVM_DEBUG(dbgs() << "********** EMITTING INSTR REFERENCES **********\n");
 
-  // Re-insert any DBG_INSTR_REFs back in the position they were. Ordering
-  // is preserved by vector.
-  const MCInstrDesc &RefII = TII->get(TargetOpcode::DBG_INSTR_REF);
-  for (auto &P : StashedInstrReferences) {
-    const SlotIndex &Idx = P.first;
-    auto *MBB = Slots->getMBBFromIndex(Idx);
-    MachineBasicBlock::iterator insertPos =
-        findInsertLocation(MBB, Idx, *LIS, BBSkipInstsMap);
-    for (auto &Stashed : P.second) {
-      auto MIB = BuildMI(*MF, std::get<4>(Stashed), RefII);
-      MIB.addImm(std::get<0>(Stashed));
-      MIB.addImm(std::get<1>(Stashed));
-      MIB.addMetadata(std::get<2>(Stashed));
-      MIB.addMetadata(std::get<3>(Stashed));
-      MachineInstr *New = MIB;
-      MBB->insert(insertPos, New);
+  // Re-insert any debug instrs back in the position they were. Ordering
+  // is preserved by vector. We must re-insert in the same order to ensure that
+  // debug instructions don't swap, which could re-order assignments.
+  for (auto &P : StashedDebugInstrs) {
+    SlotIndex Idx = P.Idx;
+
+    // Start block index: find the first non-debug instr in the block, and
+    // insert before it.
+    if (Idx == Slots->getMBBStartIdx(P.MBB)) {
+      MachineBasicBlock::iterator InsertPos =
+          findInsertLocation(P.MBB, Idx, *LIS, BBSkipInstsMap);
+      P.MBB->insert(InsertPos, P.MI);
+      continue;
+    }
+
+    if (MachineInstr *Pos = Slots->getInstructionFromIndex(Idx)) {
+      // Insert at the end of any debug instructions.
+      auto PostDebug = std::next(Pos->getIterator());
+      PostDebug = skipDebugInstructionsForward(PostDebug, P.MBB->instr_end());
+      P.MBB->insert(PostDebug, P.MI);
+    } else {
+      // Insert position disappeared; walk forwards through slots until we
+      // find a new one.
+      SlotIndex End = Slots->getMBBEndIdx(P.MBB);
+      for (; Idx < End; Idx = Slots->getNextNonNullIndex(Idx)) {
+        Pos = Slots->getInstructionFromIndex(Idx);
+        if (Pos) {
+          P.MBB->insert(Pos->getIterator(), P.MI);
+          break;
+        }
+      }
+
+      // We have reached the end of the block and didn't find anywhere to
+      // insert! It's not safe to discard any debug instructions; place them
+      // in front of the first terminator, or in front of end().
+      if (Idx >= End) {
+        auto TermIt = P.MBB->getFirstTerminator();
+        P.MBB->insert(TermIt, P.MI);
+      }
     }
   }
 
   EmitDone = true;
   BBSkipInstsMap.clear();
 }
 
 void LiveDebugVariables::emitDebugValues(VirtRegMap *VRM) {

llvm/lib/CodeGen/LiveIntervals.cpp

if (NeedsCleanup)
     li->removeEmptySubRanges();
 
   // Find all the values used, including PHI kills.
   ShrinkToUsesWorkList WorkList;
 
   // Visit all instructions reading li->reg().
   Register Reg = li->reg();
   for (MachineInstr &UseMI : MRI->reg_instructions(Reg)) {
-    if (UseMI.isDebugValue() || !UseMI.readsVirtualRegister(Reg))
+    if (UseMI.isDebugInstr() || !UseMI.readsVirtualRegister(Reg))
       continue;
     SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
     LiveQueryResult LRQ = li->Query(Idx);
     VNInfo *VNI = LRQ.valueIn();
     if (!VNI) {
       // This shouldn't happen: readsVirtualRegister returns true, but there is
       // no live value. It is likely caused by a target getting <undef> flags
       // wrong.

llvm/lib/CodeGen/MachineSink.cpp

MachineSinking::getBBRegisterPressure(MachineBasicBlock &MBB) {
   // Initialize the register pressure tracker.
   RPTracker.init(MBB.getParent(), &RegClassInfo, nullptr, &MBB, MBB.end(),
                  /*TrackLaneMasks*/ false, /*TrackUntiedDefs=*/true);
 
   for (MachineBasicBlock::iterator MII = MBB.instr_end(),
                                    MIE = MBB.instr_begin();
        MII != MIE; --MII) {
     MachineInstr &MI = *std::prev(MII);
-    if (MI.isDebugValue() || MI.isDebugLabel() || MI.isPseudoProbe())
+    if (MI.isDebugInstr() || MI.isPseudoProbe())
       continue;
     RegisterOperands RegOpers;
     RegOpers.collect(MI, *TRI, *MRI, false, false);
     RPTracker.recedeSkipDebugValues();
     assert(&*RPTracker.getPos() == &MI && "RPTracker sync error!");
     RPTracker.recede(RegOpers);
   }
 

llvm/lib/CodeGen/RegisterCoalescer.cpp

for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(IntA.reg()),
                                          UE = MRI->use_end();
        UI != UE;
        /* ++UI is below because of possible MI removal */) {
     MachineOperand &UseMO = *UI;
     ++UI;
     if (UseMO.isUndef())
       continue;
     MachineInstr *UseMI = UseMO.getParent();
-    if (UseMI->isDebugValue()) {
+    if (UseMI->isDebugInstr()) {
       // FIXME These don't have an instruction index.  Not clear we have enough
       // info to decide whether to do this replacement or not.  For now do it.
       UseMO.setReg(NewReg);
       continue;
     }
     SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI).getRegSlot(true);
     LiveInterval::iterator US = IntA.FindSegmentContaining(UseIdx);
     assert(US != IntA.end() && "Use must be live");
bool RegisterCoalescer::reMaterializeTrivialDef(const CoalescerPair &CP,
 
   // If the virtual SrcReg is completely eliminated, update all DBG_VALUEs
   // to describe DstReg instead.
   if (MRI->use_nodbg_empty(SrcReg)) {
     for (MachineRegisterInfo::use_iterator UI = MRI->use_begin(SrcReg);
          UI != MRI->use_end();) {
       MachineOperand &UseMO = *UI++;
       MachineInstr *UseMI = UseMO.getParent();
-      if (UseMI->isDebugValue()) {
+      if (UseMI->isDebugInstr()) {
         if (Register::isPhysicalRegister(DstReg))
           UseMO.substPhysReg(DstReg, *TRI);
         else
           UseMO.setReg(DstReg);
         // Move the debug value directly after the def of the rematerialized
         // value in DstReg.
         MBB->splice(std::next(NewMI.getIterator()), UseMI->getParent(), UseMI);
         LLVM_DEBUG(dbgs() << "\t\tupdated: " << *UseMI);
void RegisterCoalescer::updateRegDefsUses(Register SrcReg, Register DstReg,
   LiveInterval *DstInt = DstIsPhys ? nullptr : &LIS->getInterval(DstReg);
 
   if (DstInt && DstInt->hasSubRanges() && DstReg != SrcReg) {
     for (MachineOperand &MO : MRI->reg_operands(DstReg)) {
       unsigned SubReg = MO.getSubReg();
       if (SubReg == 0 || MO.isUndef())
         continue;
       MachineInstr &MI = *MO.getParent();
-      if (MI.isDebugValue())
+      if (MI.isDebugInstr())
         continue;
       SlotIndex UseIdx = LIS->getInstructionIndex(MI).getRegSlot(true);
       addUndefFlag(*DstInt, UseIdx, MO, SubReg);
     }
   }
 
   SmallPtrSet<MachineInstr*, 8> Visited;
   for (MachineRegisterInfo::reg_instr_iterator
if (SrcReg == DstReg && !Visited.insert(UseMI).second)
       continue;
 
     SmallVector<unsigned,8> Ops;
     bool Reads, Writes;
     std::tie(Reads, Writes) = UseMI->readsWritesVirtualRegister(SrcReg, &Ops);
 
     // If SrcReg wasn't read, it may still be the case that DstReg is live-in
     // because SrcReg is a sub-register.
-    if (DstInt && !Reads && SubIdx && !UseMI->isDebugValue())
+    if (DstInt && !Reads && SubIdx && !UseMI->isDebugInstr())
       Reads = DstInt->liveAt(LIS->getInstructionIndex(*UseMI));
 
     // Replace SrcReg with DstReg in all UseMI operands.
     for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
       MachineOperand &MO = UseMI->getOperand(Ops[i]);
 
       // Adjust <undef> flags in case of sub-register joins. We don't want to
       // turn a full def into a read-modify-write sub-register def and vice
for (unsigned i = 0, e = Ops.size(); i != e; ++i) {
             LaneBitmask UnusedLanes = FullMask & ~UsedLanes;
             DstInt->createSubRangeFrom(Allocator, UsedLanes, *DstInt);
             // The unused lanes are just empty live-ranges at this point.
             // It is the caller responsibility to set the proper
             // dead segments if there is an actual dead def of the
             // unused lanes. This may happen with rematerialization.
             DstInt->createSubRange(Allocator, UnusedLanes);
           }
-          SlotIndex MIIdx = UseMI->isDebugValue()
+          SlotIndex MIIdx = UseMI->isDebugInstr()
             ? LIS->getSlotIndexes()->getIndexBefore(*UseMI)
             : LIS->getInstructionIndex(*UseMI);
           SlotIndex UseIdx = MIIdx.getRegSlot(true);
           addUndefFlag(*DstInt, UseIdx, MO, SubUseIdx);
         }
       }
 
       if (DstIsPhys)
         MO.substPhysReg(DstReg, *TRI);
       else
         MO.substVirtReg(DstReg, SubIdx, *TRI);
     }
 
     LLVM_DEBUG({
       dbgs() << "\t\tupdated: ";
-      if (!UseMI->isDebugValue())
+      if (!UseMI->isDebugInstr())
         dbgs() << LIS->getInstructionIndex(*UseMI) << "\t";
       dbgs() << *UseMI;
     });
   }
 }
 
 bool RegisterCoalescer::canJoinPhys(const CoalescerPair &CP) {
   // Always join simple intervals that are defined by a single copy from a

llvm/lib/CodeGen/RegisterPressure.cpp

void RegPressureTracker::recedeSkipDebugValues() {
 
   // Open the top of the region using slot indexes.
   if (RequireIntervals && isTopClosed())
     static_cast<IntervalPressure&>(P).openTop(SlotIdx);
 }
 
 void RegPressureTracker::recede(SmallVectorImpl<RegisterMaskPair> *LiveUses) {
   recedeSkipDebugValues();
-  if (CurrPos->isDebugValue() || CurrPos->isPseudoProbe()) {
+  if (CurrPos->isDebugInstr() || CurrPos->isPseudoProbe()) {
     // It's possible to only have debug_value and pseudo probe instructions and
     // hit the start of the block.
     assert(CurrPos == MBB->begin());
     return;
   }
 
   const MachineInstr &MI = *CurrPos;
   RegisterOperands RegOpers;

llvm/lib/CodeGen/ScheduleDAGInstrs.cpp

void ScheduleDAGInstrs::buildSchedGraph(AAResults *AA,
   for (MachineBasicBlock::iterator MII = RegionEnd, MIE = RegionBegin;
        MII != MIE; --MII) {
     MachineInstr &MI = *std::prev(MII);
     if (DbgMI) {
       DbgValues.push_back(std::make_pair(DbgMI, &MI));
       DbgMI = nullptr;
     }
 
-    if (MI.isDebugValue() || MI.isDebugRef()) {
+    if (MI.isDebugValue() || MI.isDebugRef() || MI.isDebugPHI()) {
       DbgMI = &MI;
       continue;
     }
     if (MI.isDebugLabel())
       continue;
 
     if (MI.isPseudoProbe())
       continue;

llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

 /// appear for function arguments or in the prologue.
 bool SelectionDAGBuilder::EmitFuncArgumentDbgValue(
     const Value *V, DILocalVariable *Variable, DIExpression *Expr,
     DILocation *DL, bool IsDbgDeclare, const SDValue &N) {
   const Argument *Arg = dyn_cast<Argument>(V);
   if (!Arg)
     return false;
 
+  MachineFunction &MF = DAG.getMachineFunction();
+  const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
+
+  // Helper to create DBG_INSTR_REFs or DBG_VALUEs, depending on what kind
+  // we've been asked to pursue.
+  auto MakeVRegDbgValue = [&](Register Reg, DIExpression *FragExpr,
+                              bool Indirect) {
+    if (Reg.isVirtual() && TM.Options.ValueTrackingVariableLocations) {
+      // For VRegs, in instruction referencing mode, create a DBG_INSTR_REF
+      // pointing at the VReg, which will be patched up later.
+      auto &Inst = TII->get(TargetOpcode::DBG_INSTR_REF);
+      auto MIB = BuildMI(MF, DL, Inst);
+      MIB.addReg(Reg, RegState::Debug);
+      MIB.addImm(0);
+      MIB.addMetadata(Variable);
+      auto *NewDIExpr = FragExpr;
+      // We don't have an "Indirect" field in DBG_INSTR_REF, fold that into
+      // the DIExpression.
+      if (Indirect)
+        NewDIExpr = DIExpression::prepend(FragExpr, DIExpression::DerefBefore);
+      MIB.addMetadata(NewDIExpr);
+      return MIB;
+    } else {
+      // Create a completely standard DBG_VALUE.
+      auto &Inst = TII->get(TargetOpcode::DBG_VALUE);
+      return BuildMI(MF, DL, Inst, Indirect, Reg, Variable, FragExpr);
+    }
+  };
+
   if (!IsDbgDeclare) {
     // ArgDbgValues are hoisted to the beginning of the entry block. So we
     // should only emit as ArgDbgValue if the dbg.value intrinsic is found in
     // the entry block.
     bool IsInEntryBlock = FuncInfo.MBB == &FuncInfo.MF->front();
     if (!IsInEntryBlock)
       return false;
 
if (VariableIsFunctionInputArg) {
       if (ArgNo >= FuncInfo.DescribedArgs.size())
         FuncInfo.DescribedArgs.resize(ArgNo + 1, false);
       else if (!IsInPrologue && FuncInfo.DescribedArgs.test(ArgNo))
         return false;
       FuncInfo.DescribedArgs.set(ArgNo);
     }
   }
 
-  MachineFunction &MF = DAG.getMachineFunction();
-  const TargetInstrInfo *TII = DAG.getSubtarget().getInstrInfo();
-
   bool IsIndirect = false;
   Optional<MachineOperand> Op;
   // Some arguments' frame index is recorded during argument lowering.
   int FI = FuncInfo.getArgumentFrameIndex(Arg);
   if (FI != std::numeric_limits<int>::max())
     Op = MachineOperand::CreateFI(FI);
 
   SmallVector<std::pair<unsigned, TypeSize>, 8> ArgRegsAndSizes;
auto splitMultiRegDbgValue = [&](ArrayRef<std::pair<unsigned, TypeSize>>
         // If a valid fragment expression cannot be created, the variable's
         // correct value cannot be determined and so it is set as Undef.
         if (!FragmentExpr) {
           SDDbgValue *SDV = DAG.getConstantDbgValue(
               Variable, Expr, UndefValue::get(V->getType()), DL, SDNodeOrder);
           DAG.AddDbgValue(SDV, false);
           continue;
         }
-        FuncInfo.ArgDbgValues.push_back(
-          BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsDbgDeclare,
-                  RegAndSize.first, Variable, *FragmentExpr));
+        MachineInstr *NewMI =
+            MakeVRegDbgValue(RegAndSize.first, *FragmentExpr, IsDbgDeclare);
+        FuncInfo.ArgDbgValues.push_back(NewMI);
       }
     };
 
     // Check if ValueMap has reg number.
     DenseMap<const Value *, Register>::const_iterator
       VMI = FuncInfo.ValueMap.find(V);
     if (VMI != FuncInfo.ValueMap.end()) {
       const auto &TLI = DAG.getTargetLoweringInfo();
if (!Op) {
     }
   }
 
   if (!Op)
     return false;
 
   assert(Variable->isValidLocationForIntrinsic(DL) &&
          "Expected inlined-at fields to agree");
-  IsIndirect = (Op->isReg()) ? IsIndirect : true;
-  FuncInfo.ArgDbgValues.push_back(
-      BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), IsIndirect,
-              *Op, Variable, Expr));
+  MachineInstr *NewMI = nullptr;
+
+  if (Op->isReg())
+    NewMI = MakeVRegDbgValue(Op->getReg(), Expr, IsIndirect);
+  else
+    NewMI = BuildMI(MF, DL, TII->get(TargetOpcode::DBG_VALUE), true, *Op,
+                    Variable, Expr);
 
+  FuncInfo.ArgDbgValues.push_back(NewMI);
   return true;
 }
 
 /// Return the appropriate SDDbgValue based on N.
 SDDbgValue *SelectionDAGBuilder::getDbgValue(SDValue N,
                                              DILocalVariable *Variable,
                                              DIExpression *Expr,
                                              const DebugLoc &dl,

llvm/lib/Target/X86/X86InstrInfo.cpp

case X86::SUB8rr: {
     case X86::SUB32ri:   NewOpcode = X86::CMP32ri;   break;
     case X86::SUB32ri8:  NewOpcode = X86::CMP32ri8;  break;
     case X86::SUB16ri:   NewOpcode = X86::CMP16ri;   break;
     case X86::SUB16ri8:  NewOpcode = X86::CMP16ri8;  break;
     case X86::SUB8ri:    NewOpcode = X86::CMP8ri;    break;
     }
     CmpInstr.setDesc(get(NewOpcode));
     CmpInstr.RemoveOperand(0);
+    // Mutating this instruction invalidates any debug data associated with it.
+    CmpInstr.setDebugInstrNum(0);
     // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
     if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
         NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
       return false;
   }
   }
 
   // Get the unique definition of SrcReg.

llvm/test/DebugInfo/MIR/InstrRef/phi-coalesce-subreg.mir

 body:             |
   bb.0.entry:
     liveins: $edi, $esi
   
     %4:gr32 = COPY $esi
     %3:gr32 = COPY $edi
     %6:gr16 = COPY %4.sub_16bit
     %5:gr16 = COPY %3.sub_16bit
-    DBG_VALUE %5, $noreg, !12, !DIExpression(), debug-location !13
-    DBG_VALUE %6, $noreg, !14, !DIExpression(), debug-location !13
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
     %15:gr32 = MOVSX32rr16 %5, debug-location !13
     $edi = COPY %15, debug-location !13
     CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $edi, debug-location !13
     ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
     %14:gr32 = MOVSX32rr16 %5, debug-location !13
     %13:gr32 = ADD32ri8 killed %14, 12, implicit-def $eflags, debug-location !13
     %11:gr16 = COPY killed %13.sub_16bit, debug-location !13
-    DBG_VALUE %11, $noreg, !12, !DIExpression(), debug-location !13
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
     %9:gr32 = MOVSX32rr16 %11, debug-location !13
     $edi = COPY %9, debug-location !13
     CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $edi, debug-location !13
     ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
     CALL64pcrel32 @getlong, csr_64, implicit $rsp, implicit $ssp, implicit-def $ax, debug-location !13
     ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
     %8:gr16 = COPY $ax, debug-location !13
     CMP16ri8 %8, 0, implicit-def $eflags, debug-location !13
     JCC_1 %bb.2, 4, implicit $eflags, debug-location !13
   
   ; DOESCOALESCE-LABEL: bb.1.if.then:
   ; CHECK-LABEL:        bb.1.if.then:
   bb.1.if.then:
     %20:gr32 = MOVSX32rr16 %11, debug-location !13
     %19:gr32 = ADD32ri8 killed %20, 1, implicit-def $eflags, debug-location !13
     %17:gr16 = COPY killed %19.sub_16bit, debug-location !13
-    DBG_VALUE %17, $noreg, !12, !DIExpression(), debug-location !13
 
-  ; Verify that vreg 17 is coalesced into gr32.
+  ; Verify that vreg 17 is coalesced into a gr32, and not copied any further.
   ; DOESCOALESCE:       %{{[0-9]+}}:gr32 = ADD32ri8
-  ; DOESCOALESCE-NEXT:  DBG_VALUE %{{[0-9]+}}.sub_16bit,
+  ; DOESCOALESCE-NOT:   COPY
   ; Verify those registers land in $bx
   ; CHECK:              renamable $ebp = ADD32ri8
-  ; CHECK-NEXT:         DBG_VALUE $bp
 
   ; DOESCOALESCE-LABEL: bb.2.if.end:
   ; CHECK-LABEL:        bb.2.if.end:
   bb.2.if.end:
     %2:gr16 = PHI %11, %bb.0, %17, %bb.1, debug-instr-number 1, debug-location !13
   ; CHECK:              DBG_PHI $bp, 1
     DBG_INSTR_REF 1, 0, !12, !DIExpression(), debug-location !13
     %31:gr32 = MOVSX32rr16 %6, debug-location !13
     %30:gr32 = MOVSX32rr16 killed %2, debug-location !13
     %29:gr32 = ADD32rr killed %30, killed %31, implicit-def $eflags, debug-location !13
     %26:gr16 = COPY killed %29.sub_16bit, debug-location !13
-    DBG_VALUE %26, $noreg, !12, !DIExpression(), debug-location !13
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
     %24:gr32 = MOVSX32rr16 %26, debug-location !13
     $edi = COPY %24, debug-location !13
     CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $edi, debug-location !13
     ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
     %23:gr32 = MOVSX32rr16 %26, debug-location !13
     $eax = COPY %23, debug-location !13
     RETQ implicit $eax, debug-location !13
 
 ...

llvm/test/DebugInfo/MIR/InstrRef/phi-coalescing.mir

 # RUN: llc %s -o - -mtriple=x86_64-unknown-unknown \
 # RUN:    -experimental-debug-variable-locations \
 # RUN:    -run-pass=phi-node-elimination,simple-register-coalescing \
 # RUN:    | FileCheck %s --check-prefix=DOESCOALESCE
 # RUN: llc %s -o - -mtriple=x86_64-unknown-unknown \
 # RUN:    -experimental-debug-variable-locations \
 # RUN:    -run-pass=phi-node-elimination,simple-register-coalescing,livedebugvars,greedy,virtregrewriter \
 # RUN:    | FileCheck %s --check-prefix=CHECK
 #
 # Test that a PHI with a debug instruction number attached survives register
 # coalescing, when its vreg gets coalesced. This test comes in two parts, first
 # that coalescing actually happens, second that a DBG_PHI is still produced
 # afterwards.
 #
 # Original C code, the PHI is of the value of 'bar' after the control flow.
 # Compiled at -O0, applied -mem2reg, llc -O0, then manually added the PHI
-# instruction label.
+# instruction label. Additional variable locations removed.
 #
 #    void ext(long);
 #    long getlong(void);
 #    int foo(long bar, long baz) {
 #      ext(bar);
 #      bar += 12;
 #      ext(bar);
 #    

 body:             |
   bb.0.entry:
     liveins: $rdi, $rsi
   
     %5:gr64 = COPY $rsi
     %3:gr64 = COPY $rdi
     %4:gr64 = COPY killed %3
     %6:gr64 = COPY killed %5
-    DBG_VALUE %4, $noreg, !12, !DIExpression(), debug-location !13
-    DBG_VALUE %6, $noreg, !14, !DIExpression(), debug-location !13
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
     $rdi = COPY %4, debug-location !13
     CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, debug-location !13
     ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
     %9:gr64 = ADD64ri32 %4, 12, implicit-def $eflags, debug-location !13
-    DBG_VALUE %9, $noreg, !12, !DIExpression(), debug-location !13
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
     $rdi = COPY %9, debug-location !13
     CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, debug-location !13
     ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
     CALL64pcrel32 @getlong, csr_64, implicit $rsp, implicit $ssp, implicit-def $rax, debug-location !13
     ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
     %8:gr64 = COPY $rax, debug-location !13
     CMP64ri8 %8, 0, implicit-def $eflags, debug-location !13
     JCC_1 %bb.2, 4, implicit $eflags, debug-location !13
   
   ; DOESCOALESCE-LABEL: bb.1.if.then:
   ; CHECK-LABEL:        bb.1.if.then:
   bb.1.if.then:
     %10:gr64 = ADD64ri32 %9, 1, implicit-def $eflags, debug-location !13
-    DBG_VALUE %10, $noreg, !12, !DIExpression(), debug-location !13
 
   ; Verify that the vreg is different immediately after register coalescing.
   ; DOESCOALESCE-NOT:   %10:gr64 ADD64ri32
   ; DOESCOALESCE:       %{{[0-9]+}}:gr64 = ADD64ri32
   ; Verify that all these registers land in rbx.
   ; CHECK:              renamable $rbx = ADD64ri32 killed renamable $rbx
   
   ; DOESCOALESCE-LABEL: bb.2.if.end:
   ; CHECK-LABEL:        bb.2.if.end:
   bb.2.if.end:
     %2:gr64 = PHI %9, %bb.0, %10, %bb.1, debug-instr-number 1, debug-location !13
   ; CHECK:              DBG_PHI $rbx, 1
     DBG_INSTR_REF 1, 0, !12, !DIExpression(), debug-location !13
     %14:gr64 = ADD64rr killed %2, %6, implicit-def $eflags, debug-location !13
-    DBG_VALUE %14, $noreg, !12, !DIExpression(), debug-location !13
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
     $rdi = COPY %14, debug-location !13
     CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit $rdi, debug-location !13
     ADJCALLSTACKUP64 0, 0, implicit-def $rsp, implicit-def $eflags, implicit-def $ssp, implicit $rsp, implicit $ssp, debug-location !13
     %13:gr32 = COPY %14.sub_32bit, debug-location !13
     $eax = COPY %13, debug-location !13
     RETQ implicit $eax, debug-location !13
 
 ...

llvm/test/DebugInfo/MIR/InstrRef/phi-regallocd-to-stack.mir

body:             |
   ; CHECK:       MOV32mr %stack.1, 1, $noreg, 0, $noreg, killed renamable $ebp
   bb.0:
     successors: %bb.2(0x50000000), %bb.1(0x30000000)
     liveins: $edi, $esi
 
     DBG_VALUE $edi, $noreg, !11, !DIExpression(), debug-location !12
     DBG_VALUE $esi, $noreg, !13, !DIExpression(), debug-location !12
     %2:gr32 = COPY killed $esi
-    DBG_VALUE %2, $noreg, !13, !DIExpression(), debug-location !12
     %1:gr32 = COPY killed $edi
-    DBG_VALUE %1, $noreg, !11, !DIExpression(), debug-location !12
-    DBG_VALUE 0, $noreg, !14, !DIExpression(), debug-location !12
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !15
     %3:gr32 = MOV32r0 implicit-def dead $eflags
     $edi = COPY killed %3, debug-location !15
     CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit killed $edi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !15
     ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !15
     %4:gr32 = COPY killed $eax, debug-location !15
     %10:gr32 = MOV32ri 0
     %11:gr32 = MOV32ri 1
bb.0:
     %22:gr32 = MOV32ri 12
     %23:gr32 = MOV32ri 13
     %24:gr32 = MOV32ri 14
     TEST32rr killed %4, %4, implicit-def $eflags, debug-location !15
     JCC_1 %bb.2, 5, implicit killed $eflags, debug-location !17
     JMP_1 %bb.1, debug-location !17
 
   bb.1:
-    DBG_VALUE %2, $noreg, !14, !DIExpression(), debug-location !12
     %30:gr32 = MOV32ri 0
     %31:gr32 = MOV32ri 1
     %32:gr32 = MOV32ri 2
     %33:gr32 = MOV32ri 3
     %34:gr32 = MOV32ri 4
     %35:gr32 = MOV32ri 5
     %36:gr32 = MOV32ri 6
     %37:gr32 = MOV32ri 7

llvm/test/DebugInfo/MIR/InstrRef/phi-through-regalloc.mir

 body:             |
   bb.0.entry:
     successors: %bb.2(0x50000000), %bb.1(0x30000000)
     liveins: $edi, $esi
 
     DBG_VALUE $edi, $noreg, !11, !DIExpression(), debug-location !12
     DBG_VALUE $esi, $noreg, !13, !DIExpression(), debug-location !12
     %2:gr32 = COPY killed $esi
-    DBG_VALUE %2, $noreg, !13, !DIExpression(), debug-location !12
     %1:gr32 = COPY killed $edi
-    DBG_VALUE %1, $noreg, !11, !DIExpression(), debug-location !12
     DBG_VALUE 0, $noreg, !14, !DIExpression(), debug-location !12
     ADJCALLSTACKDOWN64 0, 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !15
     %3:gr32 = MOV32r0 implicit-def dead $eflags
     $edi = COPY killed %3, debug-location !15
     CALL64pcrel32 @ext, csr_64, implicit $rsp, implicit $ssp, implicit killed $edi, implicit-def $rsp, implicit-def $ssp, implicit-def $eax, debug-location !15
     ADJCALLSTACKUP64 0, 0, implicit-def dead $rsp, implicit-def dead $eflags, implicit-def dead $ssp, implicit $rsp, implicit $ssp, debug-location !15
     %4:gr32 = COPY killed $eax, debug-location !15
     TEST32rr killed %4, %4, implicit-def $eflags, debug-location !15
     JCC_1 %bb.2, 5, implicit killed $eflags, debug-location !17
     JMP_1 %bb.1, debug-location !17
 
   bb.1.if.else:
-    DBG_VALUE %2, $noreg, !14, !DIExpression(), debug-location !12
 
     ; CHECK-LABEL: bb.2.if.end:
   bb.2.if.end:
     %0:gr32 = PHI %1, %bb.0, %2, %bb.1, debug-instr-number 1, debug-location !18
     DBG_INSTR_REF 1, 0, !14, !DIExpression(), debug-location !12
     ; CHECK:      DBG_PHI $ebp, 1
     ; CHECK:      DBG_INSTR_REF 1, 0
     $eax = COPY killed %0, debug-location !19
     ; Confirm that %0 is allocated in $ebp,
     ; CHECK:      $eax = COPY killed renamable $ebp
     RET 0, killed $eax, debug-location !19
 
 ...

llvm/test/DebugInfo/MIR/InstrRef/x86-drop-compare-inst.mir

+# RUN: llc %s -o - -experimental-debug-variable-locations -run-pass=peephole-opt | FileCheck %s
+#
+# X86 initially produces subtract operations to perform comparisons, and then
+# downgrades them into cmp instructions if nothing uses the result. It does this
+# by calling setDesc on the instruction, mutating it from one sort to another,
+# which makes any debug instruction numbers attached to the number invalid.
+# This test tests that the relevant instruction number is dropped.
+#
+# CHECK-NOT: debug-instr-number
+# CHECK:     CMP32rm
+# CHECK-NOT: debug-instr-number
+#
+--- |
+  ; ModuleID = '/fast/fs/build34llvm4/reduced.ll'
+  target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-f80:128-n8:16:32:64-S128"
+  target triple = "x86_64-unknown-linux-gnu"
+  
+  %"class.std::vector.534" = type { %"struct.std::_Vector_base.535" }
+  %"struct.std::_Vector_base.535" = type { %"struct.std::_Vector_base<unsigned char, std::allocator<unsigned char>>::_Vector_impl" }
+  %"struct.std::_Vector_base<unsigned char, std::allocator<unsigned char>>::_Vector_impl" = type { i8*, i8*, i8* }
+  
+  ; Function Attrs: nofree nosync nounwind readnone speculatable willreturn
+  declare void @llvm.dbg.declare(metadata, metadata, metadata) #0
+  
+  define hidden fastcc void @soup() unnamed_addr !dbg !3 {
+  _ZN4llvm11raw_ostreamlsEPKc.exit2752:
+    %0 = load %"class.std::vector.534"*, %"class.std::vector.534"** undef, align 8, !dbg !7
+    %1 = load i8*, i8** undef, align 8, !dbg !7
+    %_M_start.i2756 = getelementptr inbounds %"class.std::vector.534", %"class.std::vector.534"* %0, i64 undef, i32 0, i32 0, i32 0, !dbg !7
+    %2 = load i8*, i8** %_M_start.i2756, align 8, !dbg !7
+    %sub.ptr.lhs.cast.i2757 = ptrtoint i8* %1 to i64, !dbg !7
+    %sub.ptr.rhs.cast.i2758 = ptrtoint i8* %2 to i64, !dbg !7
+    %sub.ptr.sub.i2759 = sub i64 %sub.ptr.lhs.cast.i2757, %sub.ptr.rhs.cast.i2758, !dbg !7
+    %conv373 = trunc i64 %sub.ptr.sub.i2759 to i32, !dbg !7
+    call void @llvm.dbg.value(metadata i32 %conv373, metadata !8, metadata !DIExpression()), !dbg !7
+    %cmp375.not2842 = icmp eq i32 %conv373, 0, !dbg !7
+    br i1 %cmp375.not2842, label %for.cond.cleanup376, label %for.body377, !dbg !7
+  
+  for.cond.cleanup376:                              ; preds = %_ZN4llvm11raw_ostreamlsEPKc.exit2752
+    ret void
+  
+  for.body377:                                      ; preds = %_ZN4llvm11raw_ostreamlsEPKc.exit2752
+    ret void
+  }
+  
+  ; Function Attrs: nofree nosync nounwind readnone speculatable willreturn
+  declare void @llvm.dbg.value(metadata, metadata, metadata) #0
+  
+  attributes #0 = { nofree nosync nounwind readnone speculatable willreturn }
+  
+  !llvm.module.flags = !{!0}
+  !llvm.dbg.cu = !{!1}
+  
+  !0 = !{i32 2, !"Debug Info Version", i32 3}
+  !1 = distinct !DICompileUnit(language: DW_LANG_C_plus_plus, file: !2, producer: "beards", isOptimized: true, runtimeVersion: 4, emissionKind: FullDebug)
+  !2 = !DIFile(filename: "bees.cpp", directory: "")
+  !3 = distinct !DISubprogram(name: "nope", scope: !2, file: !2, line: 1, type: !4, spFlags: DISPFlagDefinition, unit: !1)
+  !4 = !DISubroutineType(types: !5)
+  !5 = !{!6}
+  !6 = !DIBasicType(name: "int", size: 32, encoding: DW_ATE_signed)
+  !7 = !DILocation(line: 1, scope: !3)
+  !8 = !DILocalVariable(name: "flannel", scope: !3)
+
+...
+---
+name:            soup
+alignment:       16
+tracksRegLiveness: true
+registers:
+  - { id: 0, class: gr64 }
+  - { id: 1, class: gr64 }
+  - { id: 2, class: gr32 }
+  - { id: 3, class: gr32 }
+frameInfo:
+  maxAlignment:    1
+machineFunctionInfo: {}
+body:             |
+  bb.0._ZN4llvm11raw_ostreamlsEPKc.exit2752:
+    successors: %bb.1(0x30000000), %bb.2(0x50000000)
+  
+    %1:gr64 = IMPLICIT_DEF
+    %0:gr64 = MOV64rm killed %1, 1, $noreg, 0, $noreg, debug-location !7 :: (load (s64) from `i8** undef`)
+    %2:gr32 = COPY %0.sub_32bit, debug-location !7
+    %3:gr32 = SUB32rm %2, %0, 1, $noreg, 0, $noreg, implicit-def $eflags, debug-instr-number 1, debug-location !7 :: (load (s32) from %ir._M_start.i2756, align 8)
+    DBG_INSTR_REF 1, 0, !8, !DIExpression(), debug-location !7
+    JCC_1 %bb.2, 5, implicit $eflags, debug-location !7
+    JMP_1 %bb.1, debug-location !7
+  
+  bb.1.for.cond.cleanup376:
+    RET 0
+  
+  bb.2.for.body377:
+    RET 0
+
+...