[DebugInfo][InstrRef][1/4] Support transformations that widen or narrow defined values

[jmorse]

Summary

(That's right, even more patches! This is the third and final patch series for the instruction referencing work, see D85741. Everything "Interesting" should be covered by this and the two prior series, there will be a couple more individual patches to mop up optimisations that drop instruction numbers, and after that we're Done (TM)).

Very late in compilation, backends like X86 will perform optimsations like this:

%cx = MOV16rm $rax, blah blah blah
->
%rcx = MOV64rm $rax, blah blah blah

Widening the load from 16 bits to 64 bits. Seeing how the lower 16 bits remain the same this doesn't affect execution, but is a more compact instruction. However, any debug instruction reference to the defined operand now refers to a 64 bit value, not a 16 bit one, which might be unexpected. Similar things happen earlier in CodeGen:

CALL64pcrel32 @foo, implicit-def $rax
%0:gr64 = COPY $rax
%1:gr32 = COPY %0.sub_32bit

For reasons that will become clear later, we definitely don't want to label any of the COPYs with debug-instr-number. If we care about %1 for debug purposes, then we need to be able to refer to $eax's definition at the CALL64pcrel32, but it defines the wider $rax. This isn't just a matter of width either: some architectures let you refer to the high and low parts of a superregister (such as $al and $ah).

The solution: add a subregister field to the existing "substitutions" facility that lets us point one instruction / operand pair at another. Using the widening example from above, if we had:

%cx = MOV16rm $rax, blah blah blah, debug-instr-number 1 
DBG_INSTR_REF 1, 0

And widened it to be a 64 bit load, record a substitution with a subregister qualifier:

debugValueSubstitutions:
  - { srcinst: 2, srcop: 0, dstinst: 1, dstop: 0, subreg: 4 } 
  
%rcx = MOV64rm $rax, blah blah blah, debug-instr-number 2 
DBG_INSTR_REF 1, 0

The DBG_INSTR_REF still refers to the same number; but a substitution has to be looked up. And that substitution specifies that the sub_16bit field of instruction 1 / operand 0 should be read. These can even be chained.

This patch extends a few APIs to cope with this, and as a demonstration adds the relevant instrumentation to the X86FixupBWInsts pass, which performs the optimisation described above. I've also fiddled with a few tests for substitution stuff now that we've added a new field.

Having established that this feature is needed, the next patch adds support to InstrRefBasedLDV, the third makes use of it when handing COPYs in SelectionDAG, and the fourth does some cleanup.

[MaskRay]

curl -L 'https://reviews.llvm.org/D88891?download=1' does not have a/ or b/ prefix. Can you upload a diff with either arc diff, git format-patch -1 or git diff 'HEAD^'? Thanks.

I think arc diff and git format-patch -1 are preferred because they have the base commit information so people can apply this locally with arc patch D88891.

[jmorse]

(Rebase now that I've dropped some "REQUIRES: X86" lines in the modified tests...)

[jmorse]

Sorry it took so long to get back to this,

In D88891#2323663, @MaskRay wrote:

curl -L 'https://reviews.llvm.org/D88891?download=1' does not have a/ or b/ prefix. Can you upload a diff with either arc diff, git format-patch -1 or git diff 'HEAD^'? Thanks.

I think arc diff and git format-patch -1 are preferred because they have the base commit information so people can apply this locally with arc patch D88891.

Hmmm -- I did not know there was that much base / parent information preserved in phab, looking closer I see that other peoples revisions have hashes and parents, wheras mine only have diff numbers. I'll try uploading the output of git-format-patch and see what happens; I've also updated the parent commits to better represent what order these patches need to apply in.

[jmorse]

(rebase again to see if phab will accept more information about base commits and the like)

[StephenTozer]

One small nit/question attached, otherwise LGTM. Given that we don't always correctly follow subregister changes in DBG_VALUEs at the moment, this is a pleasant improvement!

llvm/lib/CodeGen/MIRParser/MIRParser.cpp

429

Complete nit, but is there a reason for the std::make_pair -> {} substitution?

[StephenTozer]

llvm/include/llvm/CodeGen/MachineFunction.h

494

Also not so much a nit or request as a question; should this default value be taken to mean that it is okay for the substitution's subreg to be larger than the source operand, with such a case being treated as a no-op rather than a sext/zext? I'd assume so, since I don't believe that we would ever want to produce a sext/zext using this substitution mechanism - that should only happen as a result of salvaging.

llvm/lib/Target/X86/X86FixupBWInsts.cpp

381

Also one more question about the intended behaviour (that does not block this patch at all), it's potentially expected that we may have to recurse through several substitutions? As is I don't think there's any issue with that, since I believe there is a small lower bound on the number of substitutions we could ever need to make for a single reference, and it seems easier than checking for existing substitutions everywhere that we might create one.

[StephenTozer]

llvm/lib/Target/X86/X86FixupBWInsts.cpp

381

s/lower/upper

[djtodoro]

@jmorse Thanks for doing this. Should we document this new MF attribute somehow? If we already created it, should we add an explanation of this new field there?

From the patch summary, I think that this is reasonable change.

llvm/include/llvm/CodeGen/MachineFunction.h

471

Do we need the std::map sortness here?

llvm/lib/CodeGen/MIRPrinter.cpp

227–234

nit: const auto &Sub ?

[jmorse]

llvm/include/llvm/CodeGen/MachineFunction.h

471

Hmmm -- not during the optimisation passes, so this can become a vector that gets sorted when lookups occur.

(I have another patch (not uploaded yet) that might need the sortness, but that can be evaluated in its own right).

494

That would be my interpretation, yeah -- while a reproducer doesn't immediately spring to mind, I can't think of a part of post-isel debug-info that minds if $al is expanded to $rax when it's the operand of a DBG_VALUE. I'm confident I've seen it in the past, but can't put my finger on it right now.

In theory, as future work, we could eliminate that situation if we perfectly instrumented the entire backend with substitution subregister info, but I don't think we would gain anything from that.

llvm/lib/CodeGen/MIRParser/MIRParser.cpp

429

IIRC it's the preferred form, and I was taking the opportunity to fix it up as this line changes anyway.

Not sure why I didn't do the other make_pair, I'll edit that in.

llvm/lib/Target/X86/X86FixupBWInsts.cpp

381

Indeed, multiple substitutions might be made -- the number will be proportionate to the amount of optimisation that has happened to a value, so it shouldn't inflate massively. It's the realisation of the overall theme: don't maintain a perfectly accurate mapping of variable locations during compilation, instead document what happens and piece it together later.

[jmorse]

llvm/include/llvm/CodeGen/MachineFunction.h

471

I realised that it's already in-tree with a std::map -- I've written D105029 as a separate patch that un-sorts it.

llvm/include/llvm/CodeGen/MIRYamlMapping.h

 };
 
 /// Serializable representation of debug value substitutions.
 struct DebugValueSubstitution {
   unsigned SrcInst;
   unsigned SrcOp;
   unsigned DstInst;
   unsigned DstOp;
+  unsigned Subreg;
 
   bool operator==(const DebugValueSubstitution &Other) const {
     return std::tie(SrcInst, SrcOp, DstInst, DstOp) ==
            std::tie(Other.SrcInst, Other.SrcOp, Other.DstInst, Other.DstOp);
   }
 };
 
 template <> struct MappingTraits<DebugValueSubstitution> {
   static void mapping(IO &YamlIO, DebugValueSubstitution &Sub) {
     YamlIO.mapRequired("srcinst", Sub.SrcInst);
     YamlIO.mapRequired("srcop", Sub.SrcOp);
     YamlIO.mapRequired("dstinst", Sub.DstInst);
     YamlIO.mapRequired("dstop", Sub.DstOp);
+    YamlIO.mapRequired("subreg", Sub.Subreg);
   }
 
   static const bool flow = true;
 };
 } // namespace yaml
 } // namespace llvm
 
 LLVM_YAML_IS_SEQUENCE_VECTOR(llvm::yaml::DebugValueSubstitution)

llvm/include/llvm/CodeGen/MachineFunction.h

public:
 
   /// Set value of DebugInstrNumberingCount field. Avoid using this unless
   /// you're deserializing this data.
   void setDebugInstrNumberingCount(unsigned Num);
 
   /// Pair of instruction number and operand number.
   using DebugInstrOperandPair = std::pair<unsigned, unsigned>;
 
-  /// Substitution map: from one <inst,operand> pair to another. Used to
-  /// record changes in where a value is defined, so that debug variable
-  /// locations can find it later.
-  std::map<DebugInstrOperandPair, DebugInstrOperandPair>
-      DebugValueSubstitutions;
+  /// Replacement definition for a debug instruction reference. Made up of an
+  /// instruction / operand pair, and a qualifying subregister indicating what
+  /// bits in the operand make up the substitution. For example, a debug user
+  /// of %1:
+  ///    %0:gr32 = someinst, debug-instr-number 2
+  ///    %1:gr16 = %0.some_16_bit_subreg
+  /// Would receive the substitution {{2, 0}, $subreg}, where $subreg is the
+  /// subregister number for some_16_bit_subreg.
+  struct DebugSubstitution {
+    DebugInstrOperandPair Dest; ///< Replacement instruction / operand pair.
+    unsigned Subreg;            ///< Qualifier for which part of Dest is read.
+  };
+
+  /// Substitution map: from one <inst,operand> pair identifying a value,
+  /// to a DebugSubstitution identifying another. Used to record changes in
+  /// where a value is defined, so that debug variable locations can find it
+  /// later.
+  std::map<DebugInstrOperandPair, DebugSubstitution> DebugValueSubstitutions;
 
   /// Location of a PHI instruction that is also a debug-info variable value,
   /// for the duration of register allocation. Loaded by the PHI-elimination
   /// pass, and emitted as DBG_PHI instructions during VirtRegRewriter, with
   /// maintenance applied by intermediate passes that edit registers (such as
   /// coalescing and the allocator passes).
   class DebugPHIRegallocPos {
   public:
     MachineBasicBlock *MBB; ///< Block where this PHI was originally located.
     Register Reg;           ///< VReg where the control-flow-merge happens.
     unsigned SubReg;        ///< Optional subreg qualifier within Reg.
     DebugPHIRegallocPos(MachineBasicBlock *MBB, Register Reg, unsigned SubReg)
         : MBB(MBB), Reg(Reg), SubReg(SubReg) {}
   };
 
   /// Map of debug instruction numbers to the position of their PHI instructions
   /// during register allocation. See DebugPHIRegallocPos.
   DenseMap<unsigned, DebugPHIRegallocPos> DebugPHIPositions;
 
   /// Create a substitution between one <instr,operand> value to a different,
   /// new value.
-  void makeDebugValueSubstitution(DebugInstrOperandPair, DebugInstrOperandPair);
+  void makeDebugValueSubstitution(DebugInstrOperandPair, DebugInstrOperandPair,
+                                  unsigned SubReg = 0);
 
   /// Create substitutions for any tracked values in \p Old, to point at
   /// \p New. Needed when we re-create an instruction during optimization,
   /// which has the same signature (i.e., def operands in the same place) but
   /// a modified instruction type, flags, or otherwise. An example: X86 moves
   /// are sometimes transformed into equivalent LEAs.
   /// If the two instructions are not the same opcode, limit which operands to
   /// examine for substitutions to the first N operands by setting

llvm/include/llvm/CodeGen/MachineInstr.h

public:
   /// Return the debug label referenced by
   /// this DBG_LABEL instruction.
   const DILabel *getDebugLabel() const;
 
   /// Fetch the instruction number of this MachineInstr. If it does not have
   /// one already, a new and unique number will be assigned.
   unsigned getDebugInstrNum();
 
+  /// Fetch instruction number of this MachineInstr -- but before it's inserted
+  /// into \p MF. Needed for transformations that create an instruction but
+  /// don't immediately insert them.
+  unsigned getDebugInstrNum(MachineFunction &MF);
+
   /// Examine the instruction number of this MachineInstr. May be zero if
   /// it hasn't been assigned a number yet.
   unsigned peekDebugInstrNum() const { return DebugInstrNum; }
 
   /// Set instruction number of this MachineInstr. Avoid using unless you're
   /// deserializing this information.
   void setDebugInstrNum(unsigned Num) { DebugInstrNum = Num; }
 

llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp

bool InstrRefBasedLDV::transferDebugInstrRef(MachineInstr &MI,
 
   const MachineFunction &MF = *MI.getParent()->getParent();
 
   // Various optimizations may have happened to the value during codegen,
   // recorded in the value substitution table. Apply any substitutions to
   // the instruction / operand number in this DBG_INSTR_REF.
   auto Sub = MF.DebugValueSubstitutions.find(std::make_pair(InstNo, OpNo));
   while (Sub != MF.DebugValueSubstitutions.end()) {
-    InstNo = Sub->second.first;
-    OpNo = Sub->second.second;
+    InstNo = Sub->second.Dest.first;
+    OpNo = Sub->second.Dest.second;
     Sub = MF.DebugValueSubstitutions.find(std::make_pair(InstNo, OpNo));
   }
 
   // Default machine value number is <None> -- if no instruction defines
   // the corresponding value, it must have been optimized out.
   Optional<ValueIDNum> NewID = None;
 
   // Try to lookup the instruction number, and find the machine value number

llvm/lib/CodeGen/MIRParser/MIRParser.cpp

void MIRParserImpl::setupDebugValueTracking(
   unsigned MaxInstrNum = 0;
   for (auto &MBB : MF)
     for (auto &MI : MBB)
       MaxInstrNum = std::max((unsigned)MI.peekDebugInstrNum(), MaxInstrNum);
   MF.setDebugInstrNumberingCount(MaxInstrNum);
 
   // Load any substitutions.
   for (auto &Sub : YamlMF.DebugValueSubstitutions) {
-    MF.makeDebugValueSubstitution(std::make_pair(Sub.SrcInst, Sub.SrcOp),
-                                  std::make_pair(Sub.DstInst, Sub.DstOp));
+    MF.makeDebugValueSubstitution({Sub.SrcInst, Sub.SrcOp},
+                                  {Sub.DstInst, Sub.DstOp}, Sub.Subreg);
   }
 }
 
 bool
 MIRParserImpl::initializeMachineFunction(const yaml::MachineFunction &YamlMF,
                                          MachineFunction &MF) {
   // TODO: Recreate the machine function.
   if (Target) {

llvm/lib/CodeGen/MIRPrinter.cpp

YamlMF.FailedISel = MF.getProperties().hasProperty(
       MachineFunctionProperties::Property::FailedISel);
 
   convert(YamlMF, MF.getRegInfo(), MF.getSubtarget().getRegisterInfo());
   MachineModuleSlotTracker MST(&MF);
   MST.incorporateFunction(MF.getFunction());
   convert(MST, YamlMF.FrameInfo, MF.getFrameInfo());
   convertStackObjects(YamlMF, MF, MST);
   convertCallSiteObjects(YamlMF, MF, MST);
-  for (auto &Sub : MF.DebugValueSubstitutions)
-    YamlMF.DebugValueSubstitutions.push_back({Sub.first.first, Sub.first.second,
-                                              Sub.second.first,
-                                              Sub.second.second});
+  for (const auto &Sub : MF.DebugValueSubstitutions) {
+    auto &SubSrc = Sub.first;
+    const MachineFunction::DebugSubstitution &SubDest = Sub.second;
+    YamlMF.DebugValueSubstitutions.push_back({SubSrc.first, SubSrc.second,
+                                              SubDest.Dest.first,
+                                              SubDest.Dest.second,
+                                              SubDest.Subreg});
+  }
   if (const auto *ConstantPool = MF.getConstantPool())
     convert(YamlMF, *ConstantPool);
   if (const auto *JumpTableInfo = MF.getJumpTableInfo())
     convert(MST, YamlMF.JumpTableInfo, *JumpTableInfo);
 
   const TargetMachine &TM = MF.getTarget();
   YamlMF.MachineFuncInfo =
       std::unique_ptr<yaml::MachineFunctionInfo>(TM.convertFuncInfoToYAML(MF));

llvm/lib/CodeGen/MachineFunction.cpp

void MachineFunction::moveCallSiteInfo(const MachineInstr *Old,
   CallSitesInfo[New] = CSInfo;
 }
 
 void MachineFunction::setDebugInstrNumberingCount(unsigned Num) {
   DebugInstrNumberingCount = Num;
 }
 
 void MachineFunction::makeDebugValueSubstitution(DebugInstrOperandPair A,
-                                                 DebugInstrOperandPair B) {
-  auto Result = DebugValueSubstitutions.insert(std::make_pair(A, B));
+                                                 DebugInstrOperandPair B,
+                                                 unsigned Subreg) {
+  // Catch any accidental self-loops.
+  assert(A.first != B.first);
+  auto Result = DebugValueSubstitutions.insert({A, {B, Subreg}});
   (void)Result;
   assert(Result.second && "Substitution for an already substituted value?");
 }
 
 void MachineFunction::substituteDebugValuesForInst(const MachineInstr &Old,
                                                    MachineInstr &New,
                                                    unsigned MaxOperand) {
   // If the Old instruction wasn't tracked at all, there is no work to do.

llvm/lib/CodeGen/MachineInstr.cpp

MachineInstr::getFoldedRestoreSize(const TargetInstrInfo *TII) const {
   return None;
 }
 
 unsigned MachineInstr::getDebugInstrNum() {
   if (DebugInstrNum == 0)
     DebugInstrNum = getParent()->getParent()->getNewDebugInstrNum();
   return DebugInstrNum;
 }
+
+unsigned MachineInstr::getDebugInstrNum(MachineFunction &MF) {
+  if (DebugInstrNum == 0)
+    DebugInstrNum = MF.getNewDebugInstrNum();
+  return DebugInstrNum;
+}

llvm/lib/Target/X86/X86FixupBWInsts.cpp

public:
   }
 
 private:
   MachineFunction *MF = nullptr;
 
   /// Machine instruction info used throughout the class.
   const X86InstrInfo *TII = nullptr;
 
+  const TargetRegisterInfo *TRI = nullptr;
+
   /// Local member for function's OptForSize attribute.
   bool OptForSize = false;
 
   /// Machine loop info used for guiding some heruistics.
   MachineLoopInfo *MLI = nullptr;
 
   /// Register Liveness information after the current instruction.
   LivePhysRegs LiveRegs;

 FunctionPass *llvm::createX86FixupBWInsts() { return new FixupBWInstPass(); }
 
 bool FixupBWInstPass::runOnMachineFunction(MachineFunction &MF) {
   if (!FixupBWInsts || skipFunction(MF.getFunction()))
     return false;
 
   this->MF = &MF;
   TII = MF.getSubtarget<X86Subtarget>().getInstrInfo();
+  TRI = MF.getRegInfo().getTargetRegisterInfo();
   MLI = &getAnalysis<MachineLoopInfo>();
   PSI = &getAnalysis<ProfileSummaryInfoWrapperPass>().getPSI();
   MBFI = (PSI && PSI->hasProfileSummary()) ?
          &getAnalysis<LazyMachineBlockFrequencyInfoPass>().getBFI() :
          nullptr;
   LiveRegs.init(TII->getRegisterInfo());
 
   LLVM_DEBUG(dbgs() << "Start X86FixupBWInsts\n";);
MachineInstrBuilder MIB =
       BuildMI(*MF, MI->getDebugLoc(), TII->get(New32BitOpcode), NewDestReg);
 
   unsigned NumArgs = MI->getNumOperands();
   for (unsigned i = 1; i < NumArgs; ++i)
     MIB.add(MI->getOperand(i));
 
   MIB.setMemRefs(MI->memoperands());
 
+  // If it was debug tracked, record a substitution.
+  if (unsigned OldInstrNum = MI->peekDebugInstrNum()) {
+    unsigned Subreg = TRI->getSubRegIndex(MIB->getOperand(0).getReg(),
+                                          MI->getOperand(0).getReg());
+    unsigned NewInstrNum = MIB->getDebugInstrNum(*MF);
+    MF->makeDebugValueSubstitution({OldInstrNum, 0}, {NewInstrNum, 0}, Subreg);
+  }
+
   return MIB;
 }
 
 MachineInstr *FixupBWInstPass::tryReplaceCopy(MachineInstr *MI) const {
   assert(MI->getNumExplicitOperands() == 2);
   auto &OldDest = MI->getOperand(0);
   auto &OldSrc = MI->getOperand(1);
 
MachineInstrBuilder MIB =
       BuildMI(*MF, MI->getDebugLoc(), TII->get(New32BitOpcode), NewDestReg);
 
   unsigned NumArgs = MI->getNumOperands();
   for (unsigned i = 1; i < NumArgs; ++i)
     MIB.add(MI->getOperand(i));
 
   MIB.setMemRefs(MI->memoperands());
 
+  if (unsigned OldInstrNum = MI->peekDebugInstrNum()) {
+    unsigned Subreg = TRI->getSubRegIndex(MIB->getOperand(0).getReg(),
+                                          MI->getOperand(0).getReg());
+    unsigned NewInstrNum = MIB->getDebugInstrNum(*MF);
+    MF->makeDebugValueSubstitution({OldInstrNum, 0}, {NewInstrNum, 0}, Subreg);
+  }
+
   return MIB;
 }
 
 MachineInstr *FixupBWInstPass::tryReplaceInstr(MachineInstr *MI,
                                                MachineBasicBlock &MBB) const {
   // See if this is an instruction of the type we are currently looking for.
   switch (MI->getOpcode()) {
 

llvm/test/DebugInfo/MIR/InstrRef/livedebugvalues_instrref_tolocs.mir

--- |
   !15 = !{!16}
   !16 = !DILocalVariable(name: "myVar", scope: !12, file: !1, line: 7, type: !6)
   !17 = !DILocation(line: 10, scope: !12)
 
 ...
 ---
 name: _Z8bb_to_bb
 debugValueSubstitutions:
-  - { srcinst: 4, srcop: 0, dstinst: 3, dstop: 0 }
+  - { srcinst: 4, srcop: 0, dstinst: 3, dstop: 0, subreg: 0 }
 body:  |
   bb.0.entry:
     $rax = MOV64ri 1, debug-instr-number 1, debug-location !17
     ; This debug instruction should identify the value as being in $rax.
     DBG_INSTR_REF 1, 0, !16, !DIExpression(), debug-location !17
     ; CHECK: DBG_VALUE $rax, $noreg
 
     $rbx = COPY killed $rax, debug-location !17

llvm/test/DebugInfo/MIR/InstrRef/substitusions-roundtrip.mir

 # RUN: llc %s -march=x86-64 -run-pass=machineverifier \
 # RUN:     -experimental-debug-variable-locations -o - 2>&1 | FileCheck %s
 #
 # REQUIRES: x86-registered-target
 #
 # CHECK:      debugValueSubstitutions:
-# CHECK-NEXT: - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0 }
+# CHECK-NEXT: - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0, subreg: 0 }
 #
 # CHECK:      MOV64rr $rdi, debug-instr-number 2
 # CHECK-NEXT: DBG_INSTR_REF 1, 0
 ---
 name: test
 tracksRegLiveness: true
 liveins:
   - { reg: '$rdi', virtual-reg: '' }
 debugValueSubstitutions:
-  - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0 }
+  - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0, subreg: 0 }
 body:  |
   bb.0:
   liveins: $rdi, $rax
     $rbp = MOV64rr $rdi, debug-instr-number 2
     DBG_INSTR_REF 1, 0
     dead $rcx = MOV64ri 0
     CMP64ri8 renamable $rax, 1, implicit-def $eflags
     RETQ $rax
 ...

llvm/test/DebugInfo/MIR/InstrRef/twoaddr-to-threeaddr-sub.mir

 # RUN: llc -run-pass=twoaddressinstruction -mtriple=x86_64-- -o - %s -experimental-debug-variable-locations | FileCheck %s
 #
 # REQUIRES: x86-registered-target
 #
 # Test that a new instruction (LEA) is created when the two-addr add below is
 # converted to three address; and that an appropriate substitution is created.
 # Maybe at some point we'll normalise DBG_INSTR_REFs on output, but until then,
 # lets not.
 #
 # CHECK:      debugValueSubstitutions:
-# CHECK-NEXT:  - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0 }
+# CHECK-NEXT:  - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0, subreg: 0 }
 #
 # CHECK:      LEA64_32r
 # CHECK-SAME: debug-instr-number 2
 #
 # CHECK:      DBG_INSTR_REF 1, 0
 ---
 name:            test1
 alignment:       16

llvm/test/DebugInfo/MIR/InstrRef/x86-fixup-bw-inst-subreb.mir

+# RUN: llc -mtriple=x86_64-unknown-linux-gnu -run-pass x86-fixup-bw-insts %s -o - -experimental-debug-variable-locations | FileCheck  %s
+#
+# This test is a copy of llvm/test/CodeGen/X86/fixup-bw-inst.mir, with a few
+# test bodies removed. The pass promotes certain register operations to be
+# wider operations (such as loads and sign extensions), which has an instruction
+# encoding benefit. New instructions are created, and so should have a debug 
+# instruction number substitution; but in addition a qualifiying subregister,
+# because the newly def'd register is a different size to the old one.
+#
+# Plain copies that get transformed are not tested for, as they should never
+# be instrumented. At a high level, copies do not define a value; they move
+# them.
+
+---
+# CHECK-LABEL: name: test1
+name:            test1
+alignment:       16
+tracksRegLiveness: true
+liveins:
+  - { reg: '$rax' }
+# CHECK:     debugValueSubstitutions:
+# CHECK-NEXT - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0, subreg: 4 }
+## Subreg 4 -> sub_16bit
+body:             |
+  bb.0:
+    liveins: $rax
+
+    $ax = MOV16rm killed $rax, 1, $noreg, 0, $noreg, debug-instr-number 1
+    ; CHECK: $eax = MOVZX32rm16 killed $rax, {{.*}} debug-instr-number 2
+
+    RETQ $ax
+
+...
+---
+# CHECK-LABEL: name: test3
+name:            test3
+alignment:       16
+tracksRegLiveness: true
+liveins:
+  - { reg: '$rdi' }
+# CHECK:     debugValueSubstitutions:
+# CHECK-NEXT - { srcinst: 1, srcop: 0, dstinst: 2, dstop: 0, subreg: 4 }
+## Subreg 4 -> sub_16bit
+body:             |
+  bb.0:
+    successors: %bb.1(0x30000000), %bb.2(0x50000000)
+    liveins: $rdi
+
+    TEST64rr $rdi, $rdi, implicit-def $eflags
+    JCC_1 %bb.1, 4, implicit $eflags
+
+  bb.2:
+    liveins: $rdi
+
+    $ax = MOV16rm killed $rdi, 1, $noreg, 0, $noreg, implicit-def $eax, debug-instr-number 1
+    ; CHECK: $eax = MOVZX32rm16 killed $rdi, {{.*}} debug-instr-number 2
+    $ax = KILL $ax, implicit killed $eax
+    RETQ $ax
+
+  bb.1:
+    $eax = XOR32rr undef $eax, undef $eax, implicit-def dead $eflags
+    $ax = KILL $ax, implicit killed $eax
+    RETQ $ax
+
+...