[lld-macho] Add ARM64 target arch

[gkm]

Summary

This is an initial base commit for ARM64 target arch support. I don't represent that it complete or bug-free, but wish to put it out for review now that some basic things like branch target & load/store address relocs are working.

I can add more tests to this base commit, or add them in follow-up commits.

It is not entirely clear whether I use the "ARM64" (Apple) or "AArch64" (non-Apple) naming convention. Guidance is appreciated.

[gkm]

• remove some left-over X86_64 code

[gkm]

• add stubs support

[gkm]

• cleanups

[gkm]

• correct some reloc length validity sets in arm64RelocAttrs[]

[int3]

lld/MachO/Arch/ARM64.cpp

49

What's the difference between None and false here?

(Also, clang-tidy naming issues seem legit)

80–91

can we factor this out and reuse it across both architectures?

94–108

some comments about the different arm64 instruction formats would be helpful

lld/MachO/Arch/X86_64.cpp

125

what does 'base encoding' mean?

[smeenai]

It is not entirely clear whether I use the "ARM64" (Apple) or "AArch64" (non-Apple) naming convention. Guidance is appreciated.

I would use arm64, since we're targeting Apple platforms.

Still working through the target code, but an initial round of comments.

lld/MachO/Arch/X86_64.cpp

124–126

I think val makes more sense than va here, since it's the calculated value for the relocation that you're writing out, which isn't necessary the target's VA (e.g. for PC-relative relocations).

lld/MachO/Driver.cpp

420

This should be a comparison against the arch that we're targeting, not a comparison against all the archs we support, since the intent is to filter out lines that aren't for the current target arch.

lld/test/lit.cfg.py

70

I think the llvm-config output will always say AArch64 and not ARM64. Is this line needed?

[smeenai]

lld/MachO/Arch/ARM64.cpp

55

Representing the valid lengths as a bitfield is a neat idea :)

111

Would be helpful to elaborate on what "base encoding" is.

112

What is the term "fixup" supposed to refer to? It's a little confusing because ld64 appears to use the term "fixup" instead of "relocation", so I don't know if this is a reference to that or something else.

115

Would be helpful to comment the reason for this assertion (I imagine it's because an instruction VA should always be 4-byte aligned).

lld/MachO/Arch/X86_64.cpp

125

Is this comment applicable to X86_64?

lld/MachO/InputSection.cpp

55–56

Same comment here about VA vs. val. I think I'd prefer to just shift the pcrel handling entirely into relocateOne; yes, it's architecture-agnostic, so there's a *tiny* bit of duplication per-architecture, but then all the logic of going from a referent VA to an actual relocation value gets shifted into relocateOne, which is nicer IMO.

[MarcusJohnson91]

It is not entirely clear whether I use the "ARM64" (Apple) or "AArch64" (non-Apple) naming convention. Guidance is appreciated.

I'd go with AArch64 to match LLVM's naming convention with the backend, if you want to enable ARM64 support when compiling the monorepo, you have to add AArch64 to the cmake variable LLVM_TARGETS_TO_BUILD, so I say be consistent with that.

[gkm]

lld/MachO/Arch/ARM64.cpp

49

llvm::Optional<bool> is tri-state: true, false, and None meaning any / don't care / not applicable.

80–91

Yes. When the dust settles, I will look for this and other opportunities.

94–108

Indeed. When I find the document that catalogues and names the encoding formats I will reference those.

112

I renamed: s/encoding/base/; s/fixupRelocFormat/encodeRelocFormat/

lld/MachO/Arch/X86_64.cpp

124–126

This was intentional: va = Virtual Address. The caller InputSection::writeTo() used to combine the va and r.addend to yield the val, but I moved that inside the TargetInfo::relocateOne() members.

For clarity, I prefer VMA over VA for these names, but there are many instances, e.g., getVA(), so I'll only do that with consent, and in a separate diff.

125

No, I suspect not. I will try assert(r.addend == 0) in X86_64::prepareSymbolRelocation() to be certain.

lld/MachO/Driver.cpp

420

Do you know offhand what is the recommended API for comparing the target arch with an arch name string?

lld/test/lit.cfg.py

70

It's a temporary expediency so that test case REQUIRES: arm64 filter works. I'll iron this out when the AArch64 vs. ARM64 choice is resolved.

[tschuett]

@psmith might be able to help.

The encodings of adrp, add, stp, ldr, ... are described here:
https://developer.arm.com/documentation/ddi0487/latest/

I was referring to the fixup calls.

[gkm]

The encodings of adrp, add, stp, ldr, ... are described here:
https://developer.arm.com/documentation/ddi0487/latest/

😆 Yes, I have that 8248(!) page doc. Chapter C4: A64 Instruction Set Encoding has all the details. Unlike PowerPC, it fails to neatly classifies & names the main encodings. Even so, this ought to suffice.

[tschuett]

Sorry for being slow.

For every adrp instruction you call fixupPage21.

inline uint64_t fixupPage21(uint64_t encoding, uint64_t va) {
  return (encoding | bitField(va, 12, 2, 29) | bitField(va, 14, 19, 5));
}

According to the ARMARM. the PC relative address is encoded into two sections. One starting at offset 5 and the width is 19. The second one starts at offset 29 and the width is 2. That matches the 2 and 29 and the 19 and 5 in fixupPage 21. I don't know yet how the explain the 12 and 14.

is encoded as "immhi:immlo" times 4096. This could explain the 12 and 14 for division.

[tschuett]

only for the b instruction, you use

inline uint64_t fixupBranch26(uint64_t encoding, uint64_t va) {
  return (encoding | bitField(va, 2, 26, 0));
}

The label is encoded in a slot starting at 0 and the width is 26, which matches the 0 and 26. The label is encoded as imm26 times 4, which could explain the 2. The 2 in bitField divides by 4.

[gkm]

lld/MachO/InputSection.cpp

55–56

pcrel handling requires the value of InputSection::getVA(), accessible here via this. Moving it into relocateOne means passing another argument. I think it's better to keep it here.

[int3]

lld/MachO/Arch/ARM64.cpp

49

What I was trying to ask was: when is the distinction between false and None important? After looking a bit more closely at the code, I guess we want None for things like ARM64_RELOC_UNSIGNED which can refer to both TLV and non-TLV symbols. Anyway, would be good to have a comment about it...

lld/MachO/Arch/X86_64.cpp

124–126

I think what @smeenai meant is, even though this parameter doesn't include the addend, it still isn't the VA when we are handling pcrel relocations.

lld/MachO/InputSection.cpp

55–56

my preference would be to keep it here but also to keep Val over VA.

[int3]

lld/MachO/Arch/ARM64.cpp

94

nit: AFAIK inline doesn't have a major impact on the compiler's inlining decisions and isn't necessary within cpp files. OTOH we should mark this static.

[gkm]

lld/MachO/Arch/ARM64.cpp

49

non-None means perform the validity check against sym->isTlv(). I populated the table according to the checks performed in lld/MachO/Arch/X86_64.cpp. It occurs to me now that more relocation types can likely be non-None, e.g., ARM64_RELOC_BRANCH26 should be false. As I get further with test cases and understand more, I might find others.

lld/MachO/InputSection.cpp

55–56

"value" is even better than "val", to further distinguish it visually from "va". 🚲

[gkm]

• rebase & amend according to review feedback

[int3]

I can add more tests to this base commit, or add them in follow-up commits.

I'm fine with either. @smeenai, what's the typical approach here?

lld/MachO/Arch/ARM64.cpp

128–131

ultra nit: I think there should be spaces around em dashes, i.e. --

also s/relococatable/relocatable/

lld/MachO/InputSection.cpp

55–56

while we're 🚲🏠ing... I think we should keep the referentVA name in lines 38-51 above and create a new value variable above line 54. That gives a clearer indication that we are handling a VA until we subtract the PC. Moreover, I think referentValue / referentVal is actually a bit of a misnomer, despite its parallels to referentVA -- "address of the referent" makes sense, but subtracting the PC doesn't give us the "value of the referent". relocValue or just value seems more accurate.

[int3]

lld/test/MachO/relocations-x86_84.s

1

nit: lld-elf's tests use x86-64 instead of x86_64 in their filenames

[gkm]

@smeenai and I agreed that this diff should contain a complete set of tests.

lld/MachO/Arch/ARM64.cpp

128–131

The real problem is that there are 4(!) em dashes in one tortuous run-on sentence. I reworded.

[gkm]

• amend according to review feedback

[gkm]

• move encoding bitfield comments outside their functions

[gkm]

• Factor skeletal paired-reloc support into a separate prerequisite diff
• ARM64RelocAttrs: drop type, add name, drop Optional<> from tlv
• s/getImplicitAddend/getAddend/ because it handles all forms of addend: implicit, explicit, paired.
• Add arm64 arch to test inputs MacOSX.sdk/usr/lib/lib*.tbd

[int3]

lld/MachO/Arch/ARM64.cpp

96–109

can we factor out the validation code into a separate function?

[gkm]

• Update according to refactored reloc handling

[int3]

lld/MachO/Arch/ARM64.cpp

120–123

I think there are some typos in this paragraph...

261–262

nit: can we have ldr in lowercase? since it's also in lowercase in e.g. stubHelperEntryCode above.

I also have a slight preference that the error messages have them in lowercase as well, but I guess it doesn't matter as much as long as things are consistent, and all-caps saves us from having to quote them for clarity

lld/MachO/Driver.cpp

166–167

ld64 seems to make unspecified arch an error when LTO is being used. I'm not sure why though. Feels like we should be able to infer the arch from our input files regardless

567

as the comment above states, we should always return true from this function when we have arm64. (ld64 will emit a warning if -no_pie is used on that arch.)

lld/MachO/InputSection.h

36 ↗

(On Diff #318138)

what's the motivation behind this change?

lld/MachO/SyntheticSections.cpp

378

so we can actually bind to __dso_handle?

[gkm]

lld/MachO/Arch/ARM64.cpp

261–262

The comment lines are copied directly and unaltered from the ARM manual.

lld/MachO/InputSection.h

36 ↗

(On Diff #318138)

That's a leftover from an aborted experiment.

lld/MachO/SyntheticSections.cpp

378

Yes, we do for arm64

[gkm]

• revise according to review feedback

[int3]

lld/MachO/Arch/ARM64.cpp

261–262

ah fair enough. Not sure if I missed it, but it'd be good to leave a comment somewhere that C6.2.131 refers to the section in the ARM manual.

lld/MachO/Driver.cpp

567

could you leave a TODO here so we remember to test this behavior?

lld/MachO/SyntheticSections.cpp

378

would be good to add a test, or at least leave a TODO here before landing it. I want to make sure I didn't miss a similar case for x86.

lld/test/MachO/relocations-x86_84.s

1

unaddressed nit :p

[int3]

(looks like there are failing tests)

[gkm]

• rebase & remove incomplete+failing test (will add later)

[gkm]

• rebase

[gkm]

• Make RelocAttrBits::LLVM_BITMASK_LARGEST_ENUMERATOR adequate to escape assertions.

[uabelho]

lld/MachO/Arch/ARM64.cpp

75

gcc warns about "type < 0" always being false since type is unsigned.
Can it be removed?

Similarly with the assert above, I suppose type >= 0 is always true and it can be removed.

[uabelho]

lld/MachO/Arch/ARM64.cpp

75

I removed the always true/false conditions in
https://reviews.llvm.org/rGcaff023b7799
to silence compiler warnings.

lld/MachO/Arch/ARM64.cpp

+//===- ARM64.cpp ---------------------------------------------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#include "InputFiles.h"
+#include "Symbols.h"
+#include "SyntheticSections.h"
+#include "Target.h"
+
+#include "lld/Common/ErrorHandler.h"
+#include "llvm/ADT/Optional.h"
+#include "llvm/BinaryFormat/MachO.h"
+#include "llvm/Support/Endian.h"
+
+using namespace llvm::MachO;
+using namespace llvm::support::endian;
+using namespace lld;
+using namespace lld::macho;
+
+namespace {
+
+struct ARM64 : TargetInfo {
+  ARM64();
+
+  uint64_t getImplicitAddend(MemoryBufferRef, const section_64 &,
+                             const relocation_info &) const override;
+  void relocateOne(uint8_t *loc, const Reloc &, uint64_t val) const override;
+
+  void writeStub(uint8_t *buf, const macho::Symbol &) const override;
+  void writeStubHelperHeader(uint8_t *buf) const override;
+  void writeStubHelperEntry(uint8_t *buf, const DylibSymbol &,
+                            uint64_t entryAddr) const override;
+
+  void prepareSymbolRelocation(lld::macho::Symbol *, const InputSection *,
+                               const Reloc &) override;
+  uint64_t resolveSymbolVA(uint8_t *buf, const lld::macho::Symbol &,
+                           uint8_t type) const override;
+};
+
+} // namespace
+
+struct ARM64RelocAttrs {
+  RelocationInfoType type;
+  llvm::Optional<bool> TLV;
+  bool PCrel;
+  uint32_t lengths;
+};
+
+static ARM64RelocAttrs arm64RelocAttrs[] = {
+    {ARM64_RELOC_UNSIGNED, llvm::None, false, 8},
+    {ARM64_RELOC_SUBTRACTOR, llvm::None, false, 8},
+    {ARM64_RELOC_BRANCH26, llvm::None, true, 4},
+    {ARM64_RELOC_PAGE21, llvm::None, true, 4},
+    {ARM64_RELOC_PAGEOFF12, llvm::None, false, 4},
+    {ARM64_RELOC_GOT_LOAD_PAGE21, false, true, 4},
+    {ARM64_RELOC_GOT_LOAD_PAGEOFF12, false, false, 4},
+    {ARM64_RELOC_POINTER_TO_GOT, false, true, 4},
+    {ARM64_RELOC_TLVP_LOAD_PAGE21, true, true, 4},
+    {ARM64_RELOC_TLVP_LOAD_PAGEOFF12, true, false, 4},
+    {ARM64_RELOC_ADDEND, llvm::None, false, 4},
+};
+
+uint64_t ARM64::getImplicitAddend(MemoryBufferRef mb, const section_64 &sec,
+                                  const relocation_info &rel) const {
+  ARM64RelocAttrs &relocAttrs = arm64RelocAttrs[rel.r_type];
+  assert(rel.r_type == relocAttrs.type);
+  assert(rel.r_pcrel == relocAttrs.PCrel);
+  const auto *buf = reinterpret_cast<const uint8_t *>(mb.getBufferStart());
+  const uint8_t *loc = buf + sec.offset + rel.r_address;
+
+  if (isThreadLocalVariables(sec.flags) && rel.r_type != ARM64_RELOC_UNSIGNED)
+    error("relocations in thread-local variable sections must be "
+          "ARM64_RELOC_UNSIGNED");
+
+  switch (rel.r_length) {
+  case 0:
+    return *loc;
+  case 1:
+    return read16le(loc);
+  case 2:
+    return read32le(loc);
+  case 3:
+    return read64le(loc);
+  default:
+    llvm_unreachable("invalid r_length");
+  }
+}
+
+inline uint64_t bitField(uint64_t value, int right, int width, int left) {
+  return ((value >> right) & ((1 << width) - 1)) << left;
+}
+
+void ARM64::relocateOne(uint8_t *loc, const Reloc &r, uint64_t va) const {
+  // For instruction fixups, r.addend contains the base encoding
+  uint64_t fixup = r.addend;
+  switch (r.type) {
+  case ARM64_RELOC_BRANCH26:
+    assert((va & 0x3) == 0);
+    fixup |= bitField(va, 2, 26, 0);
+    break;
+  case ARM64_RELOC_UNSIGNED:
+    assert(fixup == 0);
+    fixup |= va;
+    break;
+  case ARM64_RELOC_PAGE21:
+  case ARM64_RELOC_GOT_LOAD_PAGE21:
+  case ARM64_RELOC_TLVP_LOAD_PAGE21:
+    fixup |= bitField(va, 12, 2, 29) | bitField(va, 14, 19, 5);
+    break;
+  case ARM64_RELOC_PAGEOFF12:
+  case ARM64_RELOC_TLVP_LOAD_PAGEOFF12:
+  case ARM64_RELOC_GOT_LOAD_PAGEOFF12:
+    fixup |= bitField(va, 0, 12, 10);
+    break;
+  case ARM64_RELOC_POINTER_TO_GOT:
+  case ARM64_RELOC_SUBTRACTOR:
+  case ARM64_RELOC_ADDEND:
+  default:
+    llvm_unreachable("unexpected relocation type");
+  }
+
+  switch (r.length) {
+  case 2:
+    write32le(loc, fixup);
+    break;
+  case 3:
+    write64le(loc, fixup);
+    break;
+  default:
+    llvm_unreachable("invalid r_length");
+  }
+}
+
+void ARM64::writeStub(uint8_t *buf, const macho::Symbol &sym) const {
+  assert(false); // TODO(gkm): implement
+}
+
+void ARM64::writeStubHelperHeader(uint8_t *buf) const {
+  assert(false); // TODO(gkm): implement
+}
+
+void ARM64::writeStubHelperEntry(uint8_t *buf, const DylibSymbol &sym,
+                                 uint64_t entryAddr) const {
+  assert(false); // TODO(gkm): implement
+}
+
+void ARM64::prepareSymbolRelocation(lld::macho::Symbol *sym,
+                                    const InputSection *isec, const Reloc &r) {
+  ARM64RelocAttrs &relocAttrs = arm64RelocAttrs[r.type];
+  assert(r.type == relocAttrs.type);
+  assert(relocAttrs.TLV == llvm::None || relocAttrs.TLV == sym->isTlv());
+  assert((relocAttrs.lengths & (1 << r.length)) != 0);
+
+  switch (r.type) {
+  case ARM64_RELOC_GOT_LOAD_PAGE21:
+    if (needsBinding(sym))
+      in.got->addEntry(sym);
+    break;
+  case ARM64_RELOC_TLVP_LOAD_PAGE21:
+    if (needsBinding(sym))
+      in.tlvPointers->addEntry(sym);
+    break;
+  case ARM64_RELOC_POINTER_TO_GOT:
+    in.got->addEntry(sym);
+    break;
+  case ARM64_RELOC_BRANCH26:
+    prepareBranchTarget(sym);
+    break;
+  case ARM64_RELOC_UNSIGNED:
+    addNonLazyBindingEntries(sym, isec, r.offset, r.addend);
+    break;
+  case ARM64_RELOC_SUBTRACTOR:
+    fatal("TODO: handle relocation type " + std::to_string(r.type));
+    break;
+  case ARM64_RELOC_PAGE21:
+  case ARM64_RELOC_PAGEOFF12:
+  case ARM64_RELOC_TLVP_LOAD_PAGEOFF12:
+  case ARM64_RELOC_GOT_LOAD_PAGEOFF12:
+  case ARM64_RELOC_ADDEND:
+    break;
+  default:
+    llvm_unreachable("unexpected relocation type");
+  }
+}
+
+uint64_t ARM64::resolveSymbolVA(uint8_t *buf, const lld::macho::Symbol &sym,
+                                uint8_t type) const {
+  switch (type) {
+  case ARM64_RELOC_GOT_LOAD_PAGE21:
+  case ARM64_RELOC_GOT_LOAD_PAGEOFF12:
+    return in.got->addr + sym.gotIndex * WordSize;
+  case ARM64_RELOC_BRANCH26:
+    if (sym.isInStubs())
+      return in.stubs->addr + sym.stubsIndex * sizeof(stub);
+    return sym.getVA();
+  case ARM64_RELOC_UNSIGNED:
+  case ARM64_RELOC_PAGE21:
+  case ARM64_RELOC_PAGEOFF12:
+    return sym.getVA();
+  case ARM64_RELOC_TLVP_LOAD_PAGE21:
+  case ARM64_RELOC_TLVP_LOAD_PAGEOFF12:
+    if (sym.isInGot())
+      return in.tlvPointers->addr + sym.gotIndex * WordSize;
+    assert(isa<Defined>(&sym));
+    assert(false); // TODO(gkm): convert insn?
+    break;
+  case ARM64_RELOC_SUBTRACTOR:
+    fatal("TODO: handle relocation type " + std::to_string(type));
+  default:
+    llvm_unreachable("Unexpected relocation type");
+  }
+}
+
+ARM64::ARM64() {
+  cpuType = CPU_TYPE_ARM64;
+  cpuSubtype = CPU_SUBTYPE_ARM64_ALL;
+
+  stubSize = sizeof(stub);
+  stubHelperHeaderSize = sizeof(stubHelperHeader);
+  stubHelperEntrySize = sizeof(stubHelperEntry);
+}
+
+TargetInfo *macho::createARM64TargetInfo() {
+  static ARM64 t;
+  return &t;
+}

lld/MachO/Arch/X86_64.cpp

case 2:
     return read32le(loc);
   case 3:
     return read64le(loc);
   default:
     llvm_unreachable("invalid r_length");
   }
 }
 
-void X86_64::relocateOne(uint8_t *loc, const Reloc &r, uint64_t val) const {
+void X86_64::relocateOne(uint8_t *loc, const Reloc &r, uint64_t va) const {
+  // For instruction fixups, r.addend contains the base encoding
+  va += r.addend;
   switch (r.type) {
   case X86_64_RELOC_BRANCH:
   case X86_64_RELOC_SIGNED:
   case X86_64_RELOC_SIGNED_1:
   case X86_64_RELOC_SIGNED_2:
   case X86_64_RELOC_SIGNED_4:
   case X86_64_RELOC_GOT_LOAD:
   case X86_64_RELOC_GOT:
   case X86_64_RELOC_TLV:
     // These types are only used for pc-relative relocations, so offset by 4
     // since the RIP has advanced by 4 at this point. This is only valid when
     // r_length = 2, which is enforced by validateLength().
-    val -= 4;
+    va -= 4;
     break;
   case X86_64_RELOC_UNSIGNED:
     break;
   default:
     llvm_unreachable(
         "getImplicitAddend should have flagged all unhandled relocation types");
   }
 
   switch (r.length) {
   case 0:
-    *loc = val;
+    *loc = va;
     break;
   case 1:
-    write16le(loc, val);
+    write16le(loc, va);
     break;
   case 2:
-    write32le(loc, val);
+    write32le(loc, va);
     break;
   case 3:
-    write64le(loc, val);
+    write64le(loc, va);
     break;
   default:
     llvm_unreachable("invalid r_length");
   }
 }
 
 // The following methods emit a number of assembly sequences with RIP-relative
 // addressing. Note that RIP-relative addressing on X86-64 has the RIP pointing

lld/MachO/CMakeLists.txt

 set(LLVM_TARGET_DEFINITIONS Options.td)
 tablegen(LLVM Options.inc -gen-opt-parser-defs)
 add_public_tablegen_target(MachOOptionsTableGen)
 
 include_directories(${LLVM_MAIN_SRC_DIR}/../libunwind/include)
 
 add_lld_library(lldMachO2
   Arch/X86_64.cpp
+  Arch/ARM64.cpp
   UnwindInfoSection.cpp
   Driver.cpp
   DriverUtils.cpp
   ExportTrie.cpp
   InputFiles.cpp
   InputSection.cpp
   MergedOutputSection.cpp
   ObjC.cpp

lld/MachO/Driver.cpp

static Optional<std::string> findFramework(StringRef name) {
   return {};
 }
 
 static TargetInfo *createTargetInfo(opt::InputArgList &args) {
   StringRef arch = args.getLastArgValue(OPT_arch, "x86_64");
   config->arch = llvm::MachO::getArchitectureFromName(
       args.getLastArgValue(OPT_arch, arch));
   switch (config->arch) {
   case llvm::MachO::AK_x86_64:
   case llvm::MachO::AK_x86_64h:
     return createX86_64TargetInfo();
+  case llvm::MachO::AK_arm64:
+  case llvm::MachO::AK_arm64e:
+    return createARM64TargetInfo();
   default:
     fatal("missing or unsupported -arch " + arch);
   }
 }
 
 static bool warnIfNotDirectory(StringRef option, StringRef path) {
   if (!fs::exists(path)) {
     warn("directory not found for option -" + option + path);
for (StringRef rest : args::getLines(mbref)) {
     if (!arch.empty()) {
       if (!isArchString(arch)) {
         error("invalid arch \"" + arch + "\" in order file: expected one of " +
               llvm::join(archNames, ", "));
         continue;
       }
 
       // TODO: Update when we extend support for other archs
-      if (arch != "x86_64")
+      if (arch != "x86_64" && arch != "arm64")
         continue;
     }
 
     if (!objectFile.empty() && !objectFile.endswith(".o")) {
       error("invalid object file name \"" + objectFile +
             "\" in order file: should end with .o");
       continue;
     }
case OPT_grp_ignored:
     break;
   default:
     warn("Option `" + opt.getPrefixedName() +
          "' is not yet implemented. Stay tuned...");
     break;
   }
 }
 
 bool macho::link(llvm::ArrayRef<const char *> argsArr, bool canExitEarly,
                  raw_ostream &stdoutOS, raw_ostream &stderrOS) {
   lld::stdoutOS = &stdoutOS;
   lld::stderrOS = &stderrOS;
 
   stderrOS.enable_colors(stderrOS.has_colors());
   // TODO: Set up error handler properly, e.g. the errorLimitExceededMsg
 
   errorHandler().cleanupCallback = []() { freeArena(); };

lld/MachO/InputSection.cpp

if (auto *referentSym = r.referent.dyn_cast<Symbol *>()) {
         // instead of as absolute addresses.
         if (auto *defined = dyn_cast<Defined>(referentSym))
           referentVA -= defined->isec->parent->addr;
       }
     } else if (auto *referentIsec = r.referent.dyn_cast<InputSection *>()) {
       referentVA = referentIsec->getVA();
     }
 
-    uint64_t referentVal = referentVA + r.addend;
     if (r.pcrel)
-      referentVal -= getVA() + r.offset;
-    target->relocateOne(buf + r.offset, r, referentVal);
+      referentVA -= getVA() + r.offset;
+    target->relocateOne(buf + r.offset, r, referentVA);
   }
 }
 
 std::string lld::toString(const InputSection *isec) {
   return (toString(isec->file) + ":(" + isec->name + ")").str();
 }

lld/MachO/SyntheticSections.cpp

 
 uint64_t MachHeaderSection::getSize() const {
   return sizeof(MachO::mach_header_64) + sizeOfCmds + config->headerPad;
 }
 
 void MachHeaderSection::writeTo(uint8_t *buf) const {
   auto *hdr = reinterpret_cast<MachO::mach_header_64 *>(buf);
   hdr->magic = MachO::MH_MAGIC_64;
-  hdr->cputype = MachO::CPU_TYPE_X86_64;
-  hdr->cpusubtype = MachO::CPU_SUBTYPE_X86_64_ALL | MachO::CPU_SUBTYPE_LIB64;
+  hdr->cputype = target->cpuType;
+  hdr->cpusubtype = target->cpuSubtype | MachO::CPU_SUBTYPE_LIB64;
   hdr->filetype = config->outputType;
   hdr->ncmds = loadCommands.size();
   hdr->sizeofcmds = sizeOfCmds;
   hdr->flags = MachO::MH_NOUNDEFS | MachO::MH_DYLDLINK | MachO::MH_TWOLEVEL;
 
   if (config->outputType == MachO::MH_DYLIB && !config->hasReexports)
     hdr->flags |= MachO::MH_NO_REEXPORTED_DYLIBS;
 
if (auto *dysym = dyn_cast<DylibSymbol>(sym)) {
     if (dysym->isWeakDef())
       in.weakBinding->addEntry(sym, section, offset, addend);
   } else if (auto *defined = dyn_cast<Defined>(sym)) {
     in.rebase->addEntry(section, offset);
     if (defined->isWeakDef() && defined->isExternal())
       in.weakBinding->addEntry(sym, section, offset, addend);
   } else if (isa<DSOHandle>(sym)) {
     error("cannot bind to " + DSOHandle::name);
   } else {
     // Undefined symbols are filtered out in scanRelocations(); we should never
     // get here
     llvm_unreachable("cannot bind to an undefined symbol");
   }
 }
 
 StubsSection::StubsSection()
     : SyntheticSection(segment_names::text, "__stubs") {

lld/MachO/Target.h

public:
   uint32_t cpuSubtype;
 
   size_t stubSize;
   size_t stubHelperHeaderSize;
   size_t stubHelperEntrySize;
 };
 
 TargetInfo *createX86_64TargetInfo();
+TargetInfo *createARM64TargetInfo();
 
 extern TargetInfo *target;
 
 } // namespace macho
 } // namespace lld
 
 #endif

lld/test/MachO/relocations-arm64.s

+# REQUIRES: aarch64
+# RUN: rm -fr %t
+# RUN: split-file %s %t
+
+# RUN: llvm-mc -filetype=obj -triple=arm64-apple-ios %t/main.s -o %t/main.o
+# RUN: llvm-mc -filetype=obj -triple=arm64-apple-ios %t/write.s -o %t/write.o
+# RUN: %lld -lSystem -arch arm64 -o %t/main %t/main.o %t/write.o
+# RUN: llvm-objdump --section-headers --syms -d %t/main | FileCheck %s
+
+# CHECK-LABEL: Sections:
+# CHECK:       __cstring {{[0-9a-f]+}} {{([[:xdigit:]]{13})}}[[#%.3x, CSTRING_OFF:]] DATA
+
+# CHECK-LABEL: SYMBOL TABLE:
+# CHECK:       [[#%x,FUNC_ADDR:]] {{.*}} _write
+
+# CHECK-LABEL: <_main>:
+## Test ARM64_RELOC_PAGE21 / ARM64_RELOC_PAGEOFF12
+# CHECK:       adrp x1, #0
+# CHECK-NEXT:  add x1, x1, #[[#%u, CSTRING_OFF]]
+## Test ARM64_RELOC_BRANCH26
+# CHECK:       bl 0x[[#%x, FUNC_ADDR]] <_write>
+
+#--- main.s
+.section __TEXT,__text
+.globl _main
+.p2align 2
+_main:
+  stp x29, x30, [sp, #-16]!
+  mov x29, sp
+Lloh0:
+  adrp x1, l_.str@PAGE
+Lloh1:
+  add x1, x1, l_.str@PAGEOFF
+  orr w0, wzr, #0x1
+  mov w2, #13
+  bl _write
+  mov w0, #0
+  ldp x29, x30, [sp], #16
+  ret
+
+.section __TEXT,__cstring
+l_.str:
+  .asciz "hello world\n"
+
+#--- write.s
+.globl _write
+.p2align 2
+_write:
+  ret

lld/test/MachO/relocations-x86_84.s

 # REQUIRES: x86
 # RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %s -o %t.o
 # RUN: %lld -lSystem -o %t %t.o
 # RUN: llvm-objdump --section-headers --syms -d %t | FileCheck %s
 
 # CHECK-LABEL: Sections:
 # CHECK:       __cstring {{[0-9a-z]+}} [[#%x, CSTRING_ADDR:]]
 
 # CHECK-LABEL: SYMBOL TABLE:

lld/test/MachO/relocations.s

-# REQUIRES: x86
-# RUN: llvm-mc -filetype=obj -triple=x86_64-apple-darwin %s -o %t.o
-# RUN: %lld -lSystem -o %t %t.o
-# RUN: llvm-objdump --section-headers --syms -d %t | FileCheck %s
-
-# CHECK-LABEL: Sections:
-# CHECK:       __cstring {{[0-9a-z]+}} [[#%x, CSTRING_ADDR:]]
-
-# CHECK-LABEL: SYMBOL TABLE:
-# CHECK:       [[#%x, F_ADDR:]] {{.*}} _f
-
-# CHECK-LABEL: <_main>:
-## Test X86_64_RELOC_BRANCH
-# CHECK:       callq 0x[[#%x, F_ADDR]] <_f>
-## Test extern (symbol) X86_64_RELOC_SIGNED
-# CHECK:       leaq [[#%u, STR_OFF:]](%rip), %rsi
-# CHECK-NEXT:  [[#%x, CSTRING_ADDR - STR_OFF]]
-## Test non-extern (section) X86_64_RELOC_SIGNED
-# CHECK:       leaq [[#%u, LSTR_OFF:]](%rip), %rsi
-# CHECK-NEXT:  [[#%x, CSTRING_ADDR + 22 - LSTR_OFF]]
-
-# RUN: llvm-objdump --section=__const --full-contents %t | FileCheck %s --check-prefix=NONPCREL
-# NONPCREL:      Contents of section __DATA,__const:
-# NONPCREL-NEXT: 100001000 f0030000 01000000 f0030000 01000000
-
-.section __TEXT,__text
-.globl _main, _f
-_main:
-  callq _f # X86_64_RELOC_BRANCH
-  mov $0, %rax
-  ret
-
-_f:
-  movl $0x2000004, %eax # write() syscall
-  mov $1, %rdi # stdout
-  leaq _str(%rip), %rsi # Generates a X86_64_RELOC_SIGNED pcrel symbol relocation
-  mov $21, %rdx # length of str
-  syscall
-
-  movl $0x2000004, %eax # write() syscall
-  mov $1, %rdi # stdout
-  leaq L_.str(%rip), %rsi # Generates a X86_64_RELOC_SIGNED pcrel section relocation
-  mov $15, %rdx # length of str
-  syscall
-
-  movl $0x2000004, %eax # write() syscall
-  mov $1, %rdi # stdout
-  movq L_.ptr_1_to_str(%rip), %rsi
-  mov $15, %rdx # length of str
-  syscall
-  ret
-
-.section __TEXT,__cstring
-## References to this generate a symbol relocation
-_str:
-  .asciz "Local defined symbol\n"
-## References to this generate a section relocation
-L_.str:
-  .asciz "Private symbol\n"
-
-.section __DATA,__const
-## These generate X86_64_RELOC_UNSIGNED non-pcrel section relocations
-L_.ptr_1_to_str:
-  .quad L_.str
-L_.ptr_2_to_str:
-  .quad L_.str

lld/test/lit.cfg.py

 # Set if host-cxxabi's demangler can handle target's symbols.
 if platform.system() not in ['Windows']:
     config.available_features.add('demangler')
 
 llvm_config.feature_config(
     [('--build-mode', {'DEBUG': 'debug'}),
      ('--assertion-mode', {'ON': 'asserts'}),
      ('--targets-built', {'AArch64': 'aarch64',
+                          'ARM64': 'arm64',
                           'AMDGPU': 'amdgpu',
                           'ARM': 'arm',
                           'AVR': 'avr',
                           'Hexagon': 'hexagon',
                           'Mips': 'mips',
                           'MSP430': 'msp430',
                           'PowerPC': 'ppc',
                           'RISCV': 'riscv',