[AArch64] Match the windows canonical callee saved register order

[mstorsjo]

Summary

On windows, the callee saved registers in a canonical prologue are ordered starting from a lower register number at a lower stack address (with the possible gap for aligning the stack at the top); this is the opposite order that llvm normally produces.

To achieve this, reverse the order of the registers in the assignCalleeSavedSpillSlots callback, and adjust the code for matching up register pairs (to expect them in reverse order). In order to pair them properly when iterating in reverse order, restrict pairing pairs starting with an odd numbered GPR (e.g. for [x19, x20, x21], iterated over backwards, don't pair up x21 with x20, but leave x21 alone and pair x20 with x19).

This allows generated prologs more often to match the format that allows the unwind info to be written as packed info.

I've got an alternative implementation of the same, that keeps the register iteration order normal, but changes computeCalleeSaveRegisterPairs to lay things from the bottom up, instead of top down (contrary to the generic code in PrologEpilogInserter, that still lays out the matching stack objects top down). This results in a slightly smaller code change, but has the effect that the register names for the CSR stack objects (visible in MIR) actually mismatch where the registers really are saved.

I've also got two more patches coming up on top of this one, but I'm holding off the other ones until this one is settled, as one of the later ones depend on the exact form of this one.

With all of them applied, a 228 KB xdata section shrinks by 74 KB thanks to being able to write packed unwind info, ending up with smaller xdata than the corresponding section for an x86_64 build of the same DLL.

[mstorsjo]

With all of them applied, a 228 KB xdata section shrinks by 74 KB thanks to being able to write packed unwind info, ending up with smaller xdata than the corresponding section for an x86_64 build of the same DLL.

Actually, I just found another hopefully pretty simple fix that gets rid of another 46 KB - so the gains in the end are pretty notable!

[efriedma]

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

2018

This if ends up being a little confusing to read... maybe worth duplicating the if (Reg2 == Reg1 + 1) check into both the integer and fp branches of the if statement.

2211

Do we really need to check NeedsWinCFI here? It seems like the rounding should be a property of the chosen stack layout, which should already be determined at this point.

[mstorsjo]

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

2018

Hmm, maybe...

I'm a bit dissatisfied with this solution, as it misses some pairing opportunities: E.g. if saving only x20 and x21, but not x19, this code wouldn't manage to pair x20 and x21 - as when iterating over them in the top-to-bottom order, when inspecting x21, it'll choose not to pair it with x20, as it expects x20 to be paired with x19.

But I'm a bit out of ideas of a good way of achieving that, without making a huge mess in the generic code in computeCalleeSaveRegisterPairs...

On the other hand, I'm not sure if that's much of a practical issue that happens often, other than in pathological cases?

2211

We do: If we need to save the set of x19, d8 and d9, the windows stack layout of that is (bottom-up) x19, (d8, d9), gap. When iterating backwards starting from the top, we start out with d9 and pair it with d8 - but we need to add the alignment (to the d9 stack object) to get the gap here at the top. But the pair d8,d9 aren't aligned to a 16 byte boundary themselves.

[efriedma]

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

2018

Probably rare; the standard register allocation order will use x19 before x20, so ignoring weird edge cases, the only way to get into this situation is if something explicitly clobbers x20. Which probably means inline asm, since there isn't really any other way to trigger that reliably.

On the other hand, I think computeCalleeSaveRegisterPairs would be easier to follow if we actually iterated over the registers in the right order. The other changes are basically working around the fact that we're iterating in the wrong order. So maybe worth doing even if we don't really expect any significant optimization benefit. Hopefully it's not that complicated?

[mstorsjo]

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

2018

That was actually my original approach, and I have a separate version of this patch that does exactly that.

The reason why I preferred this one, is that it keeps the association between stack objects (as allocated and laid out by PrologEpilogInserter's calculateFrameObjectOffsets) more straightforward.

But I can put that alternative version up for review and point out the (potentially?) problematic mismatch there.

[mstorsjo]

Superseded by D88677.

llvm/lib/Target/AArch64/AArch64FrameLowering.h

restoreCalleeSavedRegisters(MachineBasicBlock &MBB,
                               const TargetRegisterInfo *TRI) const override;
 
   /// Can this function use the red zone for local allocations.
   bool canUseRedZone(const MachineFunction &MF) const;
 
   bool hasFP(const MachineFunction &MF) const override;
   bool hasReservedCallFrame(const MachineFunction &MF) const override;
 
+  bool
+  assignCalleeSavedSpillSlots(MachineFunction &MF,
+                              const TargetRegisterInfo *TRI,
+                              std::vector<CalleeSavedInfo> &CSI) const override;
+
   void determineCalleeSaves(MachineFunction &MF, BitVector &SavedRegs,
                             RegScavenger *RS) const override;
 
   /// Returns true if the target will correctly handle shrink wrapping.
   bool enableShrinkWrapping(const MachineFunction &MF) const override {
     return true;
   }
 

llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

   // https://docs.microsoft.com/en-us/cpp/build/arm64-exception-handling
 
   // TODO: LR can be paired with any register.  We don't support this yet in
   // the MCLayer.  We need to add support for the save_lrpair unwind code.
   if (Reg2 == AArch64::FP)
     return true;
   if (!NeedsWinCFI)
     return false;
+  // When the list of callee saved registers is backwards, we must choose
+  // not to pair e.g. x20+x21, as x20 should be paired with x19. If there's
+  // gaps in the list of callee saved registers, this might end up
+  // inefficient, but normally it should produce the canonical prologue format
+  // that matches the packed unwind format.
+  if (Reg1 >= AArch64::X0 && Reg1 <= AArch64::X28) {
+    int N = Reg1 - AArch64::X0;
+    // Reject pairs if the first reg isn't an odd register
+    if (N % 2 != 1)
+      return true;
+  } else if (Reg1 >= AArch64::D0 && Reg1 <= AArch64::D31) {
+    // Reject pairs if the first reg isn't an even register
+    int N = Reg1 - AArch64::D0;
+    if (N % 2 != 0)
+      return true;
+  } else if (Reg1 == AArch64::FP && Reg2 == AArch64::LR) {
+    return false;
+  } else {
+    return true;
+  }
   if (Reg2 == Reg1 + 1)
     return false;
   return true;
 }
 
 /// Returns true if Reg1 and Reg2 cannot be paired using a ldp/stp instruction.
 /// WindowsCFI requires that only consecutive registers can be paired.
 /// LR and FP need to be allocated together when the frame needs to save

       RPI.Type = RegPairInfo::ZPR;
     else if (AArch64::PPRRegClass.contains(RPI.Reg1))
       RPI.Type = RegPairInfo::PPR;
     else
       llvm_unreachable("Unsupported register class.");
 
     // Add the next reg to the pair if it is in the same register class.
     if (i + 1 < Count) {
+      unsigned CurReg = RPI.Reg1;
       unsigned NextReg = CSI[i + 1].getReg();
+      if (NeedsWinCFI)
+        std::swap(CurReg, NextReg);
       switch (RPI.Type) {
       case RegPairInfo::GPR:
         if (AArch64::GPR64RegClass.contains(NextReg) &&
-            !invalidateRegisterPairing(RPI.Reg1, NextReg, IsWindows, NeedsWinCFI,
-                                       NeedsFrameRecord))
+            !invalidateRegisterPairing(CurReg, NextReg, IsWindows, NeedsWinCFI,
+                                       NeedsFrameRecord)) {
+          RPI.Reg1 = CurReg;
           RPI.Reg2 = NextReg;
+        }
         break;
       case RegPairInfo::FPR64:
-        if (AArch64::FPR64RegClass.contains(NextReg) &&
-            !invalidateWindowsRegisterPairing(RPI.Reg1, NextReg, NeedsWinCFI))
+        if (AArch64::FPR64RegClass.contains(CurReg) &&
+            !invalidateWindowsRegisterPairing(CurReg, NextReg, NeedsWinCFI)) {
+          RPI.Reg1 = CurReg;
           RPI.Reg2 = NextReg;
+        }
         break;
       case RegPairInfo::FPR128:
-        if (AArch64::FPR128RegClass.contains(NextReg))
+        if (AArch64::FPR128RegClass.contains(NextReg)) {
+          RPI.Reg1 = CurReg;
           RPI.Reg2 = NextReg;
+        }
         break;
       case RegPairInfo::PPR:
       case RegPairInfo::ZPR:
         break;
       }
     }
 
     // If either of the registers to be saved is the lr register, it means that

     else
       ByteOffset -= RPI.isPaired() ? 2 * Scale : Scale;
 
     assert(!(RPI.isScalable() && RPI.isPaired()) &&
            "Paired spill/fill instructions don't exist for SVE vectors");
 
     // Round up size of non-pair to pair size if we need to pad the
     // callee-save area to ensure 16-byte alignment.
-    if (AFI->hasCalleeSaveStackFreeSpace() && !FixupDone &&
-        !RPI.isScalable() && RPI.Type != RegPairInfo::FPR128 &&
-        !RPI.isPaired()) {
-      FixupDone = true;
-      ByteOffset -= 8;
-      assert(ByteOffset % 16 == 0);
-      assert(MFI.getObjectAlign(RPI.FrameIdx) <= Align(16));
-      MFI.setObjectAlignment(RPI.FrameIdx, Align(16));
+    if (AFI->hasCalleeSaveStackFreeSpace() && !FixupDone && !RPI.isScalable() &&
+        RPI.Type != RegPairInfo::FPR128) {
+      bool DoFixup = false;
+      if (!NeedsWinCFI) {
+        DoFixup = !RPI.isPaired();
+      } else { // NeedsWinCFI
+        // For WinCFI, do the fixup before the first register; in WinCFI
+        // one can have register pairs that aren't aligned to 16 bytes.
+        DoFixup = true;
+      }
+      if (DoFixup) {
+        FixupDone = true;
+        ByteOffset -= 8;
+        if (!NeedsWinCFI)
+          assert(ByteOffset % 16 == 0);
+        assert(MFI.getObjectAlign(RPI.FrameIdx) <= Align(16));
+        MFI.setObjectAlignment(RPI.FrameIdx, Align(16));
+      }
     }
 
     int Offset = RPI.isScalable() ? ScalableByteOffset : ByteOffset;
     assert(Offset % Scale == 0);
     RPI.Offset = Offset / Scale;
 
     assert(((!RPI.isScalable() && RPI.Offset >= -64 && RPI.Offset <= 63) ||
             (RPI.isScalable() && RPI.Offset >= -256 && RPI.Offset <= 255)) &&

 
   // Round up to register pair alignment to avoid additional SP adjustment
   // instructions.
   AFI->setCalleeSavedStackSize(AlignedCSStackSize);
   AFI->setCalleeSaveStackHasFreeSpace(AlignedCSStackSize != CSStackSize);
   AFI->setSVECalleeSavedStackSize(alignTo(SVECSStackSize, 16));
 }
 
+bool AArch64FrameLowering::assignCalleeSavedSpillSlots(
+    MachineFunction &MF, const TargetRegisterInfo *TRI,
+    std::vector<CalleeSavedInfo> &CSI) const {
+  bool NeedsWinCFI = needsWinCFI(MF);
+  // To match the canonical windows frame layout, reverse the list of
+  // callee saved registers to get them laid out in the desired order
+  // (lower registers at a lower stack address).
+  if (NeedsWinCFI)
+    std::reverse(CSI.begin(), CSI.end());
+  // Let the generic code do the rest of the setup.
+  return false;
+}
+
 bool AArch64FrameLowering::enableStackSlotScavenging(
     const MachineFunction &MF) const {
   const AArch64FunctionInfo *AFI = MF.getInfo<AArch64FunctionInfo>();
   return AFI->hasCalleeSaveStackFreeSpace();
 }
 
 /// returns true if there are any SVE callee saves.
 static bool getSVECalleeSaveSlotRange(const MachineFrameInfo &MFI,

llvm/test/CodeGen/AArch64/seh-finally.ll

; CHECK: bl      foo
   call void @foo(i32 %1)
   ret void
 }
 
 ; Test SEH when stack realignment is needed in case highly aligned stack objects are present.
 define void @stack_realign() #0 personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*) {
 entry:
 ; CHECK-LABEL: stack_realign
-; CHECK: mov     x29, sp
+; CHECK: add     x29, sp, #8
 ; CHECK: sub     x9, sp, #16
 ; CHECK: and     sp, x9, #0xffffffffffffffe0
 ; CHECK: mov     x19, sp
 ; CHECK: mov     x0, #-2
-; CHECK: stur    x0, [x29, #32]
+; CHECK: stur    x0, [x29, #24]
 ; CHECK: .set .Lstack_realign$frame_escape_0, 0
 ; CHECK: ldr     w0, [x19]
 ; CHECK: bl      foo
 
   %o = alloca %struct.S, align 32
   call void (...) @llvm.localescape(%struct.S* %o)
   %x = getelementptr inbounds %struct.S, %struct.S* %o, i32 0, i32 0
   %0 = load i32, i32* %x, align 32
; CHECK: bl      foo
   call void @foo(i32 %1)
   ret void
 }
 
 ; Test when both vla's and highly aligned objects are present on stack.
 define void @vla_and_realign(i32 %n) #0 personality i8* bitcast (i32 (...)* @__C_specific_handler to i8*) {
 entry:
 ; CHECK-LABEL: vla_and_realign
-; CHECK: mov     x29, sp
+; CHECK: add     x29, sp, #8
 ; CHECK: sub     x9, sp, #48
 ; CHECK: and     sp, x9, #0xffffffffffffffe0
 ; CHECK: mov     x19, sp
 ; CHECK: mov     x1, #-2
-; CHECK: stur    x1, [x29, #32]
+; CHECK: stur    x1, [x29, #24]
 ; CHECK: .set .Lvla_and_realign$frame_escape_0, 32
-; CHECK: str     w0, [x29, #44]
-; CHECK: ldr     w8, [x29, #44]
+; CHECK: str     w0, [x29, #36]
+; CHECK: ldr     w8, [x29, #36]
 ; CHECK: mov     x9, sp
-; CHECK: str     x9, [x29, #24]
+; CHECK: str     x9, [x29, #16]
 ; CHECK: str     x8, [x19, #24]
 ; CHECK: ldr     w0, [x19, #32]
 ; CHECK: bl      foo
 
   %n.addr = alloca i32, align 4
   %o = alloca %struct.S, align 32
   %saved_stack = alloca i8*, align 8
   %__vla_expr0 = alloca i64, align 8

llvm/test/CodeGen/AArch64/sponentry.ll

define dso_local void @foo([24 x i64]*) {
   %8 = bitcast i64* %7 to i8*
   %9 = call i32 @_setjmpex(i8* %8, i8* %5)
   store i32 %9, i32* %3, align 4
   ret void
 }
 
 ; CHECK: foo:
 ; CHECK: sub     sp, sp, #448
-; CHECK: add     x29, sp, #416
-; CHECK: add     x1, x29, #32
+; CHECK: add     x29, sp, #424
+; CHECK: add     x1, x29, #24
 ; CHECK: bl      _setjmpex
 
 ; NOFP: sub     sp, sp, #432
 ; NOFP: add     x1, sp, #432
 
 define dso_local void @var_args(i8*, ...) {
   %2 = alloca i8*, align 8
   %3 = alloca i8*, align 8

llvm/test/CodeGen/AArch64/win64_vararg.ll

 declare void @llvm.va_end(i8*)
 declare void @llvm.lifetime.start.p0i8(i64, i8* nocapture) #1
 declare void @llvm.lifetime.end.p0i8(i64, i8* nocapture) #1
 
 declare i32 @__stdio_common_vsprintf(i64, i8*, i64, i8*, i8*, i8*) local_unnamed_addr #3
 declare i64* @__local_stdio_printf_options() local_unnamed_addr #4
 
 ; CHECK-LABEL: fp
-; CHECK: stp     x29, x30, [sp, #-96]
+; CHECK: stp     x19, x20, [sp, #-96]
 ; CHECK: str     x21,      [sp, #16]
-; CHECK: stp     x19, x20, [sp, #32]
-; CHECK: mov     x29, sp
-; CHECK: add     x8, x29, #56
+; CHECK: stp     x29, x30, [sp, #24]
+; CHECK: add     x29, sp, #24
+; CHECK: add     x8, x29, #32
 ; CHECK: mov     x19, x2
 ; CHECK: mov     x20, x1
 ; CHECK: mov     x21, x0
-; CHECK: stp     x3, x4, [x29, #56]
-; CHECK: stp     x5, x6, [x29, #72]
-; CHECK: str     x7, [x29, #88]
-; CHECK: str     x8, [x29, #24]
+; CHECK: stp     x3, x4, [x29, #32]
+; CHECK: stp     x5, x6, [x29, #48]
+; CHECK: str     x7, [x29, #64]
+; CHECK: str     x8, [x29, #16]
 ; CHECK: bl      __local_stdio_printf_options
 ; CHECK: ldr     x8, [x0]
-; CHECK: add     x5, x29, #56
+; CHECK: add     x5, x29, #32
 ; CHECK: mov     x1, x21
 ; CHECK: mov     x2, x20
 ; CHECK: orr     x0, x8, #0x2
 ; CHECK: mov     x3, x19
 ; CHECK: mov     x4, xzr
 ; CHECK: bl      __stdio_common_vsprintf
 ; CHECK: cmp     w0, #0
 ; CHECK: csinv   w0, w0, wzr, ge
-; CHECK: ldp     x19, x20, [sp, #32]
+; CHECK: ldp     x29, x30, [sp, #24]
 ; CHECK: ldr     x21,      [sp, #16]
-; CHECK: ldp     x29, x30, [sp], #96
+; CHECK: ldp     x19, x20, [sp], #96
 ; CHECK: ret
 define i32 @fp(i8*, i64, i8*, ...) local_unnamed_addr #6 {
   %4 = alloca i8*, align 8
   %5 = bitcast i8** %4 to i8*
   call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %5) #2
   call void @llvm.va_start(i8* nonnull %5)
   %6 = load i8*, i8** %4, align 8
   %7 = call i64* @__local_stdio_printf_options() #2
   %8 = load i64, i64* %7, align 8
   %9 = or i64 %8, 2
   %10 = call i32 @__stdio_common_vsprintf(i64 %9, i8* %0, i64 %1, i8* %2, i8* null, i8* %6) #2
   %11 = icmp sgt i32 %10, -1
   %12 = select i1 %11, i32 %10, i32 -1
   call void @llvm.va_end(i8* nonnull %5)
   call void @llvm.lifetime.end.p0i8(i64 8, i8* nonnull %5) #2
   ret i32 %12
 }
 
 attributes #6 = { "frame-pointer"="all" }
 
 ; CHECK-LABEL: vla
-; CHECK: stp     x29, x30, [sp, #-112]!
-; CHECK: str     x23, [sp, #16]
-; CHECK: stp     x21, x22, [sp, #32]
-; CHECK: stp     x19, x20, [sp, #48]
-; CHECK: mov     x29, sp
-; CHECK: add     x8, x29, #64
-; CHECK: str     x8, [x29, #24]
+; CHECK: stp     x19, x20, [sp, #-112]!
+; CHECK: stp     x21, x22, [sp, #16]
+; CHECK: str     x23,      [sp, #32]
+; CHECK: stp     x29, x30, [sp, #40]
+; CHECK: add     x29, sp, #40
+; CHECK: add     x8, x29, #24
+; CHECK: str     x8, [x29, #16]
 ; CHECK: mov     w8, w0
 ; CHECK: add     x8, x8, #15
 ; CHECK: lsr     x15, x8, #4
 ; CHECK: mov     x19, x1
 ; CHECK: mov     [[REG2:x[0-9]+]], sp
-; CHECK: stp     x2, x3, [x29, #64]
-; CHECK: stp     x4, x5, [x29, #80]
-; CHECK: stp     x6, x7, [x29, #96]
+; CHECK: stp     x2, x3, [x29, #24]
+; CHECK: stp     x4, x5, [x29, #40]
+; CHECK: stp     x6, x7, [x29, #56]
 ; CHECK: bl      __chkstk
 ; CHECK: mov     x8, sp
 ; CHECK: sub     [[REG:x[0-9]+]], x8, x15, lsl #4
 ; CHECK: mov     sp, [[REG]]
-; CHECK: ldr     [[REG3:x[0-9]+]], [x29, #24]
+; CHECK: ldr     [[REG3:x[0-9]+]], [x29, #16]
 ; CHECK: sxtw    [[REG4:x[0-9]+]], w0
 ; CHECK: bl      __local_stdio_printf_options
 ; CHECK: ldr     x8, [x0]
 ; CHECK: mov     x1, [[REG]]
 ; CHECK: mov     x2, [[REG4]]
 ; CHECK: mov     x3, x19
 ; CHECK: orr     x0, x8, #0x2
 ; CHECK: mov     x4, xzr
 ; CHECK: mov     x5, [[REG3]]
 ; CHECK: bl      __stdio_common_vsprintf
 ; CHECK: mov     sp, [[REG2]]
-; CHECK: mov     sp, x29
-; CHECK: ldp     x19, x20, [sp, #48]
-; CHECK: ldp     x21, x22, [sp, #32]
-; CHECK: ldr     x23, [sp, #16]
-; CHECK: ldp     x29, x30, [sp], #112
+; CHECK: sub     sp, x29, #40
+; CHECK: ldp     x29, x30, [sp, #40]
+; CHECK: ldr     x23,      [sp, #32]
+; CHECK: ldp     x21, x22, [sp, #16]
+; CHECK: ldp     x19, x20, [sp], #112
 ; CHECK: ret
 define void @vla(i32, i8*, ...) local_unnamed_addr {
   %3 = alloca i8*, align 8
   %4 = bitcast i8** %3 to i8*
   call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %4) #5
   call void @llvm.va_start(i8* nonnull %4)
   %5 = zext i32 %0 to i64
   %6 = call i8* @llvm.stacksave()
define void @vla(i32, i8*, ...) local_unnamed_addr {
   ret void
 }
 
 declare i8* @llvm.stacksave()
 declare void @llvm.stackrestore(i8*)
 
 ; CHECK-LABEL: snprintf
 ; CHECK-DAG: sub     sp,  sp, #96
-; CHECK-DAG: str     x30, [sp, #16]
-; CHECK-DAG: str     x21, [sp, #24]
-; CHECK-DAG: stp     x19, x20, [sp, #32]
+; CHECK-DAG: stp     x19, x20, [sp, #16]
+; CHECK-DAG: str     x21, [sp, #32]
+; CHECK-DAG: str     x30, [sp, #40]
 ; CHECK-DAG: add     x8, sp, #56
 ; CHECK-DAG: mov     x19, x2
 ; CHECK-DAG: mov     x20, x1
 ; CHECK-DAG: mov     x21, x0
 ; CHECK-DAG: stp     x3, x4, [sp, #56]
 ; CHECK-DAG: stp     x5, x6, [sp, #72]
 ; CHECK-DAG: str     x7, [sp, #88]
 ; CHECK-DAG: str     x8, [sp, #8]
 ; CHECK-DAG: bl      __local_stdio_printf_options
 ; CHECK-DAG: ldr     x8, [x0]
 ; CHECK-DAG: add     x5, sp, #56
 ; CHECK-DAG: mov     x1, x21
 ; CHECK-DAG: mov     x2, x20
 ; CHECK-DAG: orr     x0, x8, #0x2
 ; CHECK-DAG: mov     x3, x19
 ; CHECK-DAG: mov     x4, xzr
 ; CHECK-DAG: bl      __stdio_common_vsprintf
-; CHECK-DAG: ldr     x30, [sp, #16]
-; CHECK-DAG: ldr     x21, [sp, #24]
-; CHECK-DAG: ldp     x19, x20, [sp, #32]
+; CHECK-DAG: ldr     x30, [sp, #40]
+; CHECK-DAG: ldr     x21, [sp, #32]
+; CHECK-DAG: ldp     x19, x20, [sp, #16]
 ; CHECK-DAG: cmp     w0, #0
 ; CHECK-DAG: csinv   w0, w0, wzr, ge
 ; CHECK-DAG: add     sp, sp, #96
 ; CHECK-DAG: ret
 define i32 @snprintf(i8*, i64, i8*, ...) local_unnamed_addr #5 {
   %4 = alloca i8*, align 8
   %5 = bitcast i8** %4 to i8*
   call void @llvm.lifetime.start.p0i8(i64 8, i8* nonnull %5) #2

llvm/test/CodeGen/AArch64/wineh-frame-scavenge.mir

+# RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prologepilog \
+# RUN:   -stop-after=prologepilog | FileCheck %s
+# Check where the stack variable is placed
+
+# CHECK:      - { id: 0, name: '', type: default, offset: -4, size: 4, alignment: 4,
+# CHECK-NEXT:     stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+# CHECK-NEXT:     local-offset: -4, debug-info-variable: '', debug-info-expression: '',
+# CHECK-NEXT:     debug-info-location: '' }
+# CHECK-NEXT: - { id: 1, name: '', type: spill-slot, offset: -16, size: 8, alignment: 16,
+# CHECK-NEXT:     stack-id: default, callee-saved-register: '$x23', callee-saved-restored: true,
+# CHECK-NEXT:     debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+# CHECK-NEXT: - { id: 2, name: '', type: spill-slot, offset: -24, size: 8, alignment: 8,
+# CHECK-NEXT:     stack-id: default, callee-saved-register: '$x22', callee-saved-restored: true,
+# CHECK-NEXT:     debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+# CHECK-NEXT: - { id: 3, name: '', type: spill-slot, offset: -32, size: 8, alignment: 8,
+# CHECK-NEXT:     stack-id: default, callee-saved-register: '$x21', callee-saved-restored: true,
+# CHECK-NEXT:     debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+# CHECK-NEXT: - { id: 4, name: '', type: spill-slot, offset: -40, size: 8, alignment: 8,
+# CHECK-NEXT:     stack-id: default, callee-saved-register: '$x20', callee-saved-restored: true,
+# CHECK-NEXT:     debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+# CHECK-NEXT: - { id: 5, name: '', type: spill-slot, offset: -48, size: 8, alignment: 8,
+# CHECK-NEXT:     stack-id: default, callee-saved-register: '$x19', callee-saved-restored: true,
+# CHECK-NEXT:     debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
+
+# CHECK:      early-clobber $sp = frame-setup STPXpre killed $x19, killed $x20, $sp, -6 :: (store 8 into %stack.4), (store 8 into %stack.5)
+# CHECK-NEXT: frame-setup SEH_SaveRegP_X 19, 20, -48
+# CHECK-NEXT: frame-setup STPXi killed $x21, killed $x22, $sp, 2 :: (store 8 into %stack.2), (store 8 into %stack.3)
+# CHECK-NEXT: frame-setup SEH_SaveRegP 21, 22, 16
+# CHECK-NEXT: frame-setup STRXui killed $x23, $sp, 4 :: (store 8 into %stack.1)
+# CHECK-NEXT: frame-setup SEH_SaveReg 23, 32
+# CHECK-NEXT: frame-setup SEH_PrologEnd
+
+
+...
+---
+name:            func
+alignment:       4
+exposesReturnsTwice: false
+legalized:       false
+regBankSelected: false
+selected:        false
+failedISel:      false
+tracksRegLiveness: true
+hasWinCFI:       false
+registers:       []
+liveins:         []
+frameInfo:
+  isFrameAddressTaken: false
+  isReturnAddressTaken: false
+  hasStackMap:     false
+  hasPatchPoint:   false
+  stackSize:       0
+  offsetAdjustment: 0
+  maxAlignment:    4
+  adjustsStack:    false
+  hasCalls:        false
+  stackProtector:  ''
+  maxCallFrameSize: 0
+  cvBytesOfCalleeSavedRegisters: 0
+  hasOpaqueSPAdjustment: false
+  hasVAStart:      false
+  hasMustTailInVarArgFunc: false
+  localFrameSize:  4
+  savePoint:       ''
+  restorePoint:    ''
+fixedStack:      []
+stack:
+  - { id: 0, name: '', type: default, offset: 0, size: 4, alignment: 4,
+      stack-id: default, callee-saved-register: '', callee-saved-restored: true,
+      local-offset: -4, debug-info-variable: '', debug-info-expression: '',
+      debug-info-location: '' }
+callSites:       []
+constants:       []
+machineFunctionInfo: {}
+body:             |
+  bb.0.entry:
+    liveins: $x0, $x23, $x21, $x22, $x19, $x20
+
+    renamable $x8 = ADDXri %stack.0, 0, 0
+    $x19 = ADDXrr $x0, $x8
+    $x20 = ADDXrr $x19, $x0
+    $x21 = ADDXrr $x20, killed $x19
+    $x22 = ADDXrr $x21, killed $x20
+    $x23 = ADDXrr $x22, killed $x21
+    $x0 = ADDXrr $x0, killed $x23
+
+    RET_ReallyLR
+
+...

llvm/test/CodeGen/AArch64/wineh-frame0.mir

 # RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prologepilog \
 # RUN:   -stop-after=prologepilog | FileCheck %s
 # Check save_regp_x, save_regp
 
-# CHECK:        early-clobber $sp = frame-setup STPXpre killed $x27, killed $x28, $sp, -10
-# CHECK-NEXT:   frame-setup SEH_SaveRegP_X 27, 28, -80
-# CHECK-NEXT:   frame-setup STPXi killed $x25, killed $x26, $sp, 2
-# CHECK-NEXT:   frame-setup SEH_SaveRegP 25, 26, 16
+# CHECK:        early-clobber $sp = frame-setup STPXpre killed $x19, killed $x20, $sp, -10
+# CHECK-NEXT:   frame-setup SEH_SaveRegP_X 19, 20, -80
+# CHECK-NEXT:   frame-setup STPXi killed $x21, killed $x22, $sp, 2
+# CHECK-NEXT:   frame-setup SEH_SaveRegP 21, 22, 16
 # CHECK-NEXT:   frame-setup STPXi killed $x23, killed $x24, $sp, 4
 # CHECK-NEXT:   frame-setup SEH_SaveRegP 23, 24, 32
-# CHECK-NEXT:   frame-setup STPXi killed $x21, killed $x22, $sp, 6
-# CHECK-NEXT:   frame-setup SEH_SaveRegP 21, 22, 48
-# CHECK-NEXT:   frame-setup STPXi killed $x19, killed $x20, $sp, 8
-# CHECK-NEXT:   frame-setup SEH_SaveRegP 19, 20, 64
+# CHECK-NEXT:   frame-setup STPXi killed $x25, killed $x26, $sp, 6
+# CHECK-NEXT:   frame-setup SEH_SaveRegP 25, 26, 48
+# CHECK-NEXT:   frame-setup STPXi killed $x27, killed $x28, $sp, 8
+# CHECK-NEXT:   frame-setup SEH_SaveRegP 27, 28, 64
 # CHECK-NEXT:   frame-setup SEH_PrologEnd
 # CHECK:        frame-destroy SEH_EpilogStart
-# CHECK-NEXT:   $x19, $x20 = frame-destroy LDPXi $sp, 8
-# CHECK-NEXT:   frame-destroy SEH_SaveRegP 19, 20, 64
-# CHECK-NEXT:   $x21, $x22 = frame-destroy LDPXi $sp, 6
-# CHECK-NEXT:   frame-destroy SEH_SaveRegP 21, 22, 48
+# CHECK-NEXT:   $x27, $x28 = frame-destroy LDPXi $sp, 8
+# CHECK-NEXT:   frame-destroy SEH_SaveRegP 27, 28, 64
+# CHECK-NEXT:   $x25, $x26 = frame-destroy LDPXi $sp, 6
+# CHECK-NEXT:   frame-destroy SEH_SaveRegP 25, 26, 48
 # CHECK-NEXT:   $x23, $x24 = frame-destroy LDPXi $sp, 4
 # CHECK-NEXT:   frame-destroy SEH_SaveRegP 23, 24, 32
-# CHECK-NEXT:   $x25, $x26 = frame-destroy LDPXi $sp, 2
-# CHECK-NEXT:   frame-destroy SEH_SaveRegP 25, 26, 16
-# CHECK-NEXT:   early-clobber $sp, $x27, $x28 = frame-destroy LDPXpost $sp, 10
-# CHECK-NEXT:   frame-destroy SEH_SaveRegP_X 27, 28, -80
+# CHECK-NEXT:   $x21, $x22 = frame-destroy LDPXi $sp, 2
+# CHECK-NEXT:   frame-destroy SEH_SaveRegP 21, 22, 16
+# CHECK-NEXT:   early-clobber $sp, $x19, $x20 = frame-destroy LDPXpost $sp, 10
+# CHECK-NEXT:   frame-destroy SEH_SaveRegP_X 19, 20, -80
 # CHECK-NEXT:   frame-destroy SEH_EpilogEnd
 # CHECK-NEXT:   RET_ReallyLR implicit $x0
 
 ...
 ---
 name:            test
 alignment:       4
 tracksRegLiveness: true

llvm/test/CodeGen/AArch64/wineh-frame1.mir

 # RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prologepilog \
 # RUN:   -stop-after=prologepilog | FileCheck %s
 # Check save_fregp_x, save_fregp
 
-# CHECK:         early-clobber $sp = frame-setup STPDpre killed $d10, killed $d11, $sp, -14
-# CHECK-NEXT:    frame-setup SEH_SaveFRegP_X 10, 11, -112
-# CHECK-NEXT:    frame-setup STPDi killed $d8, killed $d9, $sp, 2
-# CHECK-NEXT:    frame-setup SEH_SaveFRegP 8, 9, 16
-# CHECK-NEXT:    frame-setup STPXi killed $x27, killed $x28, $sp, 4
-# CHECK-NEXT:    frame-setup SEH_SaveRegP 27, 28, 32
+# CHECK:         early-clobber $sp = frame-setup STPXpre killed $x19, killed $x20, $sp, -14
+# CHECK-NEXT:    frame-setup SEH_SaveRegP_X 19, 20, -112
+# CHECK-NEXT:    frame-setup STPXi killed $x21, killed $x22, $sp, 2
+# CHECK-NEXT:    frame-setup SEH_SaveRegP 21, 22, 16
+# CHECK-NEXT:    frame-setup STPXi killed $x23, killed $x24, $sp, 4
+# CHECK-NEXT:    frame-setup SEH_SaveRegP 23, 24, 32
 # CHECK-NEXT:    frame-setup STPXi killed $x25, killed $x26, $sp, 6
 # CHECK-NEXT:    frame-setup SEH_SaveRegP 25, 26, 48
-# CHECK-NEXT:    frame-setup STPXi killed $x23, killed $x24, $sp, 8
-# CHECK-NEXT:    frame-setup SEH_SaveRegP 23, 24, 64
-# CHECK-NEXT:    frame-setup STPXi killed $x21, killed $x22, $sp, 10
-# CHECK-NEXT:    frame-setup SEH_SaveRegP 21, 22, 80
-# CHECK-NEXT:    frame-setup STPXi killed $x19, killed $x20, $sp, 12
-# CHECK-NEXT:    frame-setup SEH_SaveRegP 19, 20, 96
+# CHECK-NEXT:    frame-setup STPXi killed $x27, killed $x28, $sp, 8
+# CHECK-NEXT:    frame-setup SEH_SaveRegP 27, 28, 64
+# CHECK-NEXT:    frame-setup STPDi killed $d8, killed $d9, $sp, 10
+# CHECK-NEXT:    frame-setup SEH_SaveFRegP 8, 9, 80
+# CHECK-NEXT:    frame-setup STPDi killed $d10, killed $d11, $sp, 12
+# CHECK-NEXT:    frame-setup SEH_SaveFRegP 10, 11, 96
 # CHECK-NEXT:    frame-setup SEH_PrologEnd
 # CHECK:         frame-destroy SEH_EpilogStart
-# CHECK-NEXT:    $x19, $x20 = frame-destroy LDPXi $sp, 12
-# CHECK-NEXT:    frame-destroy SEH_SaveRegP 19, 20, 96
-# CHECK-NEXT:    $x21, $x22 = frame-destroy LDPXi $sp, 10
-# CHECK-NEXT:    frame-destroy SEH_SaveRegP 21, 22, 80
-# CHECK-NEXT:    $x23, $x24 = frame-destroy LDPXi $sp, 8
-# CHECK-NEXT:    frame-destroy SEH_SaveRegP 23, 24, 64
+# CHECK-NEXT:    $d10, $d11 = frame-destroy LDPDi $sp, 12
+# CHECK-NEXT:    frame-destroy SEH_SaveFRegP 10, 11, 96
+# CHECK-NEXT:    $d8, $d9 = frame-destroy LDPDi $sp, 10
+# CHECK-NEXT:    frame-destroy SEH_SaveFRegP 8, 9, 80
+# CHECK-NEXT:    $x27, $x28 = frame-destroy LDPXi $sp, 8
+# CHECK-NEXT:    frame-destroy SEH_SaveRegP 27, 28, 64
 # CHECK-NEXT:    $x25, $x26 = frame-destroy LDPXi $sp, 6
 # CHECK-NEXT:    frame-destroy SEH_SaveRegP 25, 26, 48
-# CHECK-NEXT:    $x27, $x28 = frame-destroy LDPXi $sp, 4
-# CHECK-NEXT:    frame-destroy SEH_SaveRegP 27, 28, 32
-# CHECK-NEXT:    $d8, $d9 = frame-destroy LDPDi $sp, 2
-# CHECK-NEXT:    frame-destroy SEH_SaveFRegP 8, 9, 16
-# CHECK-NEXT:    early-clobber $sp, $d10, $d11 = frame-destroy LDPDpost $sp, 14
-# CHECK-NEXT:    frame-destroy SEH_SaveFRegP_X 10, 11, -112
+# CHECK-NEXT:    $x23, $x24 = frame-destroy LDPXi $sp, 4
+# CHECK-NEXT:    frame-destroy SEH_SaveRegP 23, 24, 32
+# CHECK-NEXT:    $x21, $x22 = frame-destroy LDPXi $sp, 2
+# CHECK-NEXT:    frame-destroy SEH_SaveRegP 21, 22, 16
+# CHECK-NEXT:    early-clobber $sp, $x19, $x20 = frame-destroy LDPXpost $sp, 14
+# CHECK-NEXT:    frame-destroy SEH_SaveRegP_X 19, 20, -112
 # CHECK-NEXT:    frame-destroy SEH_EpilogEnd
 # CHECK-NEXT:    RET_ReallyLR implicit $x0
 ...
 ---
 name:            test
 alignment:       4
 exposesReturnsTwice: false
 legalized:       false

llvm/test/CodeGen/AArch64/wineh-frame2.mir

 # RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prologepilog \
 # RUN:   -stop-after=prologepilog | FileCheck %s
 # Check save_freg_x, save_frep, save_reg
 
-# CHECK:       early-clobber $sp = frame-setup STRDpre killed $d12, $sp, -48
-# CHECK-NEXT:  frame-setup SEH_SaveFReg_X 12, -48
-# CHECK-NEXT:  frame-setup STPDi killed $d10, killed $d11, $sp, 1
-# CHECK-NEXT:  frame-setup SEH_SaveFRegP 10, 11, 8
-# CHECK-NEXT:  frame-setup STPDi killed $d8, killed $d9, $sp, 3
-# CHECK-NEXT:  frame-setup SEH_SaveFRegP 8, 9, 24
-# CHECK-NEXT:  frame-setup STRXui killed $x19, $sp, 5
-# CHECK-NEXT:  frame-setup SEH_SaveReg 19, 40
+# CHECK:       early-clobber $sp = frame-setup STRXpre killed $x19, $sp, -48
+# CHECK-NEXT:  frame-setup SEH_SaveReg_X 19, -48
+# CHECK-NEXT:  frame-setup STPDi killed $d8, killed $d9, $sp, 1
+# CHECK-NEXT:  frame-setup SEH_SaveFRegP 8, 9, 8
+# CHECK-NEXT:  frame-setup STPDi killed $d10, killed $d11, $sp, 3
+# CHECK-NEXT:  frame-setup SEH_SaveFRegP 10, 11, 24
+# CHECK-NEXT:  frame-setup STRDui killed $d12, $sp, 5
+# CHECK-NEXT:  frame-setup SEH_SaveFReg 12, 40
 # CHECK-NEXT:  frame-setup SEH_PrologEnd
 # CHECK:       frame-destroy SEH_EpilogStart
-# CHECK-NEXT:  $x19 = frame-destroy LDRXui $sp, 5
-# CHECK-NEXT:  frame-destroy SEH_SaveReg 19, 40
-# CHECK-NEXT:  $d8, $d9 = frame-destroy LDPDi $sp, 3
-# CHECK-NEXT:  frame-destroy SEH_SaveFRegP 8, 9, 24
-# CHECK-NEXT:  $d10, $d11 = frame-destroy LDPDi $sp, 1
-# CHECK-NEXT:  frame-destroy SEH_SaveFRegP 10, 11, 8
-# CHECK-NEXT:  early-clobber $sp, $d12 = frame-destroy LDRDpost $sp, 48
-# CHECK-NEXT:  frame-destroy SEH_SaveFReg_X 12, -48
+# CHECK-NEXT:  $d12 = frame-destroy LDRDui $sp, 5
+# CHECK-NEXT:  frame-destroy SEH_SaveFReg 12, 40
+# CHECK-NEXT:  $d10, $d11 = frame-destroy LDPDi $sp, 3
+# CHECK-NEXT:  frame-destroy SEH_SaveFRegP 10, 11, 24
+# CHECK-NEXT:  $d8, $d9 = frame-destroy LDPDi $sp, 1
+# CHECK-NEXT:  frame-destroy SEH_SaveFRegP 8, 9, 8
+# CHECK-NEXT:  early-clobber $sp, $x19 = frame-destroy LDRXpost $sp, 48
+# CHECK-NEXT:  frame-destroy SEH_SaveReg_X 19, -48
 # CHECK-NEXT:  frame-destroy SEH_EpilogEnd
 # CHECK-NEXT:  RET_ReallyLR implicit $x0
 ...
 ---
 name:            test
 alignment:       4
 exposesReturnsTwice: false
 legalized:       false

llvm/test/CodeGen/AArch64/wineh-frame3.mir

 # RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prologepilog \
 # RUN:   -stop-after=prologepilog | FileCheck %s
 # Check save_reg_x, save_reg
 
-# CHECK:      early-clobber $sp = frame-setup STRXpre killed $x22, $sp, -16
-# CHECK-NEXT: frame-setup SEH_SaveReg_X 22, -16
-# CHECK-NEXT: frame-setup STRXui killed $x19, $sp, 1
-# CHECK-NEXT: frame-setup SEH_SaveReg 19, 8
+# CHECK:      early-clobber $sp = frame-setup STRXpre killed $x19, $sp, -16
+# CHECK-NEXT: frame-setup SEH_SaveReg_X 19, -16
+# CHECK-NEXT: frame-setup STRXui killed $x22, $sp, 1
+# CHECK-NEXT: frame-setup SEH_SaveReg 22, 8
 # CHECK-NEXT: frame-setup SEH_PrologEnd
 # CHECK:      frame-destroy SEH_EpilogStart
-# CHECK-NEXT: $x19 = frame-destroy LDRXui $sp, 1
-# CHECK-NEXT: frame-destroy SEH_SaveReg 19, 8
-# CHECK-NEXT: early-clobber $sp, $x22 = frame-destroy LDRXpost $sp, 16
-# CHECK-NEXT: frame-destroy SEH_SaveReg_X 22, -16
+# CHECK-NEXT: $x22 = frame-destroy LDRXui $sp, 1
+# CHECK-NEXT: frame-destroy SEH_SaveReg 22, 8
+# CHECK-NEXT: early-clobber $sp, $x19 = frame-destroy LDRXpost $sp, 16
+# CHECK-NEXT: frame-destroy SEH_SaveReg_X 19, -16
 # CHECK-NEXT: frame-destroy SEH_EpilogEnd
 # CHECK-NEXT: RET_ReallyLR implicit $x0
 ...
 ---
 name:            test
 alignment:       4
 exposesReturnsTwice: false
 legalized:       false

llvm/test/CodeGen/AArch64/wineh-frame4.mir

 # RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prologepilog \
 # RUN:   -stop-after=prologepilog | FileCheck %s
 # Check save_freg_x, save_freg
 
-# CHECK:       early-clobber $sp = frame-setup STRDpre killed $d10, $sp, -16
-# CHECK-NEXT:  frame-setup SEH_SaveFReg_X 10, -16
-# CHECK-NEXT:  frame-setup STRDui killed $d8, $sp, 1 :: (store 8 into %stack.0)
-# CHECK-NEXT:  frame-setup SEH_SaveFReg 8, 8
+# CHECK:       early-clobber $sp = frame-setup STRDpre killed $d8, $sp, -16
+# CHECK-NEXT:  frame-setup SEH_SaveFReg_X 8, -16
+# CHECK-NEXT:  frame-setup STRDui killed $d10, $sp, 1 :: (store 8 into %stack.0)
+# CHECK-NEXT:  frame-setup SEH_SaveFReg 10, 8
 # CHECK-NEXT:  frame-setup SEH_PrologEnd
 # CHECK:       frame-destroy SEH_EpilogStart
-# CHECK-NEXT:  $d8 = frame-destroy LDRDui $sp, 1 :: (load 8 from %stack.0)
-# CHECK-NEXT:  frame-destroy SEH_SaveFReg 8, 8
-# CHECK-NEXT:  early-clobber $sp, $d10 = frame-destroy LDRDpost $sp, 16 :: (load 8 from %stack.1)
-# CHECK-NEXT:  frame-destroy SEH_SaveFReg_X 10, -16
+# CHECK-NEXT:  $d10 = frame-destroy LDRDui $sp, 1 :: (load 8 from %stack.0)
+# CHECK-NEXT:  frame-destroy SEH_SaveFReg 10, 8
+# CHECK-NEXT:  early-clobber $sp, $d8 = frame-destroy LDRDpost $sp, 16 :: (load 8 from %stack.1)
+# CHECK-NEXT:  frame-destroy SEH_SaveFReg_X 8, -16
 # CHECK-NEXT:  frame-destroy SEH_EpilogEnd
 # CHECK-NEXT:  RET_ReallyLR implicit $x0
 ...
 ---
 name:            test
 alignment:       4
 exposesReturnsTwice: false
 legalized:       false

llvm/test/CodeGen/AArch64/wineh-frame5.mir

 # RUN: llc -o - %s -mtriple=aarch64-windows -start-before=prologepilog \
 # RUN:   -stop-after=prologepilog | FileCheck %s
 # Check multiple epilogues, save_reg, save_reg_x.
 
 # CHECK-LABEL:   bb.0.entry:
-# CHECK:         early-clobber $sp = frame-setup STPXpre killed $fp, killed $lr, $sp, -4
-# CHECK-NEXT:    frame-setup SEH_SaveFPLR_X -32
-# CHECK-NEXT:    frame-setup STRXui killed $x19, $sp, 2
-# CHECK-NEXT:    frame-setup SEH_SaveReg 19, 16
+# CHECK:         early-clobber $sp = frame-setup STRXpre killed $x19, $sp, -32
+# CHECK-NEXT:    frame-setup SEH_SaveReg_X 19, -32
+# CHECK-NEXT:    frame-setup STPXi killed $fp, killed $lr, $sp, 1
+# CHECK-NEXT:    frame-setup SEH_SaveFPLR 8
 # CHECK-NEXT:    $sp = frame-setup SUBXri $sp, 496, 0
 # CHECK-NEXT:    frame-setup SEH_StackAlloc 496
 # CHECK-NEXT:    frame-setup SEH_PrologEnd
 
 # CHECK-LABEL:   bb.1.if.then:
 # CHECK:         frame-destroy SEH_EpilogStart
 # CHECK-NEXT:    $sp = frame-destroy ADDXri $sp, 496, 0
 # CHECK-NEXT:    frame-destroy SEH_StackAlloc 496
-# CHECK-NEXT:    $x19 = frame-destroy LDRXui $sp, 2
-# CHECK-NEXT:    frame-destroy SEH_SaveReg 19, 16
-# CHECK-NEXT:    early-clobber $sp, $fp, $lr = frame-destroy LDPXpost $sp, 4
-# CHECK-NEXT:    frame-destroy SEH_SaveFPLR_X -32
+# CHECK-NEXT:    $fp, $lr = frame-destroy LDPXi $sp, 1
+# CHECK-NEXT:    frame-destroy SEH_SaveFPLR 8
+# CHECK-NEXT:    early-clobber $sp, $x19 = frame-destroy LDRXpost $sp, 32
+# CHECK-NEXT:    frame-destroy SEH_SaveReg_X 19, -32
 # CHECK-NEXT:    frame-destroy SEH_EpilogEnd
 # CHECK-NEXT:    TCRETURNdi @"?func2@@YAHXZ", 0, csr_aarch64_aapcs, implicit $sp
 
 
 --- |
   target datalayout = "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128"
   target triple = "aarch64-unknown-windows-msvc19.11.0"
 

llvm/test/CodeGen/AArch64/wineh-try-catch-realign.ll

 ; RUN: llc -o - %s -mtriple=aarch64-windows -verify-machineinstrs | FileCheck %s
 
 ; Make sure we have a base pointer.
 ; CHECK-LABEL: "?a@@YAXXZ":
 ; CHECK: and     sp, x9, #0xffffffffffffffc0
 ; CHECK: mov     x19, sp
 
 ; Make sure the funclet prologue/epilogue are correct: specifically,
 ; it shouldn't access the parent's frame via sp, and the prologue and
 ; epilogue should be symmetrical.
 ; CHECK-LABEL: "?catch$2@?0??a@@YAXXZ@4HA":
-; CHECK:      stp     x29, x30, [sp, #-32]!
-; CHECK-NEXT: .seh_save_fplr_x 32
-; CHECK-NEXT: str     x28, [sp, #16]
-; CHECK-NEXT: .seh_save_reg x28, 16
-; CHECK-NEXT: str     x19, [sp, #24]
-; CHECK-NEXT: .seh_save_reg x19, 24
+; CHECK:      str     x19, [sp, #-32]!
+; CHECK-NEXT: .seh_save_reg_x x19, 32
+; CHECK-NEXT: str     x28, [sp, #8]
+; CHECK-NEXT: .seh_save_reg x28, 8
+; CHECK-NEXT: stp     x29, x30, [sp, #16]
+; CHECK-NEXT: .seh_save_fplr 16
 ; CHECK-NEXT: .seh_endprologue
 ; CHECK-NEXT: add     x0, x19, #0
 ; CHECK-NEXT: mov     w1, wzr
 ; CHECK-NEXT: bl      "?bb@@YAXPEAHH@Z"
 ; CHECK-NEXT: adrp    x0, .LBB0_1
 ; CHECK-NEXT: add     x0, x0, .LBB0_1
 ; CHECK-NEXT: .seh_startepilogue
-; CHECK-NEXT: ldr     x19, [sp, #24]
-; CHECK-NEXT: .seh_save_reg x19, 24
-; CHECK-NEXT: ldr     x28, [sp, #16]
-; CHECK-NEXT: .seh_save_reg x28, 16
-; CHECK-NEXT: ldp     x29, x30, [sp], #32
-; CHECK-NEXT: .seh_save_fplr_x 32
+; CHECK-NEXT: ldp     x29, x30, [sp, #16]
+; CHECK-NEXT: .seh_save_fplr 16
+; CHECK-NEXT: ldr     x28, [sp, #8]
+; CHECK-NEXT: .seh_save_reg x28, 8
+; CHECK-NEXT: ldr     x19, [sp], #32
+; CHECK-NEXT: .seh_save_reg_x x19, 32
 ; CHECK-NEXT: .seh_endepilogue
 ; CHECK-NEXT: ret
 
 
 target datalayout = "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64-unknown-windows-msvc19.11.0"
 
 define dso_local void @"?a@@YAXXZ"() personality i8* bitcast (i32 (...)* @__CxxFrameHandler3 to i8*) {

llvm/test/CodeGen/AArch64/wineh-try-catch.ll

 ; 3) That the locals are accessed using the frame pointer in both the funclet
 ;    and the parent function.
 
 ; The following checks that the unwind help object has -2 stored into it at
 ; fp + 16, which is on-entry sp - 16.
 ; We check this offset in the table later on.
 
 ; CHECK-LABEL: "?func@@YAHXZ":
-; CHECK:       stp     x29, x30, [sp, #-64]!
-; CHECK:       str     x28, [sp, #16]
-; CHECK:       str     x21, [sp, #24]
-; CHECK:       stp     x19, x20, [sp, #32]
-; CHECK:       mov     x29, sp
+; CHECK:       stp     x19, x20, [sp, #-64]!
+; CHECK:       str     x21, [sp, #16]
+; CHECK:       str     x28, [sp, #24]
+; CHECK:       stp     x29, x30, [sp, #32]
+; CHECK:       add     x29, sp, #32
 ; CHECK:       sub     sp, sp, #624
 ; CHECK:       mov     x19, sp
 ; CHECK:       mov     x0, #-2
-; CHECK:       stur    x0, [x29, #48]
+; CHECK:       stur    x0, [x29, #16]
 
 ; Now check that x is stored at fp - 20.  We check that this is the same
 ; location accessed from the funclet to retrieve x.
 ; CHECK:       mov     w8, #1
 ; CHECK:       stur    w8, [x29, [[X_OFFSET:#-[1-9][0-9]+]]
 
 ; Check the offset off the frame pointer at which B is located.
 ; Check the same offset is used to pass the address of B to init2 in the
 ; funclet.
 ; CHECK:       sub     x0, x29, [[B_OFFSET:#[1-9][0-9]+]]
 ; CHECK:       bl      "?init@@YAXPEAH@Z"
 
 ; This is the label for the throw that is encoded in the ip2state.
 ; We are inside the try block, where we make a call to func2
 ; CHECK-LABEL: .Ltmp0:
 ; CHECK:       bl      "?func2@@YAHXZ
 
 ; CHECK:        [[CATCHRETDEST:.LBB0_[0-9]+]]:      ; %catchret.dest
 
 ; Check the catch funclet.
 ; CHECK-LABEL: "?catch$2@?0??func@@YAHXZ@4HA":
 
 ; Check that the stack space is allocated only for the callee saved registers.
-; CHECK:       stp     x29, x30, [sp, #-48]!
-; CHECK:       str     x28, [sp, #16]
-; CHECK:       str     x21, [sp, #24]
-; CHECK:       stp     x19, x20, [sp, #32]
+; CHECK:       stp     x19, x20, [sp, #-48]!
+; CHECK:       str     x21, [sp, #16]
+; CHECK:       str     x28, [sp, #24]
+; CHECK:       stp     x29, x30, [sp, #32]
 ; CHECK:       add     x20, x19, #12
 
 ; Check that there are no further stack updates.
 ; CHECK-NOT:   sub     sp, sp
 
 ; Check that the stack address passed to init2 is off the frame pointer, and
 ; that it matches the address of B in the parent function.
 ; CHECK:       sub     x0, x29, [[B_OFFSET]]

 ; CHECK-NEXT:         .word   4                       ; IPMapEntries
 ; CHECK-NEXT:         .word   ("$ip2state$?func@@YAHXZ")@IMGREL ; IPToStateXData
 ; CHECK-NEXT:         .word   -16                     ; UnwindHelp
 
 ; UNWIND: Function: ?func@@YAHXZ (0x0)
 ; UNWIND: Prologue [
 ; UNWIND-NEXT: ; nop
 ; UNWIND-NEXT: ; sub sp, #624
-; UNWIND-NEXT: ; mov fp, sp
-; UNWIND-NEXT: ; stp x19, x20, [sp, #32]
-; UNWIND-NEXT: ; str x21, [sp, #24]
-; UNWIND-NEXT: ; str x28, [sp, #16]
-; UNWIND-NEXT: ; stp x29, x30, [sp, #-64]!
+; UNWIND-NEXT: ; add fp, sp, #32
+; UNWIND-NEXT: ; stp x29, x30, [sp, #32]
+; UNWIND-NEXT: ; str x28, [sp, #24]
+; UNWIND-NEXT: ; str x21, [sp, #16]
+; UNWIND-NEXT: ; stp x19, x20, [sp, #-64]!
 ; UNWIND-NEXT: ; end
 ; UNWIND: Function: ?catch$2@?0??func@@YAHXZ@4HA
 ; UNWIND: Prologue [
-; UNWIND-NEXT: ; stp x19, x20, [sp, #32]
-; UNWIND-NEXT: ; str x21, [sp, #24]
-; UNWIND-NEXT: ; str x28, [sp, #16]
-; UNWIND-NEXT: ; stp x29, x30, [sp, #-48]!
+; UNWIND-NEXT: ; stp x29, x30, [sp, #32]
+; UNWIND-NEXT: ; str x28, [sp, #24]
+; UNWIND-NEXT: ; str x21, [sp, #16]
+; UNWIND-NEXT: ; stp x19, x20, [sp, #-48]!
 ; UNWIND-NEXT: ; end
 
 target datalayout = "e-m:w-p:64:64-i32:32-i64:64-i128:128-n32:64-S128"
 target triple = "aarch64-unknown-windows-msvc19.11.0"
 
 %rtti.TypeDescriptor2 = type { i8**, i8*, [3 x i8] }
 %eh.CatchableType = type { i32, i32, i32, i32, i32, i32, i32 }
 %eh.CatchableTypeArray.1 = type { i32, [1 x i32] }

llvm/test/CodeGen/AArch64/wineh_shrinkwrap.mir

 # RUN: llc -O2 -o - %s -mtriple=aarch64-windows -start-before=shrink-wrap \
 # RUN:   -stop-after=prologepilog | FileCheck %s --check-prefix=WIN64
 # RUN: llc -O2 -o - %s -mtriple=aarch64-linux -start-before=shrink-wrap \
 # RUN:   -stop-after=prologepilog | FileCheck %s --check-prefix=LINUX
 
 # This tests checks that shrink wrapping bails out on Windows AMR64 due to the
 # use of Windows CFI.  We don't currently support fragments for WIndows EH on
 # ARM64.
 # The same test gets shrink wrapped on Linux ARM64.
 
 # WIN64-LABEL: bb.0.entry:
-# WIN64: early-clobber $sp = frame-setup STPXpre killed $fp, killed $lr, $sp, -4
+# WIN64: early-clobber $sp = frame-setup STRXpre killed $x19, $sp, -32
 # WIN64-LABEL: bb.1:
 # WIN64-LABEL: bb.2.if.then:
 
 # LINUX-LABEL: bb.0.entry:
 # LINUX-LABEL: bb.1:
 # LINUX-LABEL: bb.2.if.then:
 # LINUX: early-clobber $sp = frame-setup STRXpre killed $fp, $sp, -32
 --- |