[PowerPC] Materialize the immediate that is Uint32 but not Int32.

[Esme]

Summary

If the immediate doen't fit int32 but fits uint32, which means the sign bit is 1. If we use LI/LIS to load the high bits, LIS/LI will sign-extend the value, where an extra clrldi is necessary. However if its low bits fits int16, we can use LI to load the low bits then handle the high bits.
For example, currently we need 3 instructions for i32 -394967296

	lis 3, 232
	ori 3, 3, 30023
	sldi 3, 3, 8

After this patch we get,

	li 3, 18176
	oris 3, 3, 59509

[amyk]

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

918

s/doen't/doesn't

s/fits/fits in

s/which means/this means

[Esme]

Patch D92089 can cover this.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

 // selectI64Imm(N).
 static unsigned selectI64ImmInstrCountDirect(int64_t Imm) {
   // Assume no remaining bits.
   unsigned Remainder = 0;
   // Assume no shift required.
   unsigned Shift = 0;
 
   // If it can't be represented as a 32 bit value.
-  if (!isInt<32>(Imm)) {
+  if (!isInt<32>(Imm) && !(isUInt<32>(Imm) && isInt<16>(Imm & 0xFFFF))) {
     Shift = countTrailingZeros<uint64_t>(Imm);
     int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
 
     // If the shifted value fits 32 bits.
-    if (isInt<32>(ImmSh)) {
+    if (isInt<32>(ImmSh) || (isUInt<32>(ImmSh) && isInt<16>(ImmSh & 0xFFFF))) {
       // Go with the shifted value.
       Imm = ImmSh;
     } else {
       // Still stuck with a 64 bit value.
       Remainder = Imm;
       Shift = 32;
       Imm >>= 32;
     }
   }
 
   // Intermediate operand.
   unsigned Result = 0;
 
   // Handle first 32 bits.
   unsigned Lo = Imm & 0xFFFF;
 
   // Simple value.
-  if (isInt<16>(Imm)) {
+  if (isInt<16>(Imm))
     // Just the Lo bits.
     ++Result;
-  } else if (Lo) {
+  else if (isInt<32>(Imm))
+    if (Lo)
       // Handle the Hi bits and Lo bits.
       Result += 2;
-  } else {
+    else
       // Just the Hi bits.
       ++Result;
-  }
+  else
+    // Here the Imm satisfies isUInt<32>(Imm) && isInt<16>(Lo).
+    Result += 2;
 
   // If no shift, we're done.
   if (!Shift) return Result;
 
   // If Hi word == Lo word,
   // we can use rldimi to insert the Lo word into Hi word.
   if ((unsigned)(Imm & 0xFFFFFFFF) == Remainder) {
     ++Result;

 // (above) needs to be kept in sync with this function.
 static SDNode *selectI64ImmDirect(SelectionDAG *CurDAG, const SDLoc &dl,
                                   int64_t Imm) {
   // Assume no remaining bits.
   unsigned Remainder = 0;
   // Assume no shift required.
   unsigned Shift = 0;
 
+  // If the immediate doen't fit int32 but fits uint32, which means the sign bit
+  // is 1. If we use LI/LIS to load the high bits, LIS/LI will sign-extend the
+  // value, where an extra clrldi is necessary, then have no improvement.
+  // However if its low bits fits int16, we can use LI to load the low bits and
+  // then handle the high bits.
+
   // If it can't be represented as a 32 bit value.
-  if (!isInt<32>(Imm)) {
+  if (!isInt<32>(Imm) && !(isUInt<32>(Imm) && isInt<16>(Imm & 0xFFFF))) {
     Shift = countTrailingZeros<uint64_t>(Imm);
     int64_t ImmSh = static_cast<uint64_t>(Imm) >> Shift;
 
     // If the shifted value fits 32 bits.
-    if (isInt<32>(ImmSh)) {
+    if (isInt<32>(ImmSh) || (isUInt<32>(ImmSh) && isInt<16>(ImmSh & 0xFFFF))) {
       // Go with the shifted value.
       Imm = ImmSh;
     } else {
       // Still stuck with a 64 bit value.
       Remainder = Imm;
       Shift = 32;
       Imm >>= 32;
     }
static SDNode *selectI64ImmDirect(SelectionDAG *CurDAG, const SDLoc &dl,
   };
 
   // Simple value.
   if (isInt<16>(Imm)) {
     uint64_t SextImm = SignExtend64(Lo, 16);
     SDValue SDImm = CurDAG->getTargetConstant(SextImm, dl, MVT::i64);
     // Just the Lo bits.
     Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, SDImm);
-  } else if (Lo) {
+  } else if (isInt<32>(Imm)) {
+    if (Lo) {
       // Handle the Hi bits.
       unsigned OpC = Hi ? PPC::LIS8 : PPC::LI8;
       Result = CurDAG->getMachineNode(OpC, dl, MVT::i64, getI32Imm(Hi));
       // And Lo bits.
       Result = CurDAG->getMachineNode(PPC::ORI8, dl, MVT::i64,
                                       SDValue(Result, 0), getI32Imm(Lo));
-  } else {
+    } else
       // Just the Hi bits.
       Result = CurDAG->getMachineNode(PPC::LIS8, dl, MVT::i64, getI32Imm(Hi));
+  } else {
+    // Here the Imm satisfies isUInt<32>(Imm) && isInt<16>(Lo).
+    Result = CurDAG->getMachineNode(PPC::LI8, dl, MVT::i64, getI32Imm(Lo));
+    Result = CurDAG->getMachineNode(PPC::ORIS8, dl, MVT::i64,
+                                    SDValue(Result, 0), getI32Imm(Hi));
   }
 
   // If no shift, we're done.
   if (!Shift) return Result;
 
   // If Hi word == Lo word,
   // we can use rldimi to insert the Lo word into Hi word.
   if ((unsigned)(Imm & 0xFFFFFFFF) == Remainder) {

llvm/test/CodeGen/PowerPC/aix-cc-abi.ll

 entry:
   call i32 @test_ints(i32 signext 1, i32 zeroext 1, i32 zeroext 2147483648, i32 signext -2147483648, i32 signext 1, i32 signext 1, i32 signext 1, i32 signext 1)
   ret void
 }
 
 ; CHECK-LABEL: name: call_test_ints
 
 ; 64BIT: ADJCALLSTACKDOWN 112, 0, implicit-def dead $r1, implicit $r1
-; 64BIT: renamable $x3 = LI8 1
-; 64BIT: renamable $x5 = RLDICR killed renamable $x3, 31, 32
+; 64BIT: renamable $x3 = LI8 0
+; 64BIT: renamable $x5 = ORIS8 killed renamable $x3, 32768
 ; 64BIT: $x3 = LI8 1
 ; 64BIT: $x4 = LI8 1
 ; 64BIT: $x6 = LIS8 32768
 ; 64BIT: $x7 = LI8 1
 ; 64BIT: $x8 = LI8 1
 ; 64BIT: $x9 = LI8 1
 ; 64BIT: $x10 = LI8 1
 ; 64BIT:  BL8_NOP <mcsymbol .test_ints>, csr_ppc64, implicit-def dead $lr8, implicit $rm, implicit $x3, implicit killed $x4, implicit $x5, implicit killed $x6, implicit killed $x7, implicit killed $x8, implicit killed $x9, implicit killed $x10, implicit $x2, implicit-def $r1, implicit-def dead $x3

llvm/test/CodeGen/PowerPC/constants-i64.ll

 ; CHECK: blr
 }
 
 define i64 @uint32_1() #0 {
 entry:
   ret i64 3900000000
 
 ; CHECK-LABEL: @uint32_1
-; CHECK: lis [[REG1:[0-9]+]], 232
-; CHECK: ori [[REG2:[0-9]+]], [[REG1]], 30023
-; CHECK: sldi 3, [[REG2]], 8
+; CHECK: li [[REG1:[0-9]+]], 18176
+; CHECK: oris [[REG2:[0-9]+]], [[REG1]], 59509
 ; CHECK: blr
 }
 
 define i32 @uint32_1_i32() #0 {
 entry:
   ret i32 -394967296
 
 ; CHECK-LABEL: @uint32_1_i32
-; CHECK: lis [[REG1:[0-9]+]], 232
-; CHECK: ori [[REG2:[0-9]+]], [[REG1]], 30023
-; CHECK: sldi 3, [[REG2]], 8
+; CHECK: li [[REG1:[0-9]+]], 18176
+; CHECK: oris [[REG2:[0-9]+]], [[REG1]], 59509
 ; CHECK: blr
 }
 
 define i64 @uint32_2() #0 {
 entry:
   ret i64 4294967295
 
 ; CHECK-LABEL: @uint32_2

 ; CHECK: blr
 }
 
 define i64 @uint32_3() #0 {
 entry:
   ret i64 2147483648
 
 ; CHECK-LABEL: @uint32_3
-; CHECK: li [[REG1:[0-9]+]], 1
-; CHECK: sldi 3, [[REG1]], 31
+; CHECK: li [[REG1:[0-9]+]], 0
+; CHECK: oris 3, [[REG1]], 32768
 ; CHECK: blr
 }
 
 define i64 @uint32_4() #0 {
 entry:
   ret i64 124800000032
 
 ; CHECK-LABEL: @uint32_4
-; CHECK: li [[REG1:[0-9]+]], 29
-; CHECK: sldi [[REG2:[0-9]+]], [[REG1]], 32
-; CHECK: oris [[REG3:[0-9]+]], [[REG2]], 3752
-; CHECK: ori 3, [[REG3]], 57376
+; CHECK: li [[REG1:[0-9]+]], 18177
+; CHECK: oris [[REG2:[0-9]+]], [[REG1]], 59509
+; CHECK: rldicr 3, [[REG2]], 5, 63
 ; CHECK: blr
 }
 
 define i64 @cn_ones_1() #0 {
 entry:
   ret i64 10460594175
 
 ; CHECK-LABEL: @cn_ones_1