[TableGen][GlobalISel] add handling of nested *_SUBREG

[ehjogab]

Summary

When nesting INSERT_SUBREG and EXTRACT_SUBREG, GlobalISelEmitter would
fail to find the register class of the nested node. This patch fixes
that for registers with subregs.

[arsenm]

llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td

33

This is missing the checks?

llvm/utils/TableGen/GlobalISelEmitter.cpp

4954

No else after return

4960

No else after return

[ehjogab]

• add missing check in testcase
• fix lint warnings

[ehjogab]

Oops, had missed that. Thanks!

[ehjogab]

llvm/utils/TableGen/GlobalISelEmitter.cpp

4954

In the original code, there is only an 'if' and no 'else', so I followed the same original structure by just adding the 'else if's. I believe the 'else' case is handled by the code that follow these if statements.

4960

Same as above.

[arsenm]

llvm/utils/TableGen/GlobalISelEmitter.cpp

4954

I don't see what you are saying. There was no else after return pattern here before, and I don't see how this is continuing it. The elses can be removed and this will be a sequence of if () { foo(); return }

[ehjogab]

llvm/utils/TableGen/GlobalISelEmitter.cpp

4954

Okay, I see what you're saying now. I'll fix it right away.

[ehjogab]

Removed else after return

[uabelho]

I submitted for ehjogab.

llvm/test/TableGen/GlobalISelEmitter-nested-subregs.td

+// RUN: llvm-tblgen %s -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common -o - | FileCheck %s
+
+include "llvm/Target/Target.td"
+include "GlobalISelEmitterCommon.td"
+
+let Namespace = "MyTarget" in {
+
+def lo8  : SubRegIndex<8>;
+def hi8  : SubRegIndex<8, 8>;
+def lo16 : SubRegIndex<16>;
+def hi16 : SubRegIndex<16, 16>;
+
+def a0bl : Register<"a0bl">;
+def a0bh : Register<"a0bh">;
+def a0wh : Register<"a0wh">;
+
+} // Namespace = "MyTarget"
+
+def a0wl: RegisterWithSubRegs<"a0", [a0bh, a0bl]> {
+  let SubRegIndices = [hi8, lo8];
+  let CoveredBySubRegs = 1;
+}
+
+def a0: RegisterWithSubRegs<"a0", [a0wh, a0wl]> {
+  let SubRegIndices = [hi16, lo16];
+  let CoveredBySubRegs = 1;
+}
+
+def A0b : RegisterClass<"MyTarget",  [i8],  8, (add a0bl)>;
+def A0w : RegisterClass<"MyTarget", [i16], 16, (add a0wl)>;
+def A0  : RegisterClass<"MyTarget", [i32], 32, (add a0)>;
+
+def : Pat<(i16 (anyext i8:$src)),
+          (i16 (EXTRACT_SUBREG
+                 (i32 (INSERT_SUBREG
+                        (i32 (IMPLICIT_DEF)),
+                        A0b:$src,
+                        lo8)),
+                 lo16))>;

llvm/utils/TableGen/GlobalISelEmitter.cpp

 //===- GlobalISelEmitter.cpp - Generate an instruction selector -----------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
GlobalISelEmitter::inferRegClassFromPattern(TreePatternNode *N) {
   bool IsRegSequence = InstName == "REG_SEQUENCE";
   if (IsRegSequence || InstName == "COPY_TO_REGCLASS") {
     // If we have a COPY_TO_REGCLASS, then we need to handle it specially. It
     // has the desired register class as the first child.
     TreePatternNode *RCChild = N->getChild(IsRegSequence ? 0 : 1);
     if (!RCChild->isLeaf())
       return None;
     return getRegClassFromLeaf(RCChild);
   }
+  else if (InstName == "INSERT_SUBREG") {
+    TreePatternNode *Child0 = N->getChild(0);
+    assert(Child0->getNumTypes() == 1 && "Unexpected number of types!");
+    const TypeSetByHwMode &VTy = Child0->getExtType(0);
+    return inferSuperRegisterClassForNode(VTy, Child0, N->getChild(2));
+  }
+  else if (InstName == "EXTRACT_SUBREG") {
+    assert(N->getNumTypes() == 1 && "Unexpected number of types!");
+    const TypeSetByHwMode &VTy = N->getExtType(0);
+    return inferSuperRegisterClass(VTy, N->getChild(1));
+  }
 
   // Handle destination record types that we can safely infer a register class
   // from.
   const auto &DstIOperand = Inst.Operands[0];
   Record *DstIOpRec = DstIOperand.Rec;
   if (DstIOpRec->isSubClassOf("RegisterOperand")) {
     DstIOpRec = DstIOpRec->getValueAsDef("RegClass");
     const CodeGenRegisterClass &RC = Target.getRegisterClass(DstIOpRec);