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ehjogab (Gabriel Hjort Åkerlund)
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Aug 12 2020, 4:46 AM (57 w, 4 d)

Recent Activity

Jan 26 2021

ehjogab added a comment to D86617: [GlobalISel][TableGen] Take first result for multi-output instructions.

Bump

Jan 26 2021, 12:47 AM · Restricted Project

Jan 19 2021

ehjogab updated the diff for D91244: [GlobalISel] Add missing operand update when copy is required.

Added changingInstr() before setReg()

Jan 19 2021, 11:47 PM · Restricted Project
ehjogab abandoned D93859: [GlobalISel][TableGen] Add BitsPerByte value.
Jan 19 2021, 10:30 PM · Restricted Project

Jan 18 2021

ehjogab added a comment to D91244: [GlobalISel] Add missing operand update when copy is required.

Any feedback on my latest comments?
Should the patch be accepted as is, or does it require more changes?

Jan 18 2021, 5:56 AM · Restricted Project

Jan 7 2021

ehjogab added inline comments to D91244: [GlobalISel] Add missing operand update when copy is required.
Jan 7 2021, 11:23 PM · Restricted Project

Jan 6 2021

ehjogab added a comment to D91244: [GlobalISel] Add missing operand update when copy is required.

@aditya_nandakumar Can you please take a look at this patch? We are unsure on whether the observer is used correctly here.

Jan 6 2021, 11:54 PM · Restricted Project
ehjogab added a reviewer for D91244: [GlobalISel] Add missing operand update when copy is required: aditya_nandakumar.
Jan 6 2021, 11:52 PM · Restricted Project
ehjogab added inline comments to D91244: [GlobalISel] Add missing operand update when copy is required.
Jan 6 2021, 11:50 PM · Restricted Project

Jan 5 2021

ehjogab added a comment to D86617: [GlobalISel][TableGen] Take first result for multi-output instructions.

Bump

Jan 5 2021, 6:43 AM · Restricted Project
ehjogab updated the diff for D91244: [GlobalISel] Add missing operand update when copy is required.

Machine operand is now updated in constrainOperandRegClass()

Jan 5 2021, 6:37 AM · Restricted Project

Jan 4 2021

ehjogab added inline comments to D91244: [GlobalISel] Add missing operand update when copy is required.
Jan 4 2021, 11:01 PM · Restricted Project

Dec 30 2020

ehjogab updated the diff for D93945: [GlobalISel][TableGen] Fix ConstrainOperandRC bug.

Fixed bad comment

Dec 30 2020, 7:00 AM · Restricted Project
ehjogab requested review of D93945: [GlobalISel][TableGen] Fix ConstrainOperandRC bug.
Dec 30 2020, 6:57 AM · Restricted Project

Dec 29 2020

ehjogab added a comment to D93859: [GlobalISel][TableGen] Add BitsPerByte value.

I believe it is calling the one in LowLevelTypeImpl.h.

Dec 29 2020, 12:10 AM · Restricted Project
ehjogab updated the diff for D93859: [GlobalISel][TableGen] Add BitsPerByte value.

Fix lint warnings
Add testcase

Dec 29 2020, 12:05 AM · Restricted Project

Dec 28 2020

ehjogab added a comment to D91244: [GlobalISel] Add missing operand update when copy is required.

Bump

Dec 28 2020, 6:57 AM · Restricted Project
ehjogab updated the diff for D93685: [MIRPrinter] Fix incorrect output of unnamed stack names.

Removed use of temporary file.

Dec 28 2020, 6:53 AM · Restricted Project
ehjogab requested review of D93859: [GlobalISel][TableGen] Add BitsPerByte value.
Dec 28 2020, 6:44 AM · Restricted Project

Dec 23 2020

ehjogab updated the diff for D93685: [MIRPrinter] Fix incorrect output of unnamed stack names.

Moved testcase to correct location
Split RUN into multiple lines
Added check of frame object list
Fixed failing testcase

Dec 23 2020, 12:22 AM · Restricted Project

Dec 22 2020

ehjogab added reviewers for D93685: [MIRPrinter] Fix incorrect output of unnamed stack names: dfukalov, jmorse, nhaehnle, arsenm.
Dec 22 2020, 3:31 AM · Restricted Project
ehjogab requested review of D93685: [MIRPrinter] Fix incorrect output of unnamed stack names.
Dec 22 2020, 3:29 AM · Restricted Project

Dec 14 2020

ehjogab added a comment to D86203: [GlobalISel][TableGen] Add handling of unannotated dst pattern ops.

Hm, I had another look at this and it seems that it's enough to provide either a register class or a value type. In both cases you enter the same if condition (see line 4266 in GlobalISelEmitter.cpp in this review), which checks that the child record is either a RegisterClass, RegisterOperand, or ValueType. If the check passes, it will output a GIR_COPY, which just copies the operand from one instruction (the one matched) to another (the instruction to emit) and hence does not look at the register class of the destination (that seems to be taken care of at a later stage, which does not look at the annotation of the operand in the pattern).

Dec 14 2020, 10:51 PM · Restricted Project

Dec 2 2020

ehjogab updated the diff for D90304: [GlobalISel] Introduce global variant of regbankselect.
  • Directly apply mapping of there is only one. This leads to improved performance as well as improved code quality for targets that only output a single mapping that is context-dependent (now only failing 32 testcases when forcing greedy to use global instead).
  • Bug fix
Dec 2 2020, 11:43 PM · Restricted Project

Nov 29 2020

ehjogab updated the diff for D90304: [GlobalISel] Introduce global variant of regbankselect.

More bugfixes

Nov 29 2020, 10:53 PM · Restricted Project

Nov 26 2020

ehjogab updated the diff for D92161: [GlobalISel] Remove duplicates from possible mappings.

Reduce number of necessary checks.

Nov 26 2020, 2:27 AM · Restricted Project
ehjogab requested review of D92161: [GlobalISel] Remove duplicates from possible mappings.
Nov 26 2020, 2:15 AM · Restricted Project
ehjogab updated the diff for D90304: [GlobalISel] Introduce global variant of regbankselect.

Bug fixes

Nov 26 2020, 2:09 AM · Restricted Project

Nov 24 2020

ehjogab updated the summary of D90304: [GlobalISel] Introduce global variant of regbankselect.
Nov 24 2020, 8:05 AM · Restricted Project
ehjogab updated the diff for D90304: [GlobalISel] Introduce global variant of regbankselect.

Use MappingCost instead of int for representing costs.

Nov 24 2020, 8:00 AM · Restricted Project
ehjogab updated the diff for D90304: [GlobalISel] Introduce global variant of regbankselect.

Bug fix

Nov 24 2020, 7:04 AM · Restricted Project
ehjogab updated the diff for D90304: [GlobalISel] Introduce global variant of regbankselect.
  • Improved selection: Now choosing the mapping with the highest utility instead of lowest cost, which should direct optimization towards blocks with high frequency.
  • Reduce vector copying.
Nov 24 2020, 7:00 AM · Restricted Project
ehjogab updated the diff for D90304: [GlobalISel] Introduce global variant of regbankselect.

Rearranged function declarations in RegBankSelect.cpp (NFC)

Nov 24 2020, 5:58 AM · Restricted Project
ehjogab added inline comments to D90304: [GlobalISel] Introduce global variant of regbankselect.
Nov 24 2020, 5:52 AM · Restricted Project
ehjogab updated the diff for D90304: [GlobalISel] Introduce global variant of regbankselect.

Rewrote code to make use of applyMapping(). Now fast, greedy, and global version
all use the same code for enforcing the selection of instruction mappings.

Nov 24 2020, 5:50 AM · Restricted Project

Nov 23 2020

ehjogab updated the diff for D90829: [GlobalISel][TableGen] Fix seg fault for zero instruction.

Missed a part of the CHECK

Nov 23 2020, 2:00 AM · Restricted Project
ehjogab updated the diff for D90829: [GlobalISel][TableGen] Fix seg fault for zero instruction.

Fixed testcase according to bjope's feedback

Nov 23 2020, 1:59 AM · Restricted Project
ehjogab retitled D90829: [GlobalISel][TableGen] Fix seg fault for zero instruction from [GlobalISel][TableGen] fix seg fault for zero instruction to [GlobalISel][TableGen] Fix seg fault for zero instruction.
Nov 23 2020, 1:49 AM · Restricted Project

Nov 17 2020

ehjogab updated the diff for D91519: [AST][Mach0] Fix unused-variable warnings.

Replace dyn_cast with isa

Nov 17 2020, 11:21 PM · Restricted Project, Restricted Project

Nov 16 2020

ehjogab requested review of D91520: [MachO] Fix enum-int mismatch warning.
Nov 16 2020, 12:57 AM · Restricted Project
ehjogab requested review of D91519: [AST][Mach0] Fix unused-variable warnings.
Nov 16 2020, 12:57 AM · Restricted Project, Restricted Project

Nov 13 2020

ehjogab added inline comments to D91244: [GlobalISel] Add missing operand update when copy is required.
Nov 13 2020, 1:39 AM · Restricted Project
ehjogab added a comment to D90304: [GlobalISel] Introduce global variant of regbankselect.

Sorry for being terse. What I meant to say, you could take an existing test case and show the effects of the different algorithms. There is probably an existing test case for the existing algorithms.

Nov 13 2020, 1:19 AM · Restricted Project

Nov 12 2020

ehjogab added a comment to D90304: [GlobalISel] Introduce global variant of regbankselect.

How about a test-case with fast, greedy, and global to show the differences?

Nov 12 2020, 4:57 AM · Restricted Project
ehjogab added a comment to D90304: [GlobalISel] Introduce global variant of regbankselect.

I haven't had the time to test this in the new state yet, but I would love to see this integrated. However I'm not in a position to review and approve this. Someone of the GlobalISel folks should do that. As for testing, ideally you could simply leverage the existing tests of the existing GlobalISel backends by enabling this algorithm conditionally. This also requires the approval of those backend maintainers however.

Maybe it would make sense to ping the mailing list again, explaining the current state, giving some numbers how this algorithm impacts compile time and code gen, and try to discuss some integration strategy.

Nov 12 2020, 2:36 AM · Restricted Project

Nov 11 2020

ehjogab added a comment to D90829: [GlobalISel][TableGen] Fix seg fault for zero instruction.

Added Paul-C-Anagnostopoulos since he's now one of the TableGen code owners.

Nov 11 2020, 11:13 PM · Restricted Project
ehjogab added a reviewer for D90829: [GlobalISel][TableGen] Fix seg fault for zero instruction: Paul-C-Anagnostopoulos.
Nov 11 2020, 11:13 PM · Restricted Project
ehjogab added inline comments to D90829: [GlobalISel][TableGen] Fix seg fault for zero instruction.
Nov 11 2020, 11:13 PM · Restricted Project
ehjogab added inline comments to D90829: [GlobalISel][TableGen] Fix seg fault for zero instruction.
Nov 11 2020, 11:11 PM · Restricted Project
ehjogab added a comment to D86617: [GlobalISel][TableGen] Take first result for multi-output instructions.

Added Paul-C-Anagnostopoulos since he's now one of the TableGen code owners.

Nov 11 2020, 11:09 PM · Restricted Project
ehjogab added a reviewer for D86617: [GlobalISel][TableGen] Take first result for multi-output instructions: Paul-C-Anagnostopoulos.
Nov 11 2020, 11:08 PM · Restricted Project
ehjogab requested review of D91244: [GlobalISel] Add missing operand update when copy is required.
Nov 11 2020, 3:41 AM · Restricted Project

Nov 9 2020

ehjogab added a comment to D86617: [GlobalISel][TableGen] Take first result for multi-output instructions.

Any comments? Should this patch be accepted or rejected?

I mostly see this as making the behavior more opaque by changing based on the specific register classes involved, so I'm not in favor. What do others think?

Nov 9 2020, 11:41 PM · Restricted Project
ehjogab added a comment to D90304: [GlobalISel] Introduce global variant of regbankselect.

So what happens now? Should it be merge as is, or does it need to be tested more stringently before that happens? Or are there any further changes that need to be made?

Nov 9 2020, 11:39 PM · Restricted Project
ehjogab added a comment to D90829: [GlobalISel][TableGen] Fix seg fault for zero instruction.

Bump

Nov 9 2020, 11:33 PM · Restricted Project

Nov 5 2020

ehjogab requested review of D90829: [GlobalISel][TableGen] Fix seg fault for zero instruction.
Nov 5 2020, 12:11 AM · Restricted Project

Nov 2 2020

ehjogab updated the diff for D90304: [GlobalISel] Introduce global variant of regbankselect.

replace 'optimal' with 'global'

Nov 2 2020, 6:09 AM · Restricted Project
ehjogab retitled D90304: [GlobalISel] Introduce global variant of regbankselect from [GlobalISel] Introduce optimal variant of regbankselect to [GlobalISel] Introduce global variant of regbankselect.
Nov 2 2020, 6:08 AM · Restricted Project
ehjogab added inline comments to D90304: [GlobalISel] Introduce global variant of regbankselect.
Nov 2 2020, 5:55 AM · Restricted Project
ehjogab updated the diff for D90304: [GlobalISel] Introduce global variant of regbankselect.
  • fix bug when register is a physical register
  • fix lint warnings
Nov 2 2020, 5:52 AM · Restricted Project

Oct 28 2020

ehjogab updated the diff for D90304: [GlobalISel] Introduce global variant of regbankselect.

Fixed arsenm's comment on MachineIRBuilder

Oct 28 2020, 11:42 PM · Restricted Project
ehjogab updated the diff for D90304: [GlobalISel] Introduce global variant of regbankselect.

Fixes based on arsenm's comments

Oct 28 2020, 11:28 PM · Restricted Project
ehjogab added inline comments to D90304: [GlobalISel] Introduce global variant of regbankselect.
Oct 28 2020, 11:08 PM · Restricted Project
ehjogab added inline comments to D90304: [GlobalISel] Introduce global variant of regbankselect.
Oct 28 2020, 11:06 PM · Restricted Project
ehjogab updated the diff for D90304: [GlobalISel] Introduce global variant of regbankselect.

Fix lint warnings

Oct 28 2020, 11:01 PM · Restricted Project
ehjogab added a comment to D90304: [GlobalISel] Introduce global variant of regbankselect.

Thank you very much for your feedback, arsenm! Really appreciate it!

Oct 28 2020, 10:18 PM · Restricted Project
ehjogab requested review of D90304: [GlobalISel] Introduce global variant of regbankselect.
Oct 28 2020, 6:25 AM · Restricted Project

Oct 12 2020

ehjogab added a comment to D86617: [GlobalISel][TableGen] Take first result for multi-output instructions.

Any comments? Should this patch be accepted or rejected?

Oct 12 2020, 1:40 AM · Restricted Project
ehjogab abandoned D86203: [GlobalISel][TableGen] Add handling of unannotated dst pattern ops.

Seems no one else is requesting this.

Oct 12 2020, 1:39 AM · Restricted Project

Oct 5 2020

ehjogab added a comment to D86617: [GlobalISel][TableGen] Take first result for multi-output instructions.

Bump

Oct 5 2020, 12:48 AM · Restricted Project

Oct 2 2020

ehjogab added a comment to D86203: [GlobalISel][TableGen] Add handling of unannotated dst pattern ops.

Does not annotating the output really buy you much? I think inconsistent behaviors in tablegen is a bigger obstacle to understanding patterns

Oct 2 2020, 2:40 AM · Restricted Project

Sep 30 2020

ehjogab added a comment to D86203: [GlobalISel][TableGen] Add handling of unannotated dst pattern ops.

Bump

Sep 30 2020, 7:16 AM · Restricted Project
ehjogab updated the diff for D86511: [GlobalISel] Fix incorrect setting of ValNo when splitting.

Rebased to latest (forgot to pull)

Sep 30 2020, 7:08 AM · Restricted Project
ehjogab updated the diff for D86511: [GlobalISel] Fix incorrect setting of ValNo when splitting.

Rebase to latest master

Sep 30 2020, 6:01 AM · Restricted Project
ehjogab updated the diff for D88487: [TableGen][GlobalISel] add handling of nested *_SUBREG.

Removed else after return

Sep 30 2020, 12:01 AM · Restricted Project

Sep 29 2020

ehjogab added inline comments to D88487: [TableGen][GlobalISel] add handling of nested *_SUBREG.
Sep 29 2020, 11:52 PM · Restricted Project
ehjogab added inline comments to D88487: [TableGen][GlobalISel] add handling of nested *_SUBREG.
Sep 29 2020, 7:50 AM · Restricted Project
ehjogab added a comment to D88487: [TableGen][GlobalISel] add handling of nested *_SUBREG.

Oops, had missed that. Thanks!

Sep 29 2020, 7:49 AM · Restricted Project
ehjogab updated the diff for D88487: [TableGen][GlobalISel] add handling of nested *_SUBREG.
  • add missing check in testcase
  • fix lint warnings
Sep 29 2020, 7:47 AM · Restricted Project
ehjogab requested review of D88487: [TableGen][GlobalISel] add handling of nested *_SUBREG.
Sep 29 2020, 6:58 AM · Restricted Project
ehjogab added a comment to D86617: [GlobalISel][TableGen] Take first result for multi-output instructions.

Needs test. I thought I handled this in ee3feef5aaaa3c385fbe08bdb2d48829ad440b56?

Sep 29 2020, 4:54 AM · Restricted Project
ehjogab updated the diff for D86617: [GlobalISel][TableGen] Take first result for multi-output instructions.

Added testcase

Sep 29 2020, 4:53 AM · Restricted Project

Sep 28 2020

ehjogab added a comment to D86203: [GlobalISel][TableGen] Add handling of unannotated dst pattern ops.

Is this still planned to be checked-in?

Sep 28 2020, 12:20 AM · Restricted Project

Aug 31 2020

ehjogab updated the diff for D86215: [TableGen][GlobalISel] Fix handling of zero_reg.

Reordered functions as per bjope's feedback

Aug 31 2020, 12:28 AM · Restricted Project

Aug 26 2020

ehjogab requested review of D86617: [GlobalISel][TableGen] Take first result for multi-output instructions.
Aug 26 2020, 5:52 AM · Restricted Project
ehjogab added a reviewer for D86215: [TableGen][GlobalISel] Fix handling of zero_reg: bjope.
Aug 26 2020, 5:06 AM · Restricted Project
ehjogab updated the summary of D86215: [TableGen][GlobalISel] Fix handling of zero_reg.
Aug 26 2020, 5:06 AM · Restricted Project
ehjogab updated the diff for D86215: [TableGen][GlobalISel] Fix handling of zero_reg.

Updated patch according to bjope's suggestion.

Aug 26 2020, 5:04 AM · Restricted Project
ehjogab updated the diff for D86203: [GlobalISel][TableGen] Add handling of unannotated dst pattern ops.

Added check that the register class to be annotated is allocatable and is not a union of other register classes.

Aug 26 2020, 4:33 AM · Restricted Project

Aug 25 2020

ehjogab added a comment to D86203: [GlobalISel][TableGen] Add handling of unannotated dst pattern ops.

What happens if the instruction operand uses an unallocatable pseudo-class combining register classes with different banks? I would expect it would need to check any of the bank possibilities

Hm, not sure what you mean. Could you provide a brief example?

The most common AMDGPU instructions define VS_* pseudoclasses for operand constraints. The two classes added have different register banks, since the instructions support directly reading from either.
e.g.
RegisterClass VS_32 = {VGPR_32RegClass, SGPR_32RegClass}, where both of these register classes are different banks.

In terms of selecting a particular operand, there's an additional hazard. We can't freely use SGPR_32 in a given operand without considering the context of the other operands. We avoid solving this in GlobalISel by always assigning these operands to VGPRRegBankID, and relying on a later pass to optimize out these copies. We're sorely missing a RegBank legality verifier check, so I'm not sure I would want the generated patterns to infer either bank is OK.

The operands of these VS_* instructions, are the defined (in the instruction) to use the VS_32 class, or VGPR_32/SGPR_32 classes? If it is the former, then what this patch would do is to use VS_32 in the patterns. If the patterns should really be using VGPR_32/SGPR_32, then this is a problem.

As I mentioned, the VS_32 is unallocatable and only exists to model the operand constraints. The actual operands should be either VGPR_32 or SGPR_32. Querying the register bank bank for VS_32 doesn't make any sense, and I suspect would assert.

However, you still have the option of annotating the pattern operands just as before, so this patch would not interfere with any patterns that today are accepted by TableGen. If it is the latter, then this patch would use whatever class (VGPR_32 or SGPR_32) that is specified for the corresponding operands in the instruction, so here I don't see there being any problem.

This would produce a broken import by default with unannotated patterns, which is undesirable. This still has the same problem before, but now all the patterns are broken and it's harder to find which ones need fixing.

Perhaps we could add an option that this feature is disabled by default, and by activating it you take responsibility to ensure that you don't have these kinds of situations for your target?

I think tablegen is hard enough to understand as is, and changing behaviors based on targets would make that problem worse.

Aug 25 2020, 1:56 AM · Restricted Project
ehjogab added a comment to D86511: [GlobalISel] Fix incorrect setting of ValNo when splitting.

I should mention that this is required for split arguments to work for our target, and it is possible that we're doing something wrong on our end. I don't see it, however, so I decided to submit this for review in hopes that someone either can tell me whether our backend is incorrectly implemented or this is indeed a bug in global-isel.

Aug 25 2020, 1:08 AM · Restricted Project
ehjogab requested review of D86511: [GlobalISel] Fix incorrect setting of ValNo when splitting.
Aug 25 2020, 12:59 AM · Restricted Project

Aug 24 2020

ehjogab added inline comments to D86215: [TableGen][GlobalISel] Fix handling of zero_reg.
Aug 24 2020, 8:18 AM · Restricted Project
ehjogab updated the diff for D86215: [TableGen][GlobalISel] Fix handling of zero_reg.

Forgot to update testcase.

Aug 24 2020, 8:14 AM · Restricted Project
ehjogab updated the diff for D86215: [TableGen][GlobalISel] Fix handling of zero_reg.

[TableGen][GlobalISel] Fix handling of zero_reg

Aug 24 2020, 8:12 AM · Restricted Project
ehjogab added inline comments to D86215: [TableGen][GlobalISel] Fix handling of zero_reg.
Aug 24 2020, 2:06 AM · Restricted Project

Aug 21 2020

ehjogab added a comment to D86203: [GlobalISel][TableGen] Add handling of unannotated dst pattern ops.

What happens if the instruction operand uses an unallocatable pseudo-class combining register classes with different banks? I would expect it would need to check any of the bank possibilities

Hm, not sure what you mean. Could you provide a brief example?

The most common AMDGPU instructions define VS_* pseudoclasses for operand constraints. The two classes added have different register banks, since the instructions support directly reading from either.
e.g.
RegisterClass VS_32 = {VGPR_32RegClass, SGPR_32RegClass}, where both of these register classes are different banks.

In terms of selecting a particular operand, there's an additional hazard. We can't freely use SGPR_32 in a given operand without considering the context of the other operands. We avoid solving this in GlobalISel by always assigning these operands to VGPRRegBankID, and relying on a later pass to optimize out these copies. We're sorely missing a RegBank legality verifier check, so I'm not sure I would want the generated patterns to infer either bank is OK.

The operands of these VS_* instructions, are the defined (in the instruction) to use the VS_32 class, or VGPR_32/SGPR_32 classes? If it is the former, then what this patch would do is to use VS_32 in the patterns. If the patterns should really be using VGPR_32/SGPR_32, then this is a problem. However, you still have the option of annotating the pattern operands just as before, so this patch would not interfere with any patterns that today are accepted by TableGen. If it is the latter, then this patch would use whatever class (VGPR_32 or SGPR_32) that is specified for the corresponding operands in the instruction, so here I don't see there being any problem.

Perhaps we could add an option that this feature is disabled by default, and by activating it you take responsibility to ensure that you don't have these kinds of situations for your target?

When a register class is an union of two or more classes then such problems bound to occur for one or more targets. Why not do such inference when it is obvious i.e. register class in instruction definition is a leaf register class and NOT an union of some base other base classes. I think this is better than having an runtime option to enable/disable the inference.
I think leaf classes can be detected programmatically.

Aug 21 2020, 4:35 AM · Restricted Project

Aug 20 2020

ehjogab added a comment to D86203: [GlobalISel][TableGen] Add handling of unannotated dst pattern ops.

What happens if the instruction operand uses an unallocatable pseudo-class combining register classes with different banks? I would expect it would need to check any of the bank possibilities

Hm, not sure what you mean. Could you provide a brief example?

The most common AMDGPU instructions define VS_* pseudoclasses for operand constraints. The two classes added have different register banks, since the instructions support directly reading from either.
e.g.
RegisterClass VS_32 = {VGPR_32RegClass, SGPR_32RegClass}, where both of these register classes are different banks.

In terms of selecting a particular operand, there's an additional hazard. We can't freely use SGPR_32 in a given operand without considering the context of the other operands. We avoid solving this in GlobalISel by always assigning these operands to VGPRRegBankID, and relying on a later pass to optimize out these copies. We're sorely missing a RegBank legality verifier check, so I'm not sure I would want the generated patterns to infer either bank is OK.

Aug 20 2020, 10:44 PM · Restricted Project
ehjogab added inline comments to D86215: [TableGen][GlobalISel] Fix handling of zero_reg.
Aug 20 2020, 10:31 PM · Restricted Project

Aug 19 2020

ehjogab abandoned D86200: [GlobalISel] Add setting of pointer flags to ArgInfo.

I'm curious why you need this. These fields are mostly a hack for SelectionDAG?

In our target argument pointers are converted into MVT::iPTRs, but in light of your comment that might be a bug in our backend. Could you comment on how, and if, MVT::iPTR are suppose to be used in GlobalISel, or are they only intended for SelectionISel?

Ideally MVT wouldn't be used at all, and we're just using the existing SelectionDAG calling convention lowering with its ties to MVT as a crutch. LLT naturally preserves that the value is a pointer with address space and size

Aug 19 2020, 11:53 PM · Restricted Project
ehjogab added inline comments to D86215: [TableGen][GlobalISel] Fix handling of zero_reg.
Aug 19 2020, 11:45 PM · Restricted Project