[mlir][openacc] Add wait operation

[clementval]

Summary

This patch introduce the wait operation that represent the OpenACC wait directive.

[mehdi_amini]

mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp

875

Can't this be expressed with the declarative assembly?

[clementval]

mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp

875

I’ll give it a try.

[clementval]

Rebase + switch to assemblyFormat

[clementval]

newline at end of file

[clementval]

mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp

875

Switched to assembly format in the new version of the patch.

[clementval]

Remove change not needed after switch to assembly format.

[rriddle]

mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td

343

Are these necessary?

mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp

811

Missing a return on each of these errors.

[clementval]

Address review comments

mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td

343

Was using these in the error message but they are not really necessary here. I just removed them.

[ftynse]

mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp

813

Nit: waitOp.waitOperands().size() == 0 -> waitOp.waitOperands().empty()

[clementval]

Rebase

mlir/include/mlir/Dialect/OpenACC/OpenACCOps.td

OpBuilder<"OpBuilder &builder, OperationState &result",
               [{ /* nothing to do */ }]>
   ];
 
   let verifier = ?;
 
   let assemblyFormat = "attr-dict ($operands^ `:` type($operands))?";
 }
 
+//===----------------------------------------------------------------------===//
+// 2.16.3. Wait Directive
+//===----------------------------------------------------------------------===//
+
+def OpenACC_WaitOp : OpenACC_Op<"wait", [AttrSizedOperandSegments]> {
+  let summary = "wait operation";
+
+  let description = [{
+    The "acc.wait" operation represents the OpenACC wait executable
+    directive.
+
+    Example:
+
+    ```mlir
+    acc.wait(%value1: index)
+    acc.wait() async(%async1: i32)
+    ```
+  }];
+
+  let arguments = (ins Variadic<IntOrIndex>:$waitOperands,
+                       Optional<IntOrIndex>:$asyncOperand,
+                       Optional<IntOrIndex>:$waitDevnum,
+                       UnitAttr:$async,
+                       Optional<I1>:$ifCond);
+
+  let assemblyFormat = [{
+    ( `(` $waitOperands^ `:` type($waitOperands) `)` )?
+    ( `async` `(` $asyncOperand^ `:` type($asyncOperand) `)` )?
+    ( `wait_devnum` `(` $waitDevnum^ `:` type($waitDevnum) `)` )?
+    ( `if` `(` $ifCond^ `)` )? attr-dict-with-keyword
+  }];
+}
+
 #endif // OPENACC_OPS

mlir/lib/Dialect/OpenACC/IR/OpenACC.cpp

static LogicalResult verifyLoopOp(acc::LoopOp loopOp) {
   if (loopOp.region().empty()) {
     loopOp.emitError("expected non-empty body.");
     return failure();
   }
 
   return success();
 }
 
+static LogicalResult verify(acc::WaitOp waitOp) {
+  // The async attribute represent the async clause without value. Therefore the
+  // attribute and operand cannot appear at the same time.
+  if (waitOp.asyncOperand() && waitOp.async())
+    return waitOp.emitError("async attribute cannot appear with asyncOperand");
+
+  if (waitOp.waitDevnum() && waitOp.waitOperands().size() == 0)
+    return waitOp.emitError("wait_devnum cannot appear without waitOperands");
+
+  return success();
+}
+
 #define GET_OP_CLASSES
 #include "mlir/Dialect/OpenACC/OpenACCOps.cpp.inc"

mlir/test/Dialect/OpenACC/invalid.mlir

 // -----
 
 // expected-error@+1 {{only one of auto, independent, seq can be present at the same time}}
 acc.loop {
   acc.yield
 } attributes {auto_, seq}
 
 // -----
+
+%cst = constant 1 : index
+// expected-error@+1 {{wait_devnum cannot appear without waitOperands}}
+acc.wait wait_devnum(%cst: index)
+
+// -----
+
+%cst = constant 1 : index
+// expected-error@+1 {{async attribute cannot appear with asyncOperand}}
+acc.wait async(%cst: index) attributes {async}

mlir/test/Dialect/OpenACC/ops.mlir

 // CHECK:      acc.data delete([[ARGA]]: memref<10xf32>, [[ARGB]]: memref<10xf32>, [[ARGC]]: memref<10x10xf32>) {
 // CHECK-NEXT: }
 // CHECK:      acc.data attach([[ARGA]]: memref<10xf32>, [[ARGB]]: memref<10xf32>, [[ARGC]]: memref<10x10xf32>) {
 // CHECK-NEXT: }
 // CHECK:      acc.data detach([[ARGA]]: memref<10xf32>, [[ARGB]]: memref<10xf32>, [[ARGC]]: memref<10x10xf32>) {
 // CHECK-NEXT: }
 // CHECK:      acc.data present([[ARGA]]: memref<10xf32>) copyin([[ARGB]]: memref<10xf32>) copyout([[ARGC]]: memref<10x10xf32>) {
 // CHECK-NEXT: }
+
+// -----
+
+%i64Value = constant 1 : i64
+%i32Value = constant 1 : i32
+%idxValue = constant 1 : index
+%ifCond = constant true
+acc.wait
+acc.wait(%i64Value: i64)
+acc.wait(%i32Value: i32)
+acc.wait(%idxValue: index)
+acc.wait(%i32Value, %idxValue : i32, index)
+acc.wait async(%i64Value: i64)
+acc.wait async(%i32Value: i32)
+acc.wait async(%idxValue: index)
+acc.wait(%i32Value: i32) async(%idxValue: index)
+acc.wait(%i64Value: i64) wait_devnum(%i32Value: i32)
+acc.wait attributes {async}
+acc.wait(%i64Value: i64) async(%idxValue: index) wait_devnum(%i32Value: i32)
+acc.wait if(%ifCond)
+
+// CHECK: [[I64VALUE:%.*]] = constant 1 : i64
+// CHECK: [[I32VALUE:%.*]] = constant 1 : i32
+// CHECK: [[IDXVALUE:%.*]] = constant 1 : index
+// CHECK: [[IFCOND:%.*]] = constant true
+// CHECK: acc.wait
+// CHECK: acc.wait([[I64VALUE]] : i64)
+// CHECK: acc.wait([[I32VALUE]] : i32)
+// CHECK: acc.wait([[IDXVALUE]] : index)
+// CHECK: acc.wait([[I32VALUE]], [[IDXVALUE]] : i32, index)
+// CHECK: acc.wait async([[I64VALUE]] : i64)
+// CHECK: acc.wait async([[I32VALUE]] : i32)
+// CHECK: acc.wait async([[IDXVALUE]] : index)
+// CHECK: acc.wait([[I32VALUE]] : i32) async([[IDXVALUE]] : index)
+// CHECK: acc.wait([[I64VALUE]] : i64) wait_devnum([[I32VALUE]] : i32)
+// CHECK: acc.wait attributes {async}
+// CHECK: acc.wait([[I64VALUE]] : i64) async([[IDXVALUE]] : index) wait_devnum([[I32VALUE]] : i32)
+// CHECK: acc.wait if([[IFCOND]])