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[SVE][CodeGen] Lower legal integer -> floating point conversions
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Authored by kmclaughlin on Sep 18 2020, 9:10 AM.

Details

Summary

This patch adds new ISD nodes, SCVTZ_MERGE_PASSTHRU &
UCVTZ_MERGE_PASSTHRU, which are used to lower both legal
scalable vector [S|U]INT_TO_FP operations and the following intrinsics:

  • llvm.aarch64.sve.scvtf
  • llvm.aarch64.sve.ucvtf

Diff Detail

Event Timeline

kmclaughlin created this revision.Sep 18 2020, 9:10 AM
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kmclaughlin requested review of this revision.Sep 18 2020, 9:10 AM
efriedma accepted this revision.Sep 18 2020, 12:28 PM

LGTM with one minor comment.

llvm/lib/Target/AArch64/AArch64ISelLowering.h
108

Might as well name these SINT_TO_FP_MERGE_PASSTHRU and UINT_TO_FP_MERGE_PASSTHRU. I know we had a long discussion about the names on the other patch, but this direction doesn't suffer from that problem. The intrinsic has exactly the same semantics as the SelectionDAG node.

This revision is now accepted and ready to land.Sep 18 2020, 12:28 PM
sdesmalen accepted this revision.Sep 22 2020, 5:47 AM

LGTM as well, thanks @kmclaughlin!

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
1436–1460

nit: can the formatting here be improved a bit?

This revision was landed with ongoing or failed builds.Sep 23 2020, 4:04 AM
This revision was automatically updated to reflect the committed changes.
kmclaughlin marked 2 inline comments as done.