[AMDGPU] Fix ROCm unit test memref initialization

[jerryyin]

Added createLowerToCFGPass for scf.for lowering

[jerryyin]

This comment was removed by jerryyin.

[jerryyin]

Remove accidental change to clang-format

[jerryyin]

Close as submmited fb182028361504569ff6322bfa12b12e1ab74e30

mlir/.clang-format

 BasedOnStyle: LLVM
-AlwaysBreakTemplateDeclarations: Yes
+#AlwaysBreakTemplateDeclarations: Yes
 

mlir/test/mlir-rocm-runner/vecadd.mlir

gpu.launch blocks(%bx, %by, %bz) in (%grid_x = %c1, %grid_y = %c1, %grid_z = %c1)
     store %c, %arg2[%tx] : memref<?xf32>
     gpu.terminator
   }
   return
 }
 
 // CHECK: [2.46, 2.46, 2.46, 2.46, 2.46]
 func @main() {
+  %c0 = constant 0 : index
+  %c1 = constant 1 : index
+  %c5 = constant 5 : index
+  %cf1dot23 = constant 1.23 : f32
   %0 = alloc() : memref<5xf32>
   %1 = alloc() : memref<5xf32>
   %2 = alloc() : memref<5xf32>
   %3 = memref_cast %0 : memref<5xf32> to memref<?xf32>
   %4 = memref_cast %1 : memref<5xf32> to memref<?xf32>
   %5 = memref_cast %2 : memref<5xf32> to memref<?xf32>
+  scf.for %i = %c0 to %c5 step %c1 {
+    store %cf1dot23, %3[%i] : memref<?xf32>
+    store %cf1dot23, %4[%i] : memref<?xf32>
+  }
   %6 = memref_cast %3 : memref<?xf32> to memref<*xf32>
   %7 = memref_cast %4 : memref<?xf32> to memref<*xf32>
   %8 = memref_cast %5 : memref<?xf32> to memref<*xf32>
   gpu.host_register %6 : memref<*xf32>
   gpu.host_register %7 : memref<*xf32>
   gpu.host_register %8 : memref<*xf32>
   %9 = call @mgpuMemGetDeviceMemRef1dFloat(%3) : (memref<?xf32>) -> (memref<?xf32>)
   %10 = call @mgpuMemGetDeviceMemRef1dFloat(%4) : (memref<?xf32>) -> (memref<?xf32>)

mlir/test/mlir-rocm-runner/vector-transferops.mlir

vector.transfer_write %c, %arg1[%base]
       vector<4xf32>, memref<?xf32>
 
     gpu.terminator
   }
   return
 }
 
 func @main() {
+  %c0 = constant 0 : index
+  %c1 = constant 1 : index
+  %c4 = constant 4 : index
   %cf1 = constant 1.0 : f32
+  %cf1dot23 = constant 1.23 : f32
 
   %arg0 = alloc() : memref<4xf32>
   %arg1 = alloc() : memref<4xf32>
 
   %22 = memref_cast %arg0 : memref<4xf32> to memref<?xf32>
   %23 = memref_cast %arg1 : memref<4xf32> to memref<?xf32>
 
+  scf.for %i = %c0 to %c4 step %c1 {
+    store %cf1dot23, %22[%i] : memref<?xf32>
+    store %cf1dot23, %23[%i] : memref<?xf32>
+  }
+ 
   %cast0 = memref_cast %22 : memref<?xf32> to memref<*xf32>
   %cast1 = memref_cast %23 : memref<?xf32> to memref<*xf32>
 
   gpu.host_register %cast0 : memref<*xf32>
   gpu.host_register %cast1 : memref<*xf32>
 
   %24 = call @mgpuMemGetDeviceMemRef1dFloat(%22) : (memref<?xf32>) -> (memref<?xf32>)
   %26 = call @mgpuMemGetDeviceMemRef1dFloat(%23) : (memref<?xf32>) -> (memref<?xf32>)

mlir/tools/mlir-rocm-runner/mlir-rocm-runner.cpp

 // latter.
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/ADT/STLExtras.h"
 
 #include "mlir/Conversion/GPUCommon/GPUCommonPass.h"
 #include "mlir/Conversion/GPUToROCDL/GPUToROCDLPass.h"
+#include "mlir/Conversion/SCFToStandard/SCFToStandard.h"
 #include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVM.h"
 #include "mlir/Conversion/StandardToLLVM/ConvertStandardToLLVMPass.h"
 #include "mlir/Dialect/GPU/GPUDialect.h"
 #include "mlir/Dialect/GPU/Passes.h"
 #include "mlir/Dialect/LLVMIR/LLVMDialect.h"
 #include "mlir/Dialect/LLVMIR/ROCDLDialect.h"
 #include "mlir/ExecutionEngine/JitRunner.h"
 #include "mlir/ExecutionEngine/OptUtils.h"
static LogicalResult runMLIRPasses(ModuleOp m) {
   // Configure target chip ISA version if it has not been specified.
   if (!targetChip.size())
     configTargetChip();
 
   // Configure target features per ROCm / HIP version.
   configTargetFeatures();
 
   const char gpuBinaryAnnotation[] = "rocdl.hsaco";
+  pm.addPass(createLowerToCFGPass());
   pm.addPass(createGpuKernelOutliningPass());
   auto &kernelPm = pm.nest<gpu::GPUModuleOp>();
   kernelPm.addPass(createStripDebugInfoPass());
   kernelPm.addPass(createLowerGpuOpsToROCDLOpsPass());
   kernelPm.addPass(createConvertGPUKernelToBlobPass(
       compileModuleToROCDLIR, compileISAToHsaco, tripleName, targetChip,
       features, gpuBinaryAnnotation));
   pm.addPass(createGpuToLLVMConversionPass(gpuBinaryAnnotation));