[DAGCombiner] Fold fminnum(X, NaN) to X

[nikic]

Summary

If one operand to FMINNUM and FMAXNUM is NaN, then the other operand is returned. This makes NaN a neutral element for these operations, which should improve the lowerings from D87391.

[spatel]

LGTM - I'll update the other patch after this lands.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

14064

Might as well handle the other pair too (possibly in a follow-up patch)? InstSimplify has:

// If one argument is NaN, return other or NaN appropriately.
bool PropagateNaN = IID == Intrinsic::minimum || IID == Intrinsic::maximum;
if (match(Op0, m_NaN()))
  return PropagateNaN ? Op0 : Op1;
if (match(Op1, m_NaN()))
  return PropagateNaN ? Op1 : Op0;

[nikic]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

14064

Good point! I went ahead and directly included it, together with some ARM tests (which conveniently supports both variants).

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

SDValue DAGCombiner::visitFNEG(SDNode *N) {
 
   if (SDValue Cast = foldSignChangeInBitcast(N))
     return Cast;
 
   return SDValue();
 }
 
 static SDValue visitFMinMax(SelectionDAG &DAG, SDNode *N,
-                            APFloat (*Op)(const APFloat &, const APFloat &)) {
+                            APFloat (*Op)(const APFloat &, const APFloat &),
+                            bool PropagatesNaN) {
   SDValue N0 = N->getOperand(0);
   SDValue N1 = N->getOperand(1);
   EVT VT = N->getValueType(0);
   const ConstantFPSDNode *N0CFP = isConstOrConstSplatFP(N0);
   const ConstantFPSDNode *N1CFP = isConstOrConstSplatFP(N1);
 
   if (N0CFP && N1CFP) {
     const APFloat &C0 = N0CFP->getValueAPF();
     const APFloat &C1 = N1CFP->getValueAPF();
     return DAG.getConstantFP(Op(C0, C1), SDLoc(N), VT);
   }
 
   // Canonicalize to constant on RHS.
   if (isConstantFPBuildVectorOrConstantFP(N0) &&
       !isConstantFPBuildVectorOrConstantFP(N1))
     return DAG.getNode(N->getOpcode(), SDLoc(N), VT, N1, N0);
 
+  // minnum(X, nan) -> X
+  // maxnum(X, nan) -> X
+  if (!PropagatesNaN && N1CFP && N1CFP->isNaN())
+    return N->getOperand(0);
+
   return SDValue();
 }
 
 SDValue DAGCombiner::visitFMINNUM(SDNode *N) {
-  return visitFMinMax(DAG, N, minnum);
+  return visitFMinMax(DAG, N, minnum, /* PropagatesNaN */ false);
 }
 
 SDValue DAGCombiner::visitFMAXNUM(SDNode *N) {
-  return visitFMinMax(DAG, N, maxnum);
+  return visitFMinMax(DAG, N, maxnum, /* PropagatesNaN */ false);
 }
 
 SDValue DAGCombiner::visitFMINIMUM(SDNode *N) {
-  return visitFMinMax(DAG, N, minimum);
+  return visitFMinMax(DAG, N, minimum, /* PropagatesNaN */ true);
 }
 
 SDValue DAGCombiner::visitFMAXIMUM(SDNode *N) {
-  return visitFMinMax(DAG, N, maximum);
+  return visitFMinMax(DAG, N, maximum, /* PropagatesNaN */ true);
 }
 
 SDValue DAGCombiner::visitFABS(SDNode *N) {
   SDValue N0 = N->getOperand(0);
   EVT VT = N->getValueType(0);
 
   // fold (fabs c1) -> fabs(c1)
   if (isConstantFPBuildVectorOrConstantFP(N0))

llvm/test/CodeGen/X86/fmaxnum.ll

 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vmaxss {{.*}}(%rip), %xmm0, %xmm0
 ; AVX-NEXT:    retq
   %r = call float @llvm.maxnum.f32(float %x, float 1.0)
   ret float %r
 }
 
 define float @test_maxnum_const_nan(float %x) {
-; SSE-LABEL: test_maxnum_const_nan:
-; SSE:       # %bb.0:
-; SSE-NEXT:    movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
-; SSE-NEXT:    movaps %xmm0, %xmm1
-; SSE-NEXT:    cmpunordss %xmm0, %xmm1
-; SSE-NEXT:    movaps %xmm1, %xmm3
-; SSE-NEXT:    andps %xmm2, %xmm3
-; SSE-NEXT:    maxss %xmm0, %xmm2
-; SSE-NEXT:    andnps %xmm2, %xmm1
-; SSE-NEXT:    orps %xmm3, %xmm1
-; SSE-NEXT:    movaps %xmm1, %xmm0
-; SSE-NEXT:    retq
-;
-; AVX1-LABEL: test_maxnum_const_nan:
-; AVX1:       # %bb.0:
-; AVX1-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; AVX1-NEXT:    vmaxss %xmm0, %xmm1, %xmm2
-; AVX1-NEXT:    vcmpunordss %xmm0, %xmm0, %xmm0
-; AVX1-NEXT:    vblendvps %xmm0, %xmm1, %xmm2, %xmm0
-; AVX1-NEXT:    retq
-;
-; AVX512-LABEL: test_maxnum_const_nan:
-; AVX512:       # %bb.0:
-; AVX512-NEXT:    vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
-; AVX512-NEXT:    vmaxss %xmm0, %xmm2, %xmm1
-; AVX512-NEXT:    vcmpunordss %xmm0, %xmm0, %k1
-; AVX512-NEXT:    vmovss %xmm2, %xmm1, %xmm1 {%k1}
-; AVX512-NEXT:    vmovaps %xmm1, %xmm0
-; AVX512-NEXT:    retq
+; CHECK-LABEL: test_maxnum_const_nan:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    retq
   %r = call float @llvm.maxnum.f32(float %x, float 0x7fff000000000000)
   ret float %r
 }
 
 attributes #0 = { "no-nans-fp-math"="true" }
 

llvm/test/CodeGen/X86/fminnum.ll

 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vminss {{.*}}(%rip), %xmm0, %xmm0
 ; AVX-NEXT:    retq
   %r = call float @llvm.minnum.f32(float %x, float 1.0)
   ret float %r
 }
 
 define float @test_minnum_const_nan(float %x) {
-; SSE-LABEL: test_minnum_const_nan:
-; SSE:       # %bb.0:
-; SSE-NEXT:    movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
-; SSE-NEXT:    movaps %xmm0, %xmm1
-; SSE-NEXT:    cmpunordss %xmm0, %xmm1
-; SSE-NEXT:    movaps %xmm1, %xmm3
-; SSE-NEXT:    andps %xmm2, %xmm3
-; SSE-NEXT:    minss %xmm0, %xmm2
-; SSE-NEXT:    andnps %xmm2, %xmm1
-; SSE-NEXT:    orps %xmm3, %xmm1
-; SSE-NEXT:    movaps %xmm1, %xmm0
-; SSE-NEXT:    retq
-;
-; AVX1-LABEL: test_minnum_const_nan:
-; AVX1:       # %bb.0:
-; AVX1-NEXT:    vmovss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; AVX1-NEXT:    vminss %xmm0, %xmm1, %xmm2
-; AVX1-NEXT:    vcmpunordss %xmm0, %xmm0, %xmm0
-; AVX1-NEXT:    vblendvps %xmm0, %xmm1, %xmm2, %xmm0
-; AVX1-NEXT:    retq
-;
-; AVX512-LABEL: test_minnum_const_nan:
-; AVX512:       # %bb.0:
-; AVX512-NEXT:    vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
-; AVX512-NEXT:    vminss %xmm0, %xmm2, %xmm1
-; AVX512-NEXT:    vcmpunordss %xmm0, %xmm0, %k1
-; AVX512-NEXT:    vmovss %xmm2, %xmm1, %xmm1 {%k1}
-; AVX512-NEXT:    vmovaps %xmm1, %xmm0
-; AVX512-NEXT:    retq
+; CHECK-LABEL: test_minnum_const_nan:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    retq
   %r = call float @llvm.minnum.f32(float %x, float 0x7fff000000000000)
   ret float %r
 }
 
 attributes #0 = { "no-nans-fp-math"="true" }