[PowerPC] [FPEnv] Disable strict FP mutation by default for PowerPC

[qiucf]

Summary

D70226 introduced a config IsStrictFPEnabled, which controls the strict floating point mutation (transforming some strict-fp operations into non-strict). This patch disables the mutation.

[uweigand]

We're finally there, great :-) LGTM.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

     MaxStoresPerMemcpy = 128;
     MaxStoresPerMemmove = 128;
     MaxLoadsPerMemcmp = 128;
   } else {
     MaxLoadsPerMemcmp = 8;
     MaxLoadsPerMemcmpOptSize = 4;
   }
 
+  IsStrictFPEnabled = true;
+
   // Let the subtarget (CPU) decide if a predictable select is more expensive
   // than the corresponding branch. This information is used in CGP to decide
   // when to convert selects into branches.
   PredictableSelectIsExpensive = Subtarget.isPredictableSelectIsExpensive();
 }
 
 /// getMaxByValAlign - Helper for getByValTypeAlignment to determine
 /// the desired ByVal argument alignment.

llvm/lib/Target/PowerPC/PPCInstrInfo.td

 def : Pat<(i32 (extloadi16 xaddr:$src)),
           (LHZX xaddr:$src)>;
 let Predicates = [HasFPU] in {
 def : Pat<(f64 (extloadf32 iaddr:$src)),
           (COPY_TO_REGCLASS (LFS iaddr:$src), F8RC)>;
 def : Pat<(f64 (extloadf32 xaddr:$src)),
           (COPY_TO_REGCLASS (LFSX xaddr:$src), F8RC)>;
 
-def : Pat<(f64 (fpextend f32:$src)),
+def : Pat<(f64 (any_fpextend f32:$src)),
           (COPY_TO_REGCLASS $src, F8RC)>;
 }
 
 // Only seq_cst fences require the heavyweight sync (SYNC 0).
 // All others can use the lightweight sync (SYNC 1).
 // source: http://www.cl.cam.ac.uk/~pes20/cpp/cpp0xmappings.html
 // The rule for seq_cst is duplicated to work with both 64 bits and 32 bits
 // versions of Power.

llvm/test/CodeGen/PowerPC/vector-constrained-fp-intrinsics.ll

 }
 
 define <3 x double> @constrained_vector_fpext_v3f32() #0 {
 ; PC64LE-LABEL: constrained_vector_fpext_v3f32:
 ; PC64LE:       # %bb.0: # %entry
 ; PC64LE-NEXT:    addis 3, 2, .LCPI133_0@toc@ha
 ; PC64LE-NEXT:    addis 4, 2, .LCPI133_1@toc@ha
 ; PC64LE-NEXT:    addis 5, 2, .LCPI133_2@toc@ha
-; PC64LE-NEXT:    lfs 1, .LCPI133_0@toc@l(3)
+; PC64LE-NEXT:    lfs 3, .LCPI133_0@toc@l(3)
 ; PC64LE-NEXT:    lfs 2, .LCPI133_1@toc@l(4)
-; PC64LE-NEXT:    lfs 3, .LCPI133_2@toc@l(5)
+; PC64LE-NEXT:    lfs 1, .LCPI133_2@toc@l(5)
 ; PC64LE-NEXT:    blr
 ;
 ; PC64LE9-LABEL: constrained_vector_fpext_v3f32:
 ; PC64LE9:       # %bb.0: # %entry
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI133_0@toc@ha
-; PC64LE9-NEXT:    lfs 1, .LCPI133_0@toc@l(3)
+; PC64LE9-NEXT:    lfs 3, .LCPI133_0@toc@l(3)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI133_1@toc@ha
 ; PC64LE9-NEXT:    lfs 2, .LCPI133_1@toc@l(3)
 ; PC64LE9-NEXT:    addis 3, 2, .LCPI133_2@toc@ha
-; PC64LE9-NEXT:    lfs 3, .LCPI133_2@toc@l(3)
+; PC64LE9-NEXT:    lfs 1, .LCPI133_2@toc@l(3)
 ; PC64LE9-NEXT:    blr
 entry:
   %result = call <3 x double> @llvm.experimental.constrained.fpext.v3f64.v3f32(
                                 <3 x float><float 42.0, float 43.0,
                                             float 44.0>,
                                 metadata !"fpexcept.strict") #1
   ret <3 x double> %result
 }