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Differential D87166

[GlobalISel] Add G_UNMERGE(Cst) -> Cst1, Cst2, ... combine
ClosedPublic

Authored by qcolombet on Sep 4 2020, 2:31 PM.

Details

Reviewers
aemerson
paquette
arsenm
volkan
Commits
rGa36278c2f8b5: [GlobalISel] Add G_UNMERGE(Cst) -> Cst1, Cst2, ... combine
Summary

Add a combiner helper that replaces G_UNMERGE of big constants into direct
use of smaller constants.

Diff Detail

Event Timeline

qcolombet created this revision.Sep 4 2020, 2:31 PM
Herald added a project: Restricted Project. · View Herald TranscriptSep 4 2020, 2:31 PM
Herald added subscribers: hiraditya, rovka. · View Herald Transcript
qcolombet requested review of this revision.Sep 4 2020, 2:31 PM
Herald added a subscriber: wdng. · View Herald TranscriptSep 4 2020, 2:31 PM
qcolombet added a parent revision: D87117: [GlobalISel] Add G_UNMERGE_VALUES(G_MERGE_VALUES) combine.Sep 4 2020, 2:32 PM
arsenm added inline comments.Sep 4 2020, 2:51 PM
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
1623–1624

Should also handle G_FCONSTANT

1628

isImm is illegal

Harbormaster completed remote builds in B70697: Diff 290029.Sep 4 2020, 3:19 PM
qcolombet updated this revision to Diff 290042.Sep 4 2020, 3:25 PM
  • Update AMDGPU tests
Herald added subscribers: kerbowa, nhaehnle, jvesely. · View Herald TranscriptSep 4 2020, 3:25 PM
qcolombet updated this revision to Diff 290043.Sep 4 2020, 3:30 PM
  • Remove getImm(), this is illegal for G_CONSTANT
qcolombet marked an inline comment as done.Sep 4 2020, 3:34 PM
qcolombet updated this revision to Diff 290047.Sep 4 2020, 3:49 PM
  • Add G_FCONSTANT support
qcolombet marked an inline comment as done.Sep 4 2020, 3:49 PM
qcolombet added inline comments.
llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
1623–1624

Good catch!

Harbormaster completed remote builds in B70706: Diff 290043.Sep 4 2020, 4:01 PM
Harbormaster completed remote builds in B70705: Diff 290042.Sep 4 2020, 4:03 PM
Harbormaster completed remote builds in B70709: Diff 290047.Sep 4 2020, 4:18 PM
qcolombet added a child revision: D87174: [GlobalISel] Add `X,Y<dead> = G_UNMERGE Z` -> X = G_TRUNC Z.Sep 4 2020, 6:30 PM
arsenm accepted this revision.Sep 11 2020, 2:06 PM
This revision is now accepted and ready to land.Sep 11 2020, 2:06 PM
Closed by commit rGa36278c2f8b5: [GlobalISel] Add G_UNMERGE(Cst) -> Cst1, Cst2, ... combine (authored by qcolombet). · Explain WhySep 14 2020, 4:31 PM
This revision was automatically updated to reflect the committed changes.
qcolombet marked an inline comment as done.
qcolombet added a commit: rGa36278c2f8b5: [GlobalISel] Add G_UNMERGE(Cst) -> Cst1, Cst2, ... combine.

Revision Contents

PathSize
llvm/
include/
llvm/
CodeGen/
GlobalISel/
6 lines
Target/
GlobalISel/
11 lines
lib/
CodeGen/
GlobalISel/
41 lines
test/
CodeGen/
AArch64/
GlobalISel/
89 lines
AMDGPU/
GlobalISel/
182 lines
160 lines
168 lines
182 lines
100 lines
104 lines

Diff 290042

llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h

Show First 20 Lines • Show All 245 Lines • ▼ Show 20 Linespublic:
/// Transform <ty,...> G_UNMERGE(G_MERGE ty X, Y, Z) -> ty X, Y, Z. /// Transform <ty,...> G_UNMERGE(G_MERGE ty X, Y, Z) -> ty X, Y, Z.
bool bool
matchCombineUnmergeMergeToPlainValues(MachineInstr &MI, matchCombineUnmergeMergeToPlainValues(MachineInstr &MI,
SmallVectorImpl<Register> &Operands); SmallVectorImpl<Register> &Operands);
bool bool
applyCombineUnmergeMergeToPlainValues(MachineInstr &MI, applyCombineUnmergeMergeToPlainValues(MachineInstr &MI,
SmallVectorImpl<Register> &Operands); SmallVectorImpl<Register> &Operands);
/// Transform G_UNMERGE Constant -> Constant1, Constant2, ...
bool matchCombineUnmergeConstant(MachineInstr &MI,
SmallVectorImpl<APInt> &Csts);
bool applyCombineUnmergeConstant(MachineInstr &MI,
SmallVectorImpl<APInt> &Csts);
/// Transform IntToPtr(PtrToInt(x)) to x if cast is in the same address space. /// Transform IntToPtr(PtrToInt(x)) to x if cast is in the same address space.
bool matchCombineI2PToP2I(MachineInstr &MI, Register &Reg); bool matchCombineI2PToP2I(MachineInstr &MI, Register &Reg);
bool applyCombineI2PToP2I(MachineInstr &MI, Register &Reg); bool applyCombineI2PToP2I(MachineInstr &MI, Register &Reg);
/// Transform PtrToInt(IntToPtr(x)) to x. /// Transform PtrToInt(IntToPtr(x)) to x.
bool matchCombineP2IToI2P(MachineInstr &MI, Register &Reg); bool matchCombineP2IToI2P(MachineInstr &MI, Register &Reg);
bool applyCombineP2IToI2P(MachineInstr &MI, Register &Reg); bool applyCombineP2IToI2P(MachineInstr &MI, Register &Reg);
▲ Show 20 Lines • Show All 140 Lines • Show Last 20 Lines

llvm/include/llvm/Target/GlobalISel/Combine.td

Show First 20 Lines • Show All 384 Lines • ▼ Show 20 Lines
def unmerge_merge_matchinfo : GIDefMatchData<"SmallVector<Register, 8>">; def unmerge_merge_matchinfo : GIDefMatchData<"SmallVector<Register, 8>">;
def unmerge_merge : GICombineRule< def unmerge_merge : GICombineRule<
(defs root:$d, unmerge_merge_matchinfo:$info), (defs root:$d, unmerge_merge_matchinfo:$info),
(match (wip_match_opcode G_UNMERGE_VALUES): $d, (match (wip_match_opcode G_UNMERGE_VALUES): $d,
[{ return Helper.matchCombineUnmergeMergeToPlainValues(*${d}, ${info}); }]), [{ return Helper.matchCombineUnmergeMergeToPlainValues(*${d}, ${info}); }]),
(apply [{ return Helper.applyCombineUnmergeMergeToPlainValues(*${d}, ${info}); }]) (apply [{ return Helper.applyCombineUnmergeMergeToPlainValues(*${d}, ${info}); }])
>; >;
// Fold (unmerge cst) -> cst1, cst2, ...
def unmerge_cst_matchinfo : GIDefMatchData<"SmallVector<APInt, 8>">;
def unmerge_cst : GICombineRule<
(defs root:$d, unmerge_cst_matchinfo:$info),
(match (wip_match_opcode G_UNMERGE_VALUES): $d,
[{ return Helper.matchCombineUnmergeConstant(*${d}, ${info}); }]),
(apply [{ return Helper.applyCombineUnmergeConstant(*${d}, ${info}); }])
>;
// FIXME: These should use the custom predicate feature once it lands. // FIXME: These should use the custom predicate feature once it lands.
def undef_combines : GICombineGroup<[undef_to_fp_zero, undef_to_int_zero, def undef_combines : GICombineGroup<[undef_to_fp_zero, undef_to_int_zero,
undef_to_negative_one, undef_to_negative_one,
propagate_undef_any_op, propagate_undef_any_op,
propagate_undef_all_ops, propagate_undef_all_ops,
propagate_undef_shuffle_mask, propagate_undef_shuffle_mask,
erase_undef_store]>; erase_undef_store]>;
Show All 12 Lines
def trivial_combines : GICombineGroup<[copy_prop, mul_to_shl, add_p2i_to_ptradd]>; def trivial_combines : GICombineGroup<[copy_prop, mul_to_shl, add_p2i_to_ptradd]>;
def all_combines : GICombineGroup<[trivial_combines, ptr_add_immed_chain, def all_combines : GICombineGroup<[trivial_combines, ptr_add_immed_chain,
combines_for_extload, combine_indexed_load_store, undef_combines, combines_for_extload, combine_indexed_load_store, undef_combines,
identity_combines, simplify_add_to_sub, identity_combines, simplify_add_to_sub,
hoist_logic_op_with_same_opcode_hands, hoist_logic_op_with_same_opcode_hands,
shl_ashr_to_sext_inreg, sext_inreg_of_load, shl_ashr_to_sext_inreg, sext_inreg_of_load,
width_reduction_combines, select_combines, width_reduction_combines, select_combines,
known_bits_simplifications, ext_ext_fold, known_bits_simplifications, ext_ext_fold,
not_cmp_fold, unmerge_merge]>; not_cmp_fold, unmerge_merge, unmerge_cst]>;

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

Show First 20 Lines • Show All 1,609 Lines • ▼ Show 20 Lines if (CanReuseInputDirectly)
replaceRegWith(MRI, DstReg, SrcReg); replaceRegWith(MRI, DstReg, SrcReg);
else else
Builder.buildCast(DstReg, SrcReg); Builder.buildCast(DstReg, SrcReg);
} }
MI.eraseFromParent(); MI.eraseFromParent();
return true; return true;
} }
bool CombinerHelper::matchCombineUnmergeConstant(MachineInstr &MI,
SmallVectorImpl<APInt> &Csts) {
unsigned SrcIdx = MI.getNumOperands() - 1;
Register SrcReg = MI.getOperand(SrcIdx).getReg();
MachineInstr *SrcInstr = MRI.getVRegDef(SrcReg);
if (SrcInstr->getOpcode() != TargetOpcode::G_CONSTANT)
return false;
arsenmUnsubmitted
Done
ReplyInline Actions

Should also handle G_FCONSTANT

arsenm: Should also handle G_FCONSTANT
qcolombetAuthorUnsubmitted
Done
ReplyInline Actions

Good catch!

qcolombet: Good catch!
// Break down the big constant in smaller ones.
const MachineOperand &CstVal = SrcInstr->getOperand(1);
unsigned BitWidth = MRI.getType(SrcReg).getSizeInBits();
APInt Val = CstVal.isImm() ? APInt(BitWidth, CstVal.getImm())
arsenmUnsubmitted
Done
ReplyInline Actions

isImm is illegal

arsenm: isImm is illegal
: CstVal.getCImm()->getValue();
LLT Dst0Ty = MRI.getType(MI.getOperand(0).getReg());
unsigned ShiftAmt = Dst0Ty.getSizeInBits();
// Unmerge a constant.
for (unsigned Idx = 0; Idx != SrcIdx; ++Idx) {
Csts.emplace_back(Val.trunc(ShiftAmt));
Val = Val.lshr(ShiftAmt);
}
return true;
}
bool CombinerHelper::applyCombineUnmergeConstant(MachineInstr &MI,
SmallVectorImpl<APInt> &Csts) {
assert(MI.getOpcode() == TargetOpcode::G_UNMERGE_VALUES &&
"Expected an unmerge");
assert((MI.getNumOperands() - 1 == Csts.size()) &&
"Not enough operands to replace all defs");
unsigned NumElems = MI.getNumOperands() - 1;
Builder.setInstrAndDebugLoc(MI);
for (unsigned Idx = 0; Idx < NumElems; ++Idx) {
Register DstReg = MI.getOperand(Idx).getReg();
Builder.buildConstant(DstReg, Csts[Idx]);
}
MI.eraseFromParent();
return true;
}
bool CombinerHelper::matchCombineShiftToUnmerge(MachineInstr &MI, bool CombinerHelper::matchCombineShiftToUnmerge(MachineInstr &MI,
unsigned TargetShiftSize, unsigned TargetShiftSize,
unsigned &ShiftVal) { unsigned &ShiftVal) {
assert((MI.getOpcode() == TargetOpcode::G_SHL || assert((MI.getOpcode() == TargetOpcode::G_SHL ||
MI.getOpcode() == TargetOpcode::G_LSHR || MI.getOpcode() == TargetOpcode::G_LSHR ||
MI.getOpcode() == TargetOpcode::G_ASHR) && "Expected a shift"); MI.getOpcode() == TargetOpcode::G_ASHR) && "Expected a shift");
LLT Ty = MRI.getType(MI.getOperand(0).getReg()); LLT Ty = MRI.getType(MI.getOperand(0).getReg());
▲ Show 20 Lines • Show All 744 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/GlobalISel/combine-unmerge.mir

Show First 20 Lines • Show All 175 Lines • ▼ Show 20 Lines bb.1:
%1:_(<2 x s16>) = COPY $w1 %1:_(<2 x s16>) = COPY $w1
%2:_(<4 x s16>) = G_CONCAT_VECTORS %0(<2 x s16>), %1(<2 x s16>) %2:_(<4 x s16>) = G_CONCAT_VECTORS %0(<2 x s16>), %1(<2 x s16>)
%5:_(s64) = G_BITCAST %2(<4 x s16>) %5:_(s64) = G_BITCAST %2(<4 x s16>)
%3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %5(s64) %3:_(s32), %4:_(s32) = G_UNMERGE_VALUES %5(s64)
$w0 = COPY %3(s32) $w0 = COPY %3(s32)
$w1 = COPY %4(s32) $w1 = COPY %4(s32)
... ...
# Unmerge a constant into a bunch of smaller constant.
# Constant is 0x0102030405060708090a0b0c0d0e0f10 and we break it down into
# bytes:
# cst1 0x10
# cst2 0x0f
# cst3 0x0e
# ...
---
name: test_combine_unmerge_cst
body: |
bb.1:
; CHECK-LABEL: name: test_combine_unmerge_cst
; CHECK: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 16
; CHECK: [[C1:%[0-9]+]]:_(s8) = G_CONSTANT i8 15
; CHECK: [[C2:%[0-9]+]]:_(s8) = G_CONSTANT i8 14
; CHECK: [[C3:%[0-9]+]]:_(s8) = G_CONSTANT i8 13
; CHECK: [[C4:%[0-9]+]]:_(s8) = G_CONSTANT i8 12
; CHECK: [[C5:%[0-9]+]]:_(s8) = G_CONSTANT i8 11
; CHECK: [[C6:%[0-9]+]]:_(s8) = G_CONSTANT i8 10
; CHECK: [[C7:%[0-9]+]]:_(s8) = G_CONSTANT i8 9
; CHECK: [[C8:%[0-9]+]]:_(s8) = G_CONSTANT i8 8
; CHECK: [[C9:%[0-9]+]]:_(s8) = G_CONSTANT i8 7
; CHECK: [[C10:%[0-9]+]]:_(s8) = G_CONSTANT i8 6
; CHECK: [[C11:%[0-9]+]]:_(s8) = G_CONSTANT i8 5
; CHECK: [[C12:%[0-9]+]]:_(s8) = G_CONSTANT i8 4
; CHECK: [[C13:%[0-9]+]]:_(s8) = G_CONSTANT i8 3
; CHECK: [[C14:%[0-9]+]]:_(s8) = G_CONSTANT i8 2
; CHECK: [[C15:%[0-9]+]]:_(s8) = G_CONSTANT i8 1
; CHECK: $b0 = COPY [[C]](s8)
; CHECK: $b1 = COPY [[C1]](s8)
; CHECK: $b2 = COPY [[C2]](s8)
; CHECK: $b3 = COPY [[C3]](s8)
; CHECK: $b4 = COPY [[C4]](s8)
; CHECK: $b5 = COPY [[C5]](s8)
; CHECK: $b6 = COPY [[C6]](s8)
; CHECK: $b7 = COPY [[C7]](s8)
; CHECK: $b8 = COPY [[C8]](s8)
; CHECK: $b9 = COPY [[C9]](s8)
; CHECK: $b10 = COPY [[C10]](s8)
; CHECK: $b11 = COPY [[C11]](s8)
; CHECK: $b12 = COPY [[C12]](s8)
; CHECK: $b13 = COPY [[C13]](s8)
; CHECK: $b14 = COPY [[C14]](s8)
; CHECK: $b15 = COPY [[C15]](s8)
%0:_(s128) = G_CONSTANT i128 1339673755198158349044581307228491536
%1:_(s8),%2:_(s8),%3:_(s8),%4:_(s8),%5:_(s8),%6:_(s8),%7:_(s8),%8:_(s8),%9:_(s8),%10:_(s8),%11:_(s8),%12:_(s8),%13:_(s8),%14:_(s8),%15:_(s8),%16:_(s8) = G_UNMERGE_VALUES %0(s128)
$b0 = COPY %1(s8)
$b1 = COPY %2(s8)
$b2 = COPY %3(s8)
$b3 = COPY %4(s8)
$b4 = COPY %5(s8)
$b5 = COPY %6(s8)
$b6 = COPY %7(s8)
$b7 = COPY %8(s8)
$b8 = COPY %9(s8)
$b9 = COPY %10(s8)
$b10 = COPY %11(s8)
$b11 = COPY %12(s8)
$b12 = COPY %13(s8)
$b13 = COPY %14(s8)
$b14 = COPY %15(s8)
$b15 = COPY %16(s8)
...
# Unmerge a constant on a non-power of 2 type into a bunch of smaller constant.
# Constant is a 3 | 2 | 1 in chunks of 13-bit.
---
name: test_combine_unmerge_cst_36bit
body: |
bb.1:
; CHECK-LABEL: name: test_combine_unmerge_cst_36bit
; CHECK: [[C:%[0-9]+]]:_(s13) = G_CONSTANT i13 1
; CHECK: [[C1:%[0-9]+]]:_(s13) = G_CONSTANT i13 2
; CHECK: [[C2:%[0-9]+]]:_(s13) = G_CONSTANT i13 3
; CHECK: [[ZEXT:%[0-9]+]]:_(s16) = G_ZEXT [[C]](s13)
; CHECK: [[ZEXT1:%[0-9]+]]:_(s16) = G_ZEXT [[C1]](s13)
; CHECK: [[ZEXT2:%[0-9]+]]:_(s16) = G_ZEXT [[C2]](s13)
; CHECK: $h0 = COPY [[ZEXT]](s16)
; CHECK: $h1 = COPY [[ZEXT1]](s16)
; CHECK: $h2 = COPY [[ZEXT2]](s16)
%0:_(s39) = G_CONSTANT i39 201342977
%1:_(s13),%2:_(s13),%3:_(s13) = G_UNMERGE_VALUES %0(s39)
%4:_(s16) = G_ZEXT %1(s13)
%5:_(s16) = G_ZEXT %2(s13)
%6:_(s16) = G_ZEXT %3(s13)
$h0 = COPY %4(s16)
$h1 = COPY %5(s16)
$h2 = COPY %6(s16)
...

llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 4,993 Lines • ▼ Show 20 Lines
; GFX6-LABEL: v_saddsat_v2i64: ; GFX6-LABEL: v_saddsat_v2i64:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_add_i32_e32 v8, vcc, v0, v4 ; GFX6-NEXT: v_add_i32_e32 v8, vcc, v0, v4
; GFX6-NEXT: v_addc_u32_e32 v9, vcc, v1, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v9, vcc, v1, v5, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[8:9], v[0:1] ; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[8:9], v[0:1]
; GFX6-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[4:5] ; GFX6-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[4:5]
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v9 ; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v9
; GFX6-NEXT: s_brev_b32 s8, 1 ; GFX6-NEXT: v_bfrev_b32_e32 v10, 1
; GFX6-NEXT: v_mov_b32_e32 v1, s8 ; GFX6-NEXT: v_add_i32_e64 v1, s[6:7], 0, v0
; GFX6-NEXT: v_add_i32_e64 v4, s[6:7], 0, v0
; GFX6-NEXT: s_xor_b64 vcc, s[4:5], vcc ; GFX6-NEXT: s_xor_b64 vcc, s[4:5], vcc
; GFX6-NEXT: v_addc_u32_e64 v1, s[6:7], v0, v1, s[6:7] ; GFX6-NEXT: v_addc_u32_e64 v4, s[6:7], v0, v10, s[6:7]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v8, v4, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v8, v1, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc
; GFX6-NEXT: v_add_i32_e32 v4, vcc, v2, v6 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, v2, v6
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v3, v7, vcc ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, v3, v7, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[2:3] ; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[2:3]
; GFX6-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[6:7] ; GFX6-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[6:7]
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v5 ; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v5
; GFX6-NEXT: v_mov_b32_e32 v3, s8 ; GFX6-NEXT: v_add_i32_e64 v3, s[6:7], 0, v2
; GFX6-NEXT: v_add_i32_e64 v6, s[6:7], 0, v2 ; GFX6-NEXT: v_addc_u32_e64 v6, s[6:7], v2, v10, s[6:7]
; GFX6-NEXT: v_addc_u32_e64 v3, s[6:7], v2, v3, s[6:7]
; GFX6-NEXT: s_xor_b64 vcc, s[4:5], vcc ; GFX6-NEXT: s_xor_b64 vcc, s[4:5], vcc
; GFX6-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v2, v4, v3, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31] ; GFX6-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-LABEL: v_saddsat_v2i64: ; GFX8-LABEL: v_saddsat_v2i64:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_add_u32_e32 v8, vcc, v0, v4 ; GFX8-NEXT: v_add_u32_e32 v8, vcc, v0, v4
; GFX8-NEXT: v_addc_u32_e32 v9, vcc, v1, v5, vcc ; GFX8-NEXT: v_addc_u32_e32 v9, vcc, v1, v5, vcc
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[8:9], v[0:1] ; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[8:9], v[0:1]
; GFX8-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[4:5] ; GFX8-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[4:5]
; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v9 ; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v9
; GFX8-NEXT: s_brev_b32 s8, 1 ; GFX8-NEXT: v_bfrev_b32_e32 v10, 1
; GFX8-NEXT: v_mov_b32_e32 v1, s8 ; GFX8-NEXT: v_add_u32_e64 v1, s[6:7], 0, v0
; GFX8-NEXT: v_add_u32_e64 v4, s[6:7], 0, v0
; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
; GFX8-NEXT: v_addc_u32_e64 v1, s[6:7], v0, v1, s[6:7] ; GFX8-NEXT: v_addc_u32_e64 v4, s[6:7], v0, v10, s[6:7]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v8, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v8, v1, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc
; GFX8-NEXT: v_add_u32_e32 v4, vcc, v2, v6 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, v2, v6
; GFX8-NEXT: v_addc_u32_e32 v5, vcc, v3, v7, vcc ; GFX8-NEXT: v_addc_u32_e32 v5, vcc, v3, v7, vcc
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[2:3] ; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[2:3]
; GFX8-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[6:7] ; GFX8-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[6:7]
; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v5 ; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v5
; GFX8-NEXT: v_mov_b32_e32 v3, s8 ; GFX8-NEXT: v_add_u32_e64 v3, s[6:7], 0, v2
; GFX8-NEXT: v_add_u32_e64 v6, s[6:7], 0, v2 ; GFX8-NEXT: v_addc_u32_e64 v6, s[6:7], v2, v10, s[6:7]
; GFX8-NEXT: v_addc_u32_e64 v3, s[6:7], v2, v3, s[6:7]
; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v3, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-LABEL: v_saddsat_v2i64: ; GFX9-LABEL: v_saddsat_v2i64:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v0, v4 ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v0, v4
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v1, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v1, v5, vcc
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[8:9], v[0:1] ; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[8:9], v[0:1]
; GFX9-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[4:5] ; GFX9-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[4:5]
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v9 ; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v9
; GFX9-NEXT: s_brev_b32 s8, 1 ; GFX9-NEXT: v_bfrev_b32_e32 v10, 1
; GFX9-NEXT: v_mov_b32_e32 v1, s8 ; GFX9-NEXT: v_add_co_u32_e64 v1, s[6:7], 0, v0
; GFX9-NEXT: v_add_co_u32_e64 v4, s[6:7], 0, v0
; GFX9-NEXT: s_xor_b64 vcc, s[4:5], vcc ; GFX9-NEXT: s_xor_b64 vcc, s[4:5], vcc
; GFX9-NEXT: v_addc_co_u32_e64 v1, s[6:7], v0, v1, s[6:7] ; GFX9-NEXT: v_addc_co_u32_e64 v4, s[6:7], v0, v10, s[6:7]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v8, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v8, v1, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v2, v6 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, v2, v6
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v3, v7, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, v3, v7, vcc
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[2:3] ; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[2:3]
; GFX9-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[6:7] ; GFX9-NEXT: v_cmp_gt_i64_e64 s[4:5], 0, v[6:7]
; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v5 ; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v5
; GFX9-NEXT: v_mov_b32_e32 v3, s8 ; GFX9-NEXT: v_add_co_u32_e64 v3, s[6:7], 0, v2
; GFX9-NEXT: v_add_co_u32_e64 v6, s[6:7], 0, v2 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[6:7], v2, v10, s[6:7]
; GFX9-NEXT: v_addc_co_u32_e64 v3, s[6:7], v2, v3, s[6:7]
; GFX9-NEXT: s_xor_b64 vcc, s[4:5], vcc ; GFX9-NEXT: s_xor_b64 vcc, s[4:5], vcc
; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_saddsat_v2i64: ; GFX10-LABEL: v_saddsat_v2i64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_mov_b32_e32 v9, v0 ; GFX10-NEXT: v_mov_b32_e32 v14, v0
; GFX10-NEXT: v_mov_b32_e32 v10, v1 ; GFX10-NEXT: v_mov_b32_e32 v15, v1
; GFX10-NEXT: v_mov_b32_e32 v13, v2 ; GFX10-NEXT: v_mov_b32_e32 v17, v2
; GFX10-NEXT: v_mov_b32_e32 v14, v3 ; GFX10-NEXT: v_mov_b32_e32 v18, v3
; GFX10-NEXT: v_cmp_gt_i64_e64 s4, 0, v[4:5] ; GFX10-NEXT: v_cmp_gt_i64_e64 s4, 0, v[4:5]
; GFX10-NEXT: v_add_co_u32_e64 v19, vcc_lo, v9, v4 ; GFX10-NEXT: v_add_co_u32_e64 v8, vcc_lo, v14, v4
; GFX10-NEXT: s_brev_b32 s8, 1
; GFX10-NEXT: v_add_co_ci_u32_e32 v20, vcc_lo, v10, v5, vcc_lo
; GFX10-NEXT: v_add_co_u32_e64 v23, vcc_lo, v13, v6
; GFX10-NEXT: v_cmp_gt_i64_e64 s6, 0, v[6:7] ; GFX10-NEXT: v_cmp_gt_i64_e64 s6, 0, v[6:7]
; GFX10-NEXT: v_add_co_ci_u32_e32 v24, vcc_lo, v14, v7, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v9, vcc_lo, v15, v5, vcc_lo
; GFX10-NEXT: v_add_co_u32_e64 v19, vcc_lo, v17, v6
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: v_add_co_ci_u32_e32 v20, vcc_lo, v18, v7, vcc_lo
; GFX10-NEXT: v_ashrrev_i32_e32 v12, 31, v9
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[8:9], v[14:15]
; GFX10-NEXT: v_ashrrev_i32_e32 v0, 31, v20 ; GFX10-NEXT: v_ashrrev_i32_e32 v0, 31, v20
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[19:20], v[9:10] ; GFX10-NEXT: v_add_co_u32_e64 v1, s5, v12, 0
; GFX10-NEXT: v_ashrrev_i32_e32 v1, 31, v24 ; GFX10-NEXT: v_add_co_ci_u32_e64 v4, s5, 0x80000000, v12, s5
; GFX10-NEXT: v_add_co_u32_e64 v4, s5, v0, 0 ; GFX10-NEXT: v_cmp_lt_i64_e64 s5, v[19:20], v[17:18]
; GFX10-NEXT: v_add_co_ci_u32_e64 v5, s5, s8, v0, s5 ; GFX10-NEXT: v_add_co_u32_e64 v2, s7, v0, 0
; GFX10-NEXT: v_cmp_lt_i64_e64 s5, v[23:24], v[13:14]
; GFX10-NEXT: v_add_co_u32_e64 v2, s7, v1, 0
; GFX10-NEXT: s_xor_b32 vcc_lo, s4, vcc_lo ; GFX10-NEXT: s_xor_b32 vcc_lo, s4, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s7, s8, v1, s7 ; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s7, 0x80000000, v0, s7
; GFX10-NEXT: v_cndmask_b32_e32 v0, v19, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v8, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v20, v5, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc_lo
; GFX10-NEXT: s_xor_b32 vcc_lo, s6, s5 ; GFX10-NEXT: s_xor_b32 vcc_lo, s6, s5
; GFX10-NEXT: v_cndmask_b32_e32 v2, v23, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v20, v3, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs) %result = call <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
ret <2 x i64> %result ret <2 x i64> %result
} }
define amdgpu_ps <2 x i64> @s_saddsat_v2i64(<2 x i64> inreg %lhs, <2 x i64> inreg %rhs) { define amdgpu_ps <2 x i64> @s_saddsat_v2i64(<2 x i64> inreg %lhs, <2 x i64> inreg %rhs) {
; GFX6-LABEL: s_saddsat_v2i64: ; GFX6-LABEL: s_saddsat_v2i64:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
▲ Show 20 Lines • Show All 1,104 Lines • ▼ Show 20 Lines
; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 ; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX6-NEXT: s_and_b32 s4, 1, s5 ; GFX6-NEXT: s_and_b32 s4, 1, s5
; GFX6-NEXT: v_ashr_i64 v[8:9], v[18:19], s6 ; GFX6-NEXT: v_ashr_i64 v[8:9], v[18:19], s6
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, s4 ; GFX6-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, s4
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX6-NEXT: v_ashrrev_i32_e32 v11, 31, v19 ; GFX6-NEXT: v_ashrrev_i32_e32 v11, 31, v19
; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v16, s[4:5] ; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v16, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v17, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v2, v11, v8, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v2, v11, v8, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v17, s[4:5]
; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0, v0
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX6-NEXT: s_brev_b32 s4, 1 ; GFX6-NEXT: v_bfrev_b32_e32 v20, 1
; GFX6-NEXT: v_mov_b32_e32 v8, s4
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v20, vcc
; GFX6-NEXT: v_and_b32_e32 v8, 1, v10 ; GFX6-NEXT: v_and_b32_e32 v8, 1, v10
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX6-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
; GFX6-NEXT: v_add_i32_e32 v8, vcc, v4, v12 ; GFX6-NEXT: v_add_i32_e32 v8, vcc, v4, v12
; GFX6-NEXT: v_addc_u32_e32 v9, vcc, v5, v13, vcc ; GFX6-NEXT: v_addc_u32_e32 v9, vcc, v5, v13, vcc
; GFX6-NEXT: v_addc_u32_e32 v10, vcc, v6, v14, vcc ; GFX6-NEXT: v_addc_u32_e32 v10, vcc, v6, v14, vcc
; GFX6-NEXT: v_addc_u32_e32 v11, vcc, v7, v15, vcc ; GFX6-NEXT: v_addc_u32_e32 v11, vcc, v7, v15, vcc
; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] ; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
; GFX6-NEXT: s_cmp_lt_u32 s6, 64 ; GFX6-NEXT: s_cmp_lt_u32 s6, 64
; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7] ; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7]
; GFX6-NEXT: s_cselect_b32 s5, 1, 0 ; GFX6-NEXT: s_cselect_b32 s4, 1, 0
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7] ; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7]
; GFX6-NEXT: s_cmp_eq_u32 s6, 0 ; GFX6-NEXT: s_cmp_eq_u32 s6, 0
; GFX6-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
; GFX6-NEXT: v_cmp_gt_u64_e32 vcc, 0, v[12:13] ; GFX6-NEXT: v_cmp_gt_u64_e32 vcc, 0, v[12:13]
; GFX6-NEXT: s_cselect_b32 s9, 1, 0 ; GFX6-NEXT: s_cselect_b32 s5, 1, 0
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX6-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[14:15] ; GFX6-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[14:15]
; GFX6-NEXT: v_ashr_i64 v[12:13], v[10:11], s6 ; GFX6-NEXT: v_ashr_i64 v[12:13], v[10:11], s6
; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15] ; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15]
; GFX6-NEXT: v_ashrrev_i32_e32 v15, 31, v11 ; GFX6-NEXT: s_and_b32 s5, 1, s5
; GFX6-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
; GFX6-NEXT: v_xor_b32_e32 v14, v5, v4 ; GFX6-NEXT: v_xor_b32_e32 v14, v5, v4
; GFX6-NEXT: v_lshr_b64 v[4:5], v[8:9], s6 ; GFX6-NEXT: v_lshr_b64 v[4:5], v[8:9], s6
; GFX6-NEXT: v_lshl_b64 v[6:7], v[10:11], s8 ; GFX6-NEXT: v_lshl_b64 v[6:7], v[10:11], s8
; GFX6-NEXT: s_and_b32 s6, 1, s5 ; GFX6-NEXT: s_and_b32 s6, 1, s4
; GFX6-NEXT: v_or_b32_e32 v6, v4, v6 ; GFX6-NEXT: v_or_b32_e32 v6, v4, v6
; GFX6-NEXT: v_or_b32_e32 v7, v5, v7 ; GFX6-NEXT: v_or_b32_e32 v7, v5, v7
; GFX6-NEXT: v_ashr_i64 v[4:5], v[10:11], s7 ; GFX6-NEXT: v_ashr_i64 v[4:5], v[10:11], s7
; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6 ; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6
; GFX6-NEXT: s_and_b32 s6, 1, s9
; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6 ; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5
; GFX6-NEXT: s_and_b32 s5, 1, s5 ; GFX6-NEXT: s_and_b32 s4, 1, s4
; GFX6-NEXT: v_ashrrev_i32_e32 v15, 31, v11
; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc
; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5 ; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX6-NEXT: v_cndmask_b32_e32 v6, v15, v12, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v6, v15, v12, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v7, v15, v13, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v7, v15, v13, vcc
; GFX6-NEXT: v_add_i32_e32 v4, vcc, 0, v4 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, 0, v4
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; GFX6-NEXT: v_mov_b32_e32 v12, s4
; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc ; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc
; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v7, v12, vcc ; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v7, v20, vcc
; GFX6-NEXT: v_and_b32_e32 v12, 1, v14 ; GFX6-NEXT: v_and_b32_e32 v12, 1, v14
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; GFX6-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31] ; GFX6-NEXT: s_setpc_b64 s[30:31]
; ;
Show All 33 Lines
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX8-NEXT: s_and_b32 s4, 1, s5 ; GFX8-NEXT: s_and_b32 s4, 1, s5
; GFX8-NEXT: v_ashrrev_i64 v[8:9], s6, v[18:19] ; GFX8-NEXT: v_ashrrev_i64 v[8:9], s6, v[18:19]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX8-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, s4 ; GFX8-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, s4
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX8-NEXT: v_ashrrev_i32_e32 v11, 31, v19 ; GFX8-NEXT: v_ashrrev_i32_e32 v11, 31, v19
; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v16, s[4:5] ; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v16, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v17, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v2, v11, v8, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v2, v11, v8, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v17, s[4:5]
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0, v0 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0, v0
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: s_brev_b32 s4, 1 ; GFX8-NEXT: v_bfrev_b32_e32 v20, 1
; GFX8-NEXT: v_mov_b32_e32 v8, s4
; GFX8-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc ; GFX8-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v3, v20, vcc
; GFX8-NEXT: v_and_b32_e32 v8, 1, v10 ; GFX8-NEXT: v_and_b32_e32 v8, 1, v10
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX8-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
; GFX8-NEXT: v_add_u32_e32 v8, vcc, v4, v12 ; GFX8-NEXT: v_add_u32_e32 v8, vcc, v4, v12
; GFX8-NEXT: v_addc_u32_e32 v9, vcc, v5, v13, vcc ; GFX8-NEXT: v_addc_u32_e32 v9, vcc, v5, v13, vcc
; GFX8-NEXT: v_addc_u32_e32 v10, vcc, v6, v14, vcc ; GFX8-NEXT: v_addc_u32_e32 v10, vcc, v6, v14, vcc
; GFX8-NEXT: v_addc_u32_e32 v11, vcc, v7, v15, vcc ; GFX8-NEXT: v_addc_u32_e32 v11, vcc, v7, v15, vcc
; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] ; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
; GFX8-NEXT: s_cmp_lt_u32 s6, 64 ; GFX8-NEXT: s_cmp_lt_u32 s6, 64
; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7] ; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7]
; GFX8-NEXT: s_cselect_b32 s5, 1, 0 ; GFX8-NEXT: s_cselect_b32 s4, 1, 0
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7] ; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7]
; GFX8-NEXT: s_cmp_eq_u32 s6, 0 ; GFX8-NEXT: s_cmp_eq_u32 s6, 0
; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, 0, v[12:13] ; GFX8-NEXT: v_cmp_gt_u64_e32 vcc, 0, v[12:13]
; GFX8-NEXT: s_cselect_b32 s9, 1, 0 ; GFX8-NEXT: s_cselect_b32 s5, 1, 0
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[14:15] ; GFX8-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[14:15]
; GFX8-NEXT: v_ashrrev_i64 v[12:13], s6, v[10:11] ; GFX8-NEXT: v_ashrrev_i64 v[12:13], s6, v[10:11]
; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15] ; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15]
; GFX8-NEXT: v_ashrrev_i32_e32 v15, 31, v11 ; GFX8-NEXT: s_and_b32 s5, 1, s5
; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
; GFX8-NEXT: v_xor_b32_e32 v14, v5, v4 ; GFX8-NEXT: v_xor_b32_e32 v14, v5, v4
; GFX8-NEXT: v_lshrrev_b64 v[4:5], s6, v[8:9] ; GFX8-NEXT: v_lshrrev_b64 v[4:5], s6, v[8:9]
; GFX8-NEXT: v_lshlrev_b64 v[6:7], s8, v[10:11] ; GFX8-NEXT: v_lshlrev_b64 v[6:7], s8, v[10:11]
; GFX8-NEXT: s_and_b32 s6, 1, s5 ; GFX8-NEXT: s_and_b32 s6, 1, s4
; GFX8-NEXT: v_or_b32_e32 v6, v4, v6 ; GFX8-NEXT: v_or_b32_e32 v6, v4, v6
; GFX8-NEXT: v_or_b32_e32 v7, v5, v7 ; GFX8-NEXT: v_or_b32_e32 v7, v5, v7
; GFX8-NEXT: v_ashrrev_i64 v[4:5], s7, v[10:11] ; GFX8-NEXT: v_ashrrev_i64 v[4:5], s7, v[10:11]
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6 ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6
; GFX8-NEXT: s_and_b32 s6, 1, s9
; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6 ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5
; GFX8-NEXT: s_and_b32 s5, 1, s5 ; GFX8-NEXT: s_and_b32 s4, 1, s4
; GFX8-NEXT: v_ashrrev_i32_e32 v15, 31, v11
; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5 ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX8-NEXT: v_cndmask_b32_e32 v6, v15, v12, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v6, v15, v12, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v7, v15, v13, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v7, v15, v13, vcc
; GFX8-NEXT: v_add_u32_e32 v4, vcc, 0, v4 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, 0, v4
; GFX8-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc ; GFX8-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; GFX8-NEXT: v_mov_b32_e32 v12, s4
; GFX8-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc ; GFX8-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc
; GFX8-NEXT: v_addc_u32_e32 v7, vcc, v7, v12, vcc ; GFX8-NEXT: v_addc_u32_e32 v7, vcc, v7, v20, vcc
; GFX8-NEXT: v_and_b32_e32 v12, 1, v14 ; GFX8-NEXT: v_and_b32_e32 v12, 1, v14
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; GFX8-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-NEXT: s_setpc_b64 s[30:31]
; ;
Show All 33 Lines
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 ; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX9-NEXT: s_and_b32 s4, 1, s5 ; GFX9-NEXT: s_and_b32 s4, 1, s5
; GFX9-NEXT: v_ashrrev_i64 v[8:9], s6, v[18:19] ; GFX9-NEXT: v_ashrrev_i64 v[8:9], s6, v[18:19]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, s4 ; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, s4
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX9-NEXT: v_ashrrev_i32_e32 v11, 31, v19 ; GFX9-NEXT: v_ashrrev_i32_e32 v11, 31, v19
; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v16, s[4:5] ; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v16, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v17, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v2, v11, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v11, v8, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v17, s[4:5]
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: s_brev_b32 s4, 1 ; GFX9-NEXT: v_bfrev_b32_e32 v20, 1
; GFX9-NEXT: v_mov_b32_e32 v8, s4
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v8, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v20, vcc
; GFX9-NEXT: v_and_b32_e32 v8, 1, v10 ; GFX9-NEXT: v_and_b32_e32 v8, 1, v10
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v4, v12 ; GFX9-NEXT: v_add_co_u32_e32 v8, vcc, v4, v12
; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v5, v13, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v9, vcc, v5, v13, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v6, v14, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v10, vcc, v6, v14, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v7, v15, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v11, vcc, v7, v15, vcc
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] ; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
; GFX9-NEXT: s_cmp_lt_u32 s6, 64 ; GFX9-NEXT: s_cmp_lt_u32 s6, 64
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7] ; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7]
; GFX9-NEXT: s_cselect_b32 s5, 1, 0 ; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7] ; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7]
; GFX9-NEXT: s_cmp_eq_u32 s6, 0 ; GFX9-NEXT: s_cmp_eq_u32 s6, 0
; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
; GFX9-NEXT: v_cmp_gt_u64_e32 vcc, 0, v[12:13] ; GFX9-NEXT: v_cmp_gt_u64_e32 vcc, 0, v[12:13]
; GFX9-NEXT: s_cselect_b32 s9, 1, 0 ; GFX9-NEXT: s_cselect_b32 s5, 1, 0
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[14:15] ; GFX9-NEXT: v_cmp_gt_i64_e32 vcc, 0, v[14:15]
; GFX9-NEXT: v_ashrrev_i64 v[12:13], s6, v[10:11] ; GFX9-NEXT: v_ashrrev_i64 v[12:13], s6, v[10:11]
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15] ; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15]
; GFX9-NEXT: v_ashrrev_i32_e32 v15, 31, v11 ; GFX9-NEXT: s_and_b32 s5, 1, s5
; GFX9-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
; GFX9-NEXT: v_xor_b32_e32 v14, v5, v4 ; GFX9-NEXT: v_xor_b32_e32 v14, v5, v4
; GFX9-NEXT: v_lshrrev_b64 v[4:5], s6, v[8:9] ; GFX9-NEXT: v_lshrrev_b64 v[4:5], s6, v[8:9]
; GFX9-NEXT: v_lshlrev_b64 v[6:7], s8, v[10:11] ; GFX9-NEXT: v_lshlrev_b64 v[6:7], s8, v[10:11]
; GFX9-NEXT: s_and_b32 s6, 1, s5 ; GFX9-NEXT: s_and_b32 s6, 1, s4
; GFX9-NEXT: v_or_b32_e32 v6, v4, v6 ; GFX9-NEXT: v_or_b32_e32 v6, v4, v6
; GFX9-NEXT: v_or_b32_e32 v7, v5, v7 ; GFX9-NEXT: v_or_b32_e32 v7, v5, v7
; GFX9-NEXT: v_ashrrev_i64 v[4:5], s7, v[10:11] ; GFX9-NEXT: v_ashrrev_i64 v[4:5], s7, v[10:11]
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6 ; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6
; GFX9-NEXT: s_and_b32 s6, 1, s9
; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6 ; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5
; GFX9-NEXT: s_and_b32 s5, 1, s5 ; GFX9-NEXT: s_and_b32 s4, 1, s4
; GFX9-NEXT: v_ashrrev_i32_e32 v15, 31, v11
; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5 ; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX9-NEXT: v_cndmask_b32_e32 v6, v15, v12, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v6, v15, v12, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v7, v15, v13, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v7, v15, v13, vcc
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 0, v4 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 0, v4
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX9-NEXT: v_mov_b32_e32 v12, s4
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v12, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v20, vcc
; GFX9-NEXT: v_and_b32_e32 v12, 1, v14 ; GFX9-NEXT: v_and_b32_e32 v12, 1, v14
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; GFX9-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
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; GFX10-NEXT: s_cselect_b32 s4, 1, 0 ; GFX10-NEXT: s_cselect_b32 s4, 1, 0
; GFX10-NEXT: s_and_b32 s8, 1, vcc_lo ; GFX10-NEXT: s_and_b32 s8, 1, vcc_lo
; GFX10-NEXT: s_and_b32 s4, 1, s4 ; GFX10-NEXT: s_and_b32 s4, 1, s4
; GFX10-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4
; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, s8 ; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, s8
; GFX10-NEXT: v_xor_b32_e32 v9, v10, v20 ; GFX10-NEXT: v_xor_b32_e32 v9, v10, v20
; GFX10-NEXT: s_brev_b32 s8, 1
; GFX10-NEXT: s_cmp_lt_u32 s5, 64 ; GFX10-NEXT: s_cmp_lt_u32 s5, 64
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v16, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v16, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v17, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v17, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v11, v0, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v11, v0, s4
; GFX10-NEXT: v_cndmask_b32_e64 v1, v11, v1, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v11, v1, s4
; GFX10-NEXT: v_and_b32_e32 v8, 1, v9 ; GFX10-NEXT: v_and_b32_e32 v8, 1, v9
; GFX10-NEXT: v_add_co_u32_e64 v2, vcc_lo, v2, 0 ; GFX10-NEXT: v_add_co_u32_e64 v2, vcc_lo, v2, 0
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e32 v20, vcc_lo, 0, v0, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v20, vcc_lo, 0, v0, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e32 v21, vcc_lo, s8, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v21, vcc_lo, 0x80000000, v1, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; GFX10-NEXT: v_add_co_u32_e64 v8, s4, v26, v12 ; GFX10-NEXT: v_add_co_u32_e64 v8, s4, v26, v12
; GFX10-NEXT: v_add_co_ci_u32_e64 v9, s4, v27, v13, s4 ; GFX10-NEXT: v_add_co_ci_u32_e64 v9, s4, v27, v13, s4
; GFX10-NEXT: v_add_co_ci_u32_e64 v10, s4, v24, v14, s4 ; GFX10-NEXT: v_add_co_ci_u32_e64 v10, s4, v24, v14, s4
; GFX10-NEXT: v_cndmask_b32_e32 v0, v16, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v16, v2, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e64 v11, s4, v25, v15, s4 ; GFX10-NEXT: v_add_co_ci_u32_e64 v11, s4, v25, v15, s4
; GFX10-NEXT: v_cmp_lt_u64_e64 s4, v[8:9], v[26:27] ; GFX10-NEXT: v_cmp_lt_u64_e64 s4, v[8:9], v[26:27]
; GFX10-NEXT: v_cndmask_b32_e32 v1, v17, v3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v17, v3, vcc_lo
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; GFX10-NEXT: v_and_b32_e32 v7, 1, v7 ; GFX10-NEXT: v_and_b32_e32 v7, 1, v7
; GFX10-NEXT: v_cndmask_b32_e64 v3, v18, v3, s5 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v18, v3, s5
; GFX10-NEXT: v_cndmask_b32_e64 v4, v18, v4, s5 ; GFX10-NEXT: v_cndmask_b32_e64 v4, v18, v4, s5
; GFX10-NEXT: v_add_co_u32_e64 v5, s4, v5, 0 ; GFX10-NEXT: v_add_co_u32_e64 v5, s4, v5, 0
; GFX10-NEXT: v_add_co_ci_u32_e64 v6, s4, 0, v6, s4 ; GFX10-NEXT: v_add_co_ci_u32_e64 v6, s4, 0, v6, s4
; GFX10-NEXT: v_cmp_ne_u32_e64 s5, 0, v7 ; GFX10-NEXT: v_cmp_ne_u32_e64 s5, 0, v7
; GFX10-NEXT: v_add_co_ci_u32_e64 v7, s4, 0, v3, s4 ; GFX10-NEXT: v_add_co_ci_u32_e64 v7, s4, 0, v3, s4
; GFX10-NEXT: v_cndmask_b32_e32 v3, v19, v21, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v19, v21, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e64 v12, s4, s8, v4, s4 ; GFX10-NEXT: v_add_co_ci_u32_e64 v12, s4, 0x80000000, v4, s4
; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, v5, s5 ; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, v5, s5
; GFX10-NEXT: v_cndmask_b32_e64 v5, v9, v6, s5 ; GFX10-NEXT: v_cndmask_b32_e64 v5, v9, v6, s5
; GFX10-NEXT: v_cndmask_b32_e64 v6, v10, v7, s5 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v10, v7, s5
; GFX10-NEXT: v_cndmask_b32_e64 v7, v11, v12, s5 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v11, v12, s5
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i128> @llvm.sadd.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs) %result = call <2 x i128> @llvm.sadd.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)
ret <2 x i128> %result ret <2 x i128> %result
} }
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llvm/test/CodeGen/AMDGPU/GlobalISel/sdiv.i64.ll

Show First 20 Lines • Show All 1,050 Lines • ▼ Show 20 Lines; CGP-NEXT: s_setpc_b64 s[30:31]
%result = sdiv <2 x i64> %num, %den %result = sdiv <2 x i64> %num, %den
ret <2 x i64> %result ret <2 x i64> %result
} }
define i64 @v_sdiv_i64_pow2k_denom(i64 %num) { define i64 @v_sdiv_i64_pow2k_denom(i64 %num) {
; CHECK-LABEL: v_sdiv_i64_pow2k_denom: ; CHECK-LABEL: v_sdiv_i64_pow2k_denom:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_movk_i32 s6, 0x1000 ; CHECK-NEXT: v_cvt_f32_u32_e32 v2, 0x1000
; CHECK-NEXT: v_cvt_f32_u32_e32 v2, s6
; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v4, 0 ; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v4, 0
; CHECK-NEXT: s_mov_b32 s7, 0xfffff000 ; CHECK-NEXT: s_movk_i32 s6, 0xf000
; CHECK-NEXT: v_ashrrev_i32_e32 v3, 31, v1 ; CHECK-NEXT: v_ashrrev_i32_e32 v3, 31, v1
; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v4 ; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v4
; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v3 ; CHECK-NEXT: v_xor_b32_e32 v0, v0, v3
; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 ; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
; CHECK-NEXT: v_mul_f32_e32 v4, 0x2f800000, v2 ; CHECK-NEXT: v_mul_f32_e32 v4, 0x2f800000, v2
; CHECK-NEXT: v_trunc_f32_e32 v4, v4 ; CHECK-NEXT: v_trunc_f32_e32 v4, v4
; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v4 ; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v4
; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2 ; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4 ; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4
; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3 ; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3
; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2 ; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2
; CHECK-NEXT: v_mul_lo_u32 v6, s7, v4 ; CHECK-NEXT: v_mul_lo_u32 v6, s6, v4
; CHECK-NEXT: v_mul_hi_u32 v8, s7, v2 ; CHECK-NEXT: v_mul_hi_u32 v8, s6, v2
; CHECK-NEXT: v_mul_lo_u32 v7, s7, v2 ; CHECK-NEXT: v_mul_lo_u32 v7, s6, v2
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v8 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; CHECK-NEXT: v_mul_lo_u32 v6, v4, v7 ; CHECK-NEXT: v_mul_lo_u32 v6, v4, v7
; CHECK-NEXT: v_mul_lo_u32 v8, v2, v5 ; CHECK-NEXT: v_mul_lo_u32 v8, v2, v5
; CHECK-NEXT: v_mul_hi_u32 v9, v2, v7 ; CHECK-NEXT: v_mul_hi_u32 v9, v2, v7
; CHECK-NEXT: v_mul_hi_u32 v7, v4, v7 ; CHECK-NEXT: v_mul_hi_u32 v7, v4, v7
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
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; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; CHECK-NEXT: v_addc_u32_e64 v6, s[4:5], v4, v5, vcc ; CHECK-NEXT: v_addc_u32_e64 v6, s[4:5], v4, v5, vcc
; CHECK-NEXT: v_mul_lo_u32 v7, -1, v2 ; CHECK-NEXT: v_mul_lo_u32 v7, -1, v2
; CHECK-NEXT: v_mul_lo_u32 v8, s7, v6 ; CHECK-NEXT: v_mul_lo_u32 v8, s6, v6
; CHECK-NEXT: v_mul_hi_u32 v10, s7, v2 ; CHECK-NEXT: v_mul_hi_u32 v10, s6, v2
; CHECK-NEXT: v_mul_lo_u32 v9, s7, v2 ; CHECK-NEXT: v_mul_lo_u32 v9, s6, v2
; CHECK-NEXT: v_add_i32_e64 v4, s[4:5], v4, v5 ; CHECK-NEXT: v_add_i32_e64 v4, s[4:5], v4, v5
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v8 ; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v8
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v10 ; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v10
; CHECK-NEXT: v_mul_lo_u32 v8, v6, v9 ; CHECK-NEXT: v_mul_lo_u32 v8, v6, v9
; CHECK-NEXT: v_mul_lo_u32 v10, v2, v7 ; CHECK-NEXT: v_mul_lo_u32 v10, v2, v7
; CHECK-NEXT: v_mul_hi_u32 v5, v2, v9 ; CHECK-NEXT: v_mul_hi_u32 v5, v2, v9
; CHECK-NEXT: v_mul_hi_u32 v9, v6, v9 ; CHECK-NEXT: v_mul_hi_u32 v9, v6, v9
; CHECK-NEXT: s_movk_i32 s6, 0x1000
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v10 ; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v10
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5]
; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v8, v5 ; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v8, v5
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[4:5]
; CHECK-NEXT: v_mul_lo_u32 v8, v6, v7 ; CHECK-NEXT: v_mul_lo_u32 v8, v6, v7
; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v10, v5 ; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v10, v5
; CHECK-NEXT: v_mul_hi_u32 v10, v2, v7 ; CHECK-NEXT: v_mul_hi_u32 v10, v2, v7
; CHECK-NEXT: v_mul_hi_u32 v6, v6, v7 ; CHECK-NEXT: v_mul_hi_u32 v6, v6, v7
▲ Show 20 Lines • Show All 372 Lines • ▼ Show 20 Lines
; GISEL-NEXT: v_xor_b32_e32 v3, v3, v7 ; GISEL-NEXT: v_xor_b32_e32 v3, v3, v7
; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v7 ; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v7
; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v7, vcc ; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v7, vcc
; GISEL-NEXT: s_setpc_b64 s[30:31] ; GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; CGP-LABEL: v_sdiv_v2i64_pow2k_denom: ; CGP-LABEL: v_sdiv_v2i64_pow2k_denom:
; CGP: ; %bb.0: ; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CGP-NEXT: s_movk_i32 s6, 0x1000 ; CGP-NEXT: v_cvt_f32_u32_e32 v4, 0x1000
; CGP-NEXT: v_cvt_f32_u32_e32 v4, s6
; CGP-NEXT: v_cvt_f32_ubyte0_e32 v6, 0 ; CGP-NEXT: v_cvt_f32_ubyte0_e32 v6, 0
; CGP-NEXT: s_mov_b32 s7, 0xfffff000 ; CGP-NEXT: s_movk_i32 s6, 0xf000
; CGP-NEXT: v_ashrrev_i32_e32 v5, 31, v1 ; CGP-NEXT: v_ashrrev_i32_e32 v5, 31, v1
; CGP-NEXT: v_mov_b32_e32 v7, v4 ; CGP-NEXT: v_mov_b32_e32 v7, v4
; CGP-NEXT: v_mac_f32_e32 v7, 0x4f800000, v6 ; CGP-NEXT: v_mac_f32_e32 v7, 0x4f800000, v6
; CGP-NEXT: v_rcp_iflag_f32_e32 v7, v7 ; CGP-NEXT: v_rcp_iflag_f32_e32 v7, v7
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v5 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v5
; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v5, vcc ; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v5, vcc
; CGP-NEXT: v_xor_b32_e32 v0, v0, v5 ; CGP-NEXT: v_xor_b32_e32 v0, v0, v5
; CGP-NEXT: v_mul_f32_e32 v7, 0x5f7ffffc, v7 ; CGP-NEXT: v_mul_f32_e32 v7, 0x5f7ffffc, v7
; CGP-NEXT: v_mul_f32_e32 v8, 0x2f800000, v7 ; CGP-NEXT: v_mul_f32_e32 v8, 0x2f800000, v7
; CGP-NEXT: v_trunc_f32_e32 v8, v8 ; CGP-NEXT: v_trunc_f32_e32 v8, v8
; CGP-NEXT: v_mac_f32_e32 v7, 0xcf800000, v8 ; CGP-NEXT: v_mac_f32_e32 v7, 0xcf800000, v8
; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7 ; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7
; CGP-NEXT: v_cvt_u32_f32_e32 v8, v8 ; CGP-NEXT: v_cvt_u32_f32_e32 v8, v8
; CGP-NEXT: v_xor_b32_e32 v1, v1, v5 ; CGP-NEXT: v_xor_b32_e32 v1, v1, v5
; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v6 ; CGP-NEXT: s_movk_i32 s7, 0x1000
; CGP-NEXT: v_mul_lo_u32 v9, -1, v7 ; CGP-NEXT: v_mul_lo_u32 v9, -1, v7
; CGP-NEXT: v_mul_lo_u32 v10, s7, v8 ; CGP-NEXT: v_mul_lo_u32 v10, s6, v8
; CGP-NEXT: v_mul_hi_u32 v12, s7, v7 ; CGP-NEXT: v_mul_hi_u32 v12, s6, v7
; CGP-NEXT: v_mul_lo_u32 v11, s7, v7 ; CGP-NEXT: v_mul_lo_u32 v11, s6, v7
; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4 ; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v6
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_mul_lo_u32 v10, v8, v11 ; CGP-NEXT: v_mul_lo_u32 v10, v8, v11
; CGP-NEXT: v_mul_lo_u32 v12, v7, v9 ; CGP-NEXT: v_mul_lo_u32 v12, v7, v9
; CGP-NEXT: v_mul_hi_u32 v13, v7, v11 ; CGP-NEXT: v_mul_hi_u32 v13, v7, v11
; CGP-NEXT: v_mul_hi_u32 v11, v8, v11 ; CGP-NEXT: v_mul_hi_u32 v11, v8, v11
; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v13 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v13
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_mul_lo_u32 v13, v8, v9 ; CGP-NEXT: v_mul_lo_u32 v13, v8, v9
; CGP-NEXT: v_add_i32_e32 v10, vcc, v12, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v12, v10
; CGP-NEXT: v_mul_hi_u32 v12, v7, v9 ; CGP-NEXT: v_mul_hi_u32 v12, v7, v9
; CGP-NEXT: v_mul_hi_u32 v9, v8, v9 ; CGP-NEXT: v_mul_hi_u32 v9, v8, v9
; CGP-NEXT: v_add_i32_e32 v11, vcc, v13, v11 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v13, v11
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; CGP-NEXT: v_addc_u32_e64 v10, s[4:5], v8, v9, vcc ; CGP-NEXT: v_addc_u32_e64 v10, s[4:5], v8, v9, vcc
; CGP-NEXT: v_mul_lo_u32 v11, -1, v7 ; CGP-NEXT: v_mul_lo_u32 v11, -1, v7
; CGP-NEXT: v_mul_lo_u32 v12, s7, v10 ; CGP-NEXT: v_mul_lo_u32 v12, s6, v10
; CGP-NEXT: v_mul_hi_u32 v14, s7, v7 ; CGP-NEXT: v_mul_hi_u32 v14, s6, v7
; CGP-NEXT: v_mul_lo_u32 v13, s7, v7 ; CGP-NEXT: v_mul_lo_u32 v13, s6, v7
; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9 ; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12 ; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14 ; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14
; CGP-NEXT: v_mul_lo_u32 v12, v10, v13 ; CGP-NEXT: v_mul_lo_u32 v12, v10, v13
; CGP-NEXT: v_mul_lo_u32 v14, v7, v11 ; CGP-NEXT: v_mul_lo_u32 v14, v7, v11
; CGP-NEXT: v_mul_hi_u32 v9, v7, v13 ; CGP-NEXT: v_mul_hi_u32 v9, v7, v13
; CGP-NEXT: v_mul_hi_u32 v13, v10, v13 ; CGP-NEXT: v_mul_hi_u32 v13, v10, v13
; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v3 ; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14 ; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9 ; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5]
; CGP-NEXT: v_mul_lo_u32 v12, v10, v11 ; CGP-NEXT: v_mul_lo_u32 v12, v10, v11
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v14, v9 ; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v14, v9
; CGP-NEXT: v_mul_hi_u32 v14, v7, v11 ; CGP-NEXT: v_mul_hi_u32 v14, v7, v11
; CGP-NEXT: v_mul_hi_u32 v10, v10, v11 ; CGP-NEXT: v_mul_hi_u32 v10, v10, v11
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v13 ; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v13
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14 ; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v13, v14 ; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v13, v14
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9 ; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v13, v12 ; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v13, v12
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11 ; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11
; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v10, vcc ; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v10, vcc
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v9 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; CGP-NEXT: v_addc_u32_e32 v8, vcc, 0, v8, vcc ; CGP-NEXT: v_addc_u32_e32 v8, vcc, 0, v8, vcc
; CGP-NEXT: v_mul_lo_u32 v9, v1, v7 ; CGP-NEXT: v_mul_lo_u32 v9, v1, v7
; CGP-NEXT: v_mul_lo_u32 v10, v0, v8 ; CGP-NEXT: v_mul_lo_u32 v10, v0, v8
; CGP-NEXT: v_mul_hi_u32 v11, v0, v7 ; CGP-NEXT: v_mul_hi_u32 v11, v0, v7
; CGP-NEXT: v_mul_hi_u32 v7, v1, v7 ; CGP-NEXT: v_mul_hi_u32 v7, v1, v7
; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v3
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CGP-NEXT: v_mul_lo_u32 v11, v1, v8 ; CGP-NEXT: v_mul_lo_u32 v11, v1, v8
; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CGP-NEXT: v_mul_hi_u32 v10, v0, v8 ; CGP-NEXT: v_mul_hi_u32 v10, v0, v8
; CGP-NEXT: v_mul_hi_u32 v8, v1, v8 ; CGP-NEXT: v_mul_hi_u32 v8, v1, v8
; CGP-NEXT: v_add_i32_e32 v7, vcc, v11, v7 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v11, v7
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v9 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CGP-NEXT: v_mul_lo_u32 v9, 0, v7 ; CGP-NEXT: v_mul_lo_u32 v9, 0, v7
; CGP-NEXT: v_mul_lo_u32 v10, s6, v8 ; CGP-NEXT: v_mul_lo_u32 v10, s7, v8
; CGP-NEXT: v_mul_hi_u32 v12, s6, v7 ; CGP-NEXT: v_mul_hi_u32 v12, s7, v7
; CGP-NEXT: v_mul_lo_u32 v11, s6, v7 ; CGP-NEXT: v_mul_lo_u32 v11, s7, v7
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v11 ; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v11
; CGP-NEXT: v_subb_u32_e64 v10, s[4:5], v1, v9, vcc ; CGP-NEXT: v_subb_u32_e64 v10, s[4:5], v1, v9, vcc
; CGP-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v9 ; CGP-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v9
; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v10 ; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v10
; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v0 ; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v0
; CGP-NEXT: v_subrev_i32_e32 v0, vcc, s6, v0 ; CGP-NEXT: v_subrev_i32_e32 v0, vcc, s7, v0
; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v10 ; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v10
; CGP-NEXT: v_add_i32_e32 v10, vcc, 1, v7 ; CGP-NEXT: v_add_i32_e32 v10, vcc, 1, v7
; CGP-NEXT: v_cndmask_b32_e64 v9, v9, v11, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v9, v9, v11, s[4:5]
; CGP-NEXT: v_addc_u32_e32 v11, vcc, 0, v8, vcc ; CGP-NEXT: v_addc_u32_e32 v11, vcc, 0, v8, vcc
; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v1 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v1
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s6, v0 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, s7, v0
; CGP-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; CGP-NEXT: v_cndmask_b32_e32 v0, v12, v0, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v12, v0, vcc
; CGP-NEXT: v_add_i32_e32 v1, vcc, 1, v10 ; CGP-NEXT: v_add_i32_e32 v1, vcc, 1, v10
; CGP-NEXT: v_addc_u32_e32 v12, vcc, 0, v11, vcc ; CGP-NEXT: v_addc_u32_e32 v12, vcc, 0, v11, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; CGP-NEXT: v_cndmask_b32_e32 v0, v10, v1, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v10, v1, vcc
; CGP-NEXT: v_cndmask_b32_e32 v1, v11, v12, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v11, v12, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
; CGP-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc
; CGP-NEXT: v_mul_f32_e32 v7, 0x2f800000, v4 ; CGP-NEXT: v_mul_f32_e32 v7, 0x2f800000, v4
; CGP-NEXT: v_trunc_f32_e32 v7, v7 ; CGP-NEXT: v_trunc_f32_e32 v7, v7
; CGP-NEXT: v_mac_f32_e32 v4, 0xcf800000, v7 ; CGP-NEXT: v_mac_f32_e32 v4, 0xcf800000, v7
; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4 ; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4
; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7 ; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7
; CGP-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v6 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; CGP-NEXT: v_mul_lo_u32 v8, -1, v4 ; CGP-NEXT: v_mul_lo_u32 v8, -1, v4
; CGP-NEXT: v_mul_lo_u32 v9, s7, v7 ; CGP-NEXT: v_mul_lo_u32 v9, s6, v7
; CGP-NEXT: v_mul_hi_u32 v11, s7, v4 ; CGP-NEXT: v_mul_hi_u32 v11, s6, v4
; CGP-NEXT: v_mul_lo_u32 v10, s7, v4 ; CGP-NEXT: v_mul_lo_u32 v10, s6, v4
; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v6, vcc ; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v6, vcc
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v11 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; CGP-NEXT: v_mul_lo_u32 v9, v7, v10 ; CGP-NEXT: v_mul_lo_u32 v9, v7, v10
; CGP-NEXT: v_mul_lo_u32 v11, v4, v8 ; CGP-NEXT: v_mul_lo_u32 v11, v4, v8
; CGP-NEXT: v_mul_hi_u32 v12, v4, v10 ; CGP-NEXT: v_mul_hi_u32 v12, v4, v10
; CGP-NEXT: v_mul_hi_u32 v10, v7, v10 ; CGP-NEXT: v_mul_hi_u32 v10, v7, v10
; CGP-NEXT: v_xor_b32_e32 v0, v0, v5 ; CGP-NEXT: v_xor_b32_e32 v0, v0, v5
Show All 12 Lines
; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v10 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v9 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v9
; CGP-NEXT: v_addc_u32_e64 v9, s[4:5], v7, v8, vcc ; CGP-NEXT: v_addc_u32_e64 v9, s[4:5], v7, v8, vcc
; CGP-NEXT: v_mul_lo_u32 v10, -1, v4 ; CGP-NEXT: v_mul_lo_u32 v10, -1, v4
; CGP-NEXT: v_mul_lo_u32 v11, s7, v9 ; CGP-NEXT: v_mul_lo_u32 v11, s6, v9
; CGP-NEXT: v_mul_hi_u32 v13, s7, v4 ; CGP-NEXT: v_mul_hi_u32 v13, s6, v4
; CGP-NEXT: v_mul_lo_u32 v12, s7, v4 ; CGP-NEXT: v_mul_lo_u32 v12, s6, v4
; CGP-NEXT: v_add_i32_e64 v7, s[4:5], v7, v8 ; CGP-NEXT: v_add_i32_e64 v7, s[4:5], v7, v8
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11 ; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v13 ; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v13
; CGP-NEXT: v_mul_lo_u32 v11, v9, v12 ; CGP-NEXT: v_mul_lo_u32 v11, v9, v12
; CGP-NEXT: v_mul_lo_u32 v13, v4, v10 ; CGP-NEXT: v_mul_lo_u32 v13, v4, v10
; CGP-NEXT: v_mul_hi_u32 v8, v4, v12 ; CGP-NEXT: v_mul_hi_u32 v8, v4, v12
; CGP-NEXT: v_mul_hi_u32 v12, v9, v12 ; CGP-NEXT: v_mul_hi_u32 v12, v9, v12
; CGP-NEXT: v_xor_b32_e32 v2, v2, v6 ; CGP-NEXT: v_xor_b32_e32 v2, v2, v6
Show All 38 Lines
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v9 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v9
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v5 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v5
; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v5, vcc, v8, v5 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v8, v5
; CGP-NEXT: v_add_i32_e32 v5, vcc, v7, v5 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v7, v5
; CGP-NEXT: v_mul_lo_u32 v7, 0, v4 ; CGP-NEXT: v_mul_lo_u32 v7, 0, v4
; CGP-NEXT: v_mul_lo_u32 v8, s6, v5 ; CGP-NEXT: v_mul_lo_u32 v8, s7, v5
; CGP-NEXT: v_mul_hi_u32 v10, s6, v4 ; CGP-NEXT: v_mul_hi_u32 v10, s7, v4
; CGP-NEXT: v_mul_lo_u32 v9, s6, v4 ; CGP-NEXT: v_mul_lo_u32 v9, s7, v4
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v9 ; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v9
; CGP-NEXT: v_subb_u32_e64 v8, s[4:5], v3, v7, vcc ; CGP-NEXT: v_subb_u32_e64 v8, s[4:5], v3, v7, vcc
; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v7 ; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v7
; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v8 ; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v8
; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc ; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v2 ; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v2
; CGP-NEXT: v_subrev_i32_e32 v2, vcc, s6, v2 ; CGP-NEXT: v_subrev_i32_e32 v2, vcc, s7, v2
; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc ; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v8 ; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v8
; CGP-NEXT: v_add_i32_e32 v8, vcc, 1, v4 ; CGP-NEXT: v_add_i32_e32 v8, vcc, 1, v4
; CGP-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[4:5]
; CGP-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc ; CGP-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v3 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v3
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s6, v2 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, s7, v2
; CGP-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc
; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 ; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; CGP-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
; CGP-NEXT: v_add_i32_e32 v3, vcc, 1, v8 ; CGP-NEXT: v_add_i32_e32 v3, vcc, 1, v8
; CGP-NEXT: v_addc_u32_e32 v10, vcc, 0, v9, vcc ; CGP-NEXT: v_addc_u32_e32 v10, vcc, 0, v9, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; CGP-NEXT: v_cndmask_b32_e32 v2, v8, v3, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v8, v3, vcc
; CGP-NEXT: v_cndmask_b32_e32 v3, v9, v10, vcc ; CGP-NEXT: v_cndmask_b32_e32 v3, v9, v10, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; CGP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; CGP-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc ; CGP-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; CGP-NEXT: v_xor_b32_e32 v2, v2, v6 ; CGP-NEXT: v_xor_b32_e32 v2, v2, v6
; CGP-NEXT: v_xor_b32_e32 v3, v3, v6 ; CGP-NEXT: v_xor_b32_e32 v3, v3, v6
; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v6 ; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v6
; CGP-NEXT: v_subb_u32_e32 v3, vcc, v3, v6, vcc ; CGP-NEXT: v_subb_u32_e32 v3, vcc, v3, v6, vcc
; CGP-NEXT: s_setpc_b64 s[30:31] ; CGP-NEXT: s_setpc_b64 s[30:31]
%result = sdiv <2 x i64> %num, <i64 4096, i64 4096> %result = sdiv <2 x i64> %num, <i64 4096, i64 4096>
ret <2 x i64> %result ret <2 x i64> %result
} }
define i64 @v_sdiv_i64_oddk_denom(i64 %num) { define i64 @v_sdiv_i64_oddk_denom(i64 %num) {
; CHECK-LABEL: v_sdiv_i64_oddk_denom: ; CHECK-LABEL: v_sdiv_i64_oddk_denom:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_mov_b32 s6, 0x12d8fb ; CHECK-NEXT: v_cvt_f32_u32_e32 v2, 0x12d8fb
; CHECK-NEXT: v_cvt_f32_u32_e32 v2, s6
; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v4, 0 ; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v4, 0
; CHECK-NEXT: s_mov_b32 s7, 0xffed2705 ; CHECK-NEXT: s_mov_b32 s6, 0xffed2705
; CHECK-NEXT: v_ashrrev_i32_e32 v3, 31, v1 ; CHECK-NEXT: v_ashrrev_i32_e32 v3, 31, v1
; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v4 ; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v4
; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v3 ; CHECK-NEXT: v_xor_b32_e32 v0, v0, v3
; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 ; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
; CHECK-NEXT: v_mul_f32_e32 v4, 0x2f800000, v2 ; CHECK-NEXT: v_mul_f32_e32 v4, 0x2f800000, v2
; CHECK-NEXT: v_trunc_f32_e32 v4, v4 ; CHECK-NEXT: v_trunc_f32_e32 v4, v4
; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v4 ; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v4
; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2 ; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4 ; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4
; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3 ; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3
; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2 ; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2
; CHECK-NEXT: v_mul_lo_u32 v6, s7, v4 ; CHECK-NEXT: v_mul_lo_u32 v6, s6, v4
; CHECK-NEXT: v_mul_hi_u32 v8, s7, v2 ; CHECK-NEXT: v_mul_hi_u32 v8, s6, v2
; CHECK-NEXT: v_mul_lo_u32 v7, s7, v2 ; CHECK-NEXT: v_mul_lo_u32 v7, s6, v2
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v8 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; CHECK-NEXT: v_mul_lo_u32 v6, v4, v7 ; CHECK-NEXT: v_mul_lo_u32 v6, v4, v7
; CHECK-NEXT: v_mul_lo_u32 v8, v2, v5 ; CHECK-NEXT: v_mul_lo_u32 v8, v2, v5
; CHECK-NEXT: v_mul_hi_u32 v9, v2, v7 ; CHECK-NEXT: v_mul_hi_u32 v9, v2, v7
; CHECK-NEXT: v_mul_hi_u32 v7, v4, v7 ; CHECK-NEXT: v_mul_hi_u32 v7, v4, v7
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
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; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; CHECK-NEXT: v_addc_u32_e64 v6, s[4:5], v4, v5, vcc ; CHECK-NEXT: v_addc_u32_e64 v6, s[4:5], v4, v5, vcc
; CHECK-NEXT: v_mul_lo_u32 v7, -1, v2 ; CHECK-NEXT: v_mul_lo_u32 v7, -1, v2
; CHECK-NEXT: v_mul_lo_u32 v8, s7, v6 ; CHECK-NEXT: v_mul_lo_u32 v8, s6, v6
; CHECK-NEXT: v_mul_hi_u32 v10, s7, v2 ; CHECK-NEXT: v_mul_hi_u32 v10, s6, v2
; CHECK-NEXT: v_mul_lo_u32 v9, s7, v2 ; CHECK-NEXT: v_mul_lo_u32 v9, s6, v2
; CHECK-NEXT: v_add_i32_e64 v4, s[4:5], v4, v5 ; CHECK-NEXT: v_add_i32_e64 v4, s[4:5], v4, v5
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v8 ; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v8
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v10 ; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v10
; CHECK-NEXT: v_mul_lo_u32 v8, v6, v9 ; CHECK-NEXT: v_mul_lo_u32 v8, v6, v9
; CHECK-NEXT: v_mul_lo_u32 v10, v2, v7 ; CHECK-NEXT: v_mul_lo_u32 v10, v2, v7
; CHECK-NEXT: v_mul_hi_u32 v5, v2, v9 ; CHECK-NEXT: v_mul_hi_u32 v5, v2, v9
; CHECK-NEXT: v_mul_hi_u32 v9, v6, v9 ; CHECK-NEXT: v_mul_hi_u32 v9, v6, v9
; CHECK-NEXT: s_mov_b32 s6, 0x12d8fb
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v10 ; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v10
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5]
; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v8, v5 ; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v8, v5
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[4:5]
; CHECK-NEXT: v_mul_lo_u32 v8, v6, v7 ; CHECK-NEXT: v_mul_lo_u32 v8, v6, v7
; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v10, v5 ; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v10, v5
; CHECK-NEXT: v_mul_hi_u32 v10, v2, v7 ; CHECK-NEXT: v_mul_hi_u32 v10, v2, v7
; CHECK-NEXT: v_mul_hi_u32 v6, v6, v7 ; CHECK-NEXT: v_mul_hi_u32 v6, v6, v7
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; GISEL-NEXT: v_xor_b32_e32 v3, v3, v7 ; GISEL-NEXT: v_xor_b32_e32 v3, v3, v7
; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v7 ; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v7
; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v7, vcc ; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v7, vcc
; GISEL-NEXT: s_setpc_b64 s[30:31] ; GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; CGP-LABEL: v_sdiv_v2i64_oddk_denom: ; CGP-LABEL: v_sdiv_v2i64_oddk_denom:
; CGP: ; %bb.0: ; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CGP-NEXT: s_mov_b32 s6, 0x12d8fb ; CGP-NEXT: v_cvt_f32_u32_e32 v4, 0x12d8fb
; CGP-NEXT: v_cvt_f32_u32_e32 v4, s6
; CGP-NEXT: v_cvt_f32_ubyte0_e32 v6, 0 ; CGP-NEXT: v_cvt_f32_ubyte0_e32 v6, 0
; CGP-NEXT: s_mov_b32 s7, 0xffed2705 ; CGP-NEXT: s_mov_b32 s6, 0xffed2705
; CGP-NEXT: v_ashrrev_i32_e32 v5, 31, v1 ; CGP-NEXT: v_ashrrev_i32_e32 v5, 31, v1
; CGP-NEXT: v_mov_b32_e32 v7, v4 ; CGP-NEXT: v_mov_b32_e32 v7, v4
; CGP-NEXT: v_mac_f32_e32 v7, 0x4f800000, v6 ; CGP-NEXT: v_mac_f32_e32 v7, 0x4f800000, v6
; CGP-NEXT: v_rcp_iflag_f32_e32 v7, v7 ; CGP-NEXT: v_rcp_iflag_f32_e32 v7, v7
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v5 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v5
; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v5, vcc ; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v5, vcc
; CGP-NEXT: v_xor_b32_e32 v0, v0, v5 ; CGP-NEXT: v_xor_b32_e32 v0, v0, v5
; CGP-NEXT: v_mul_f32_e32 v7, 0x5f7ffffc, v7 ; CGP-NEXT: v_mul_f32_e32 v7, 0x5f7ffffc, v7
; CGP-NEXT: v_mul_f32_e32 v8, 0x2f800000, v7 ; CGP-NEXT: v_mul_f32_e32 v8, 0x2f800000, v7
; CGP-NEXT: v_trunc_f32_e32 v8, v8 ; CGP-NEXT: v_trunc_f32_e32 v8, v8
; CGP-NEXT: v_mac_f32_e32 v7, 0xcf800000, v8 ; CGP-NEXT: v_mac_f32_e32 v7, 0xcf800000, v8
; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7 ; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7
; CGP-NEXT: v_cvt_u32_f32_e32 v8, v8 ; CGP-NEXT: v_cvt_u32_f32_e32 v8, v8
; CGP-NEXT: v_xor_b32_e32 v1, v1, v5 ; CGP-NEXT: v_xor_b32_e32 v1, v1, v5
; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v6 ; CGP-NEXT: s_mov_b32 s7, 0x12d8fb
; CGP-NEXT: v_mul_lo_u32 v9, -1, v7 ; CGP-NEXT: v_mul_lo_u32 v9, -1, v7
; CGP-NEXT: v_mul_lo_u32 v10, s7, v8 ; CGP-NEXT: v_mul_lo_u32 v10, s6, v8
; CGP-NEXT: v_mul_hi_u32 v12, s7, v7 ; CGP-NEXT: v_mul_hi_u32 v12, s6, v7
; CGP-NEXT: v_mul_lo_u32 v11, s7, v7 ; CGP-NEXT: v_mul_lo_u32 v11, s6, v7
; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4 ; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v6
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_mul_lo_u32 v10, v8, v11 ; CGP-NEXT: v_mul_lo_u32 v10, v8, v11
; CGP-NEXT: v_mul_lo_u32 v12, v7, v9 ; CGP-NEXT: v_mul_lo_u32 v12, v7, v9
; CGP-NEXT: v_mul_hi_u32 v13, v7, v11 ; CGP-NEXT: v_mul_hi_u32 v13, v7, v11
; CGP-NEXT: v_mul_hi_u32 v11, v8, v11 ; CGP-NEXT: v_mul_hi_u32 v11, v8, v11
; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v13 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v13
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_mul_lo_u32 v13, v8, v9 ; CGP-NEXT: v_mul_lo_u32 v13, v8, v9
; CGP-NEXT: v_add_i32_e32 v10, vcc, v12, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v12, v10
; CGP-NEXT: v_mul_hi_u32 v12, v7, v9 ; CGP-NEXT: v_mul_hi_u32 v12, v7, v9
; CGP-NEXT: v_mul_hi_u32 v9, v8, v9 ; CGP-NEXT: v_mul_hi_u32 v9, v8, v9
; CGP-NEXT: v_add_i32_e32 v11, vcc, v13, v11 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v13, v11
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; CGP-NEXT: v_addc_u32_e64 v10, s[4:5], v8, v9, vcc ; CGP-NEXT: v_addc_u32_e64 v10, s[4:5], v8, v9, vcc
; CGP-NEXT: v_mul_lo_u32 v11, -1, v7 ; CGP-NEXT: v_mul_lo_u32 v11, -1, v7
; CGP-NEXT: v_mul_lo_u32 v12, s7, v10 ; CGP-NEXT: v_mul_lo_u32 v12, s6, v10
; CGP-NEXT: v_mul_hi_u32 v14, s7, v7 ; CGP-NEXT: v_mul_hi_u32 v14, s6, v7
; CGP-NEXT: v_mul_lo_u32 v13, s7, v7 ; CGP-NEXT: v_mul_lo_u32 v13, s6, v7
; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9 ; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12 ; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14 ; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14
; CGP-NEXT: v_mul_lo_u32 v12, v10, v13 ; CGP-NEXT: v_mul_lo_u32 v12, v10, v13
; CGP-NEXT: v_mul_lo_u32 v14, v7, v11 ; CGP-NEXT: v_mul_lo_u32 v14, v7, v11
; CGP-NEXT: v_mul_hi_u32 v9, v7, v13 ; CGP-NEXT: v_mul_hi_u32 v9, v7, v13
; CGP-NEXT: v_mul_hi_u32 v13, v10, v13 ; CGP-NEXT: v_mul_hi_u32 v13, v10, v13
; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v3 ; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14 ; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9 ; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5]
; CGP-NEXT: v_mul_lo_u32 v12, v10, v11 ; CGP-NEXT: v_mul_lo_u32 v12, v10, v11
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v14, v9 ; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v14, v9
; CGP-NEXT: v_mul_hi_u32 v14, v7, v11 ; CGP-NEXT: v_mul_hi_u32 v14, v7, v11
; CGP-NEXT: v_mul_hi_u32 v10, v10, v11 ; CGP-NEXT: v_mul_hi_u32 v10, v10, v11
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v13 ; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v13
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14 ; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v13, v14 ; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v13, v14
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9 ; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v13, v12 ; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v13, v12
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11 ; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11
; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v10, vcc ; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v10, vcc
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v9 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; CGP-NEXT: v_addc_u32_e32 v8, vcc, 0, v8, vcc ; CGP-NEXT: v_addc_u32_e32 v8, vcc, 0, v8, vcc
; CGP-NEXT: v_mul_lo_u32 v9, v1, v7 ; CGP-NEXT: v_mul_lo_u32 v9, v1, v7
; CGP-NEXT: v_mul_lo_u32 v10, v0, v8 ; CGP-NEXT: v_mul_lo_u32 v10, v0, v8
; CGP-NEXT: v_mul_hi_u32 v11, v0, v7 ; CGP-NEXT: v_mul_hi_u32 v11, v0, v7
; CGP-NEXT: v_mul_hi_u32 v7, v1, v7 ; CGP-NEXT: v_mul_hi_u32 v7, v1, v7
; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v3
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CGP-NEXT: v_mul_lo_u32 v11, v1, v8 ; CGP-NEXT: v_mul_lo_u32 v11, v1, v8
; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CGP-NEXT: v_mul_hi_u32 v10, v0, v8 ; CGP-NEXT: v_mul_hi_u32 v10, v0, v8
; CGP-NEXT: v_mul_hi_u32 v8, v1, v8 ; CGP-NEXT: v_mul_hi_u32 v8, v1, v8
; CGP-NEXT: v_add_i32_e32 v7, vcc, v11, v7 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v11, v7
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v9 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CGP-NEXT: v_mul_lo_u32 v9, 0, v7 ; CGP-NEXT: v_mul_lo_u32 v9, 0, v7
; CGP-NEXT: v_mul_lo_u32 v10, s6, v8 ; CGP-NEXT: v_mul_lo_u32 v10, s7, v8
; CGP-NEXT: v_mul_hi_u32 v12, s6, v7 ; CGP-NEXT: v_mul_hi_u32 v12, s7, v7
; CGP-NEXT: v_mul_lo_u32 v11, s6, v7 ; CGP-NEXT: v_mul_lo_u32 v11, s7, v7
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v11 ; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v11
; CGP-NEXT: v_subb_u32_e64 v10, s[4:5], v1, v9, vcc ; CGP-NEXT: v_subb_u32_e64 v10, s[4:5], v1, v9, vcc
; CGP-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v9 ; CGP-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v9
; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v10 ; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v10
; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v0 ; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v0
; CGP-NEXT: v_subrev_i32_e32 v0, vcc, s6, v0 ; CGP-NEXT: v_subrev_i32_e32 v0, vcc, s7, v0
; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v10 ; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v10
; CGP-NEXT: v_add_i32_e32 v10, vcc, 1, v7 ; CGP-NEXT: v_add_i32_e32 v10, vcc, 1, v7
; CGP-NEXT: v_cndmask_b32_e64 v9, v9, v11, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v9, v9, v11, s[4:5]
; CGP-NEXT: v_addc_u32_e32 v11, vcc, 0, v8, vcc ; CGP-NEXT: v_addc_u32_e32 v11, vcc, 0, v8, vcc
; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v1 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v1
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, -1, vcc
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s6, v0 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, s7, v0
; CGP-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; CGP-NEXT: v_cndmask_b32_e32 v0, v12, v0, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v12, v0, vcc
; CGP-NEXT: v_add_i32_e32 v1, vcc, 1, v10 ; CGP-NEXT: v_add_i32_e32 v1, vcc, 1, v10
; CGP-NEXT: v_addc_u32_e32 v12, vcc, 0, v11, vcc ; CGP-NEXT: v_addc_u32_e32 v12, vcc, 0, v11, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; CGP-NEXT: v_cndmask_b32_e32 v0, v10, v1, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v10, v1, vcc
; CGP-NEXT: v_cndmask_b32_e32 v1, v11, v12, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v11, v12, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v9
; CGP-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v7, v0, vcc
; CGP-NEXT: v_mul_f32_e32 v7, 0x2f800000, v4 ; CGP-NEXT: v_mul_f32_e32 v7, 0x2f800000, v4
; CGP-NEXT: v_trunc_f32_e32 v7, v7 ; CGP-NEXT: v_trunc_f32_e32 v7, v7
; CGP-NEXT: v_mac_f32_e32 v4, 0xcf800000, v7 ; CGP-NEXT: v_mac_f32_e32 v4, 0xcf800000, v7
; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4 ; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4
; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7 ; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7
; CGP-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v6 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; CGP-NEXT: v_mul_lo_u32 v8, -1, v4 ; CGP-NEXT: v_mul_lo_u32 v8, -1, v4
; CGP-NEXT: v_mul_lo_u32 v9, s7, v7 ; CGP-NEXT: v_mul_lo_u32 v9, s6, v7
; CGP-NEXT: v_mul_hi_u32 v11, s7, v4 ; CGP-NEXT: v_mul_hi_u32 v11, s6, v4
; CGP-NEXT: v_mul_lo_u32 v10, s7, v4 ; CGP-NEXT: v_mul_lo_u32 v10, s6, v4
; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v6, vcc ; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v6, vcc
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v11 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; CGP-NEXT: v_mul_lo_u32 v9, v7, v10 ; CGP-NEXT: v_mul_lo_u32 v9, v7, v10
; CGP-NEXT: v_mul_lo_u32 v11, v4, v8 ; CGP-NEXT: v_mul_lo_u32 v11, v4, v8
; CGP-NEXT: v_mul_hi_u32 v12, v4, v10 ; CGP-NEXT: v_mul_hi_u32 v12, v4, v10
; CGP-NEXT: v_mul_hi_u32 v10, v7, v10 ; CGP-NEXT: v_mul_hi_u32 v10, v7, v10
; CGP-NEXT: v_xor_b32_e32 v0, v0, v5 ; CGP-NEXT: v_xor_b32_e32 v0, v0, v5
Show All 12 Lines
; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v10 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v9 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v9
; CGP-NEXT: v_addc_u32_e64 v9, s[4:5], v7, v8, vcc ; CGP-NEXT: v_addc_u32_e64 v9, s[4:5], v7, v8, vcc
; CGP-NEXT: v_mul_lo_u32 v10, -1, v4 ; CGP-NEXT: v_mul_lo_u32 v10, -1, v4
; CGP-NEXT: v_mul_lo_u32 v11, s7, v9 ; CGP-NEXT: v_mul_lo_u32 v11, s6, v9
; CGP-NEXT: v_mul_hi_u32 v13, s7, v4 ; CGP-NEXT: v_mul_hi_u32 v13, s6, v4
; CGP-NEXT: v_mul_lo_u32 v12, s7, v4 ; CGP-NEXT: v_mul_lo_u32 v12, s6, v4
; CGP-NEXT: v_add_i32_e64 v7, s[4:5], v7, v8 ; CGP-NEXT: v_add_i32_e64 v7, s[4:5], v7, v8
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11 ; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v13 ; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v13
; CGP-NEXT: v_mul_lo_u32 v11, v9, v12 ; CGP-NEXT: v_mul_lo_u32 v11, v9, v12
; CGP-NEXT: v_mul_lo_u32 v13, v4, v10 ; CGP-NEXT: v_mul_lo_u32 v13, v4, v10
; CGP-NEXT: v_mul_hi_u32 v8, v4, v12 ; CGP-NEXT: v_mul_hi_u32 v8, v4, v12
; CGP-NEXT: v_mul_hi_u32 v12, v9, v12 ; CGP-NEXT: v_mul_hi_u32 v12, v9, v12
; CGP-NEXT: v_xor_b32_e32 v2, v2, v6 ; CGP-NEXT: v_xor_b32_e32 v2, v2, v6
Show All 38 Lines
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v9 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v9
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v5 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v5
; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v5, vcc, v8, v5 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v8, v5
; CGP-NEXT: v_add_i32_e32 v5, vcc, v7, v5 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v7, v5
; CGP-NEXT: v_mul_lo_u32 v7, 0, v4 ; CGP-NEXT: v_mul_lo_u32 v7, 0, v4
; CGP-NEXT: v_mul_lo_u32 v8, s6, v5 ; CGP-NEXT: v_mul_lo_u32 v8, s7, v5
; CGP-NEXT: v_mul_hi_u32 v10, s6, v4 ; CGP-NEXT: v_mul_hi_u32 v10, s7, v4
; CGP-NEXT: v_mul_lo_u32 v9, s6, v4 ; CGP-NEXT: v_mul_lo_u32 v9, s7, v4
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v8 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v8
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v9 ; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v9
; CGP-NEXT: v_subb_u32_e64 v8, s[4:5], v3, v7, vcc ; CGP-NEXT: v_subb_u32_e64 v8, s[4:5], v3, v7, vcc
; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v7 ; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v7
; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v8 ; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v8
; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc ; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v2 ; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v2
; CGP-NEXT: v_subrev_i32_e32 v2, vcc, s6, v2 ; CGP-NEXT: v_subrev_i32_e32 v2, vcc, s7, v2
; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc ; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v8 ; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v8
; CGP-NEXT: v_add_i32_e32 v8, vcc, 1, v4 ; CGP-NEXT: v_add_i32_e32 v8, vcc, 1, v4
; CGP-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[4:5]
; CGP-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc ; CGP-NEXT: v_addc_u32_e32 v9, vcc, 0, v5, vcc
; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v3 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v3
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s6, v2 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, s7, v2
; CGP-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v2, 0, -1, vcc
; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 ; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; CGP-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v10, v2, vcc
; CGP-NEXT: v_add_i32_e32 v3, vcc, 1, v8 ; CGP-NEXT: v_add_i32_e32 v3, vcc, 1, v8
; CGP-NEXT: v_addc_u32_e32 v10, vcc, 0, v9, vcc ; CGP-NEXT: v_addc_u32_e32 v10, vcc, 0, v9, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; CGP-NEXT: v_cndmask_b32_e32 v2, v8, v3, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v8, v3, vcc
; CGP-NEXT: v_cndmask_b32_e32 v3, v9, v10, vcc ; CGP-NEXT: v_cndmask_b32_e32 v3, v9, v10, vcc
▲ Show 20 Lines • Show All 1,247 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/srem.i64.ll

Show First 20 Lines • Show All 1,030 Lines • ▼ Show 20 Lines; CGP-NEXT: s_setpc_b64 s[30:31]
%result = srem <2 x i64> %num, %den %result = srem <2 x i64> %num, %den
ret <2 x i64> %result ret <2 x i64> %result
} }
define i64 @v_srem_i64_pow2k_denom(i64 %num) { define i64 @v_srem_i64_pow2k_denom(i64 %num) {
; CHECK-LABEL: v_srem_i64_pow2k_denom: ; CHECK-LABEL: v_srem_i64_pow2k_denom:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_movk_i32 s6, 0x1000 ; CHECK-NEXT: v_cvt_f32_u32_e32 v2, 0x1000
; CHECK-NEXT: v_cvt_f32_u32_e32 v2, s6
; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v4, 0 ; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v4, 0
; CHECK-NEXT: s_mov_b32 s7, 0xfffff000 ; CHECK-NEXT: s_movk_i32 s6, 0xf000
; CHECK-NEXT: v_ashrrev_i32_e32 v3, 31, v1 ; CHECK-NEXT: v_ashrrev_i32_e32 v3, 31, v1
; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v4 ; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v4
; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v3 ; CHECK-NEXT: v_xor_b32_e32 v0, v0, v3
; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 ; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
; CHECK-NEXT: v_mul_f32_e32 v4, 0x2f800000, v2 ; CHECK-NEXT: v_mul_f32_e32 v4, 0x2f800000, v2
; CHECK-NEXT: v_trunc_f32_e32 v4, v4 ; CHECK-NEXT: v_trunc_f32_e32 v4, v4
; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v4 ; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v4
; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2 ; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4 ; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4
; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3 ; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3
; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2 ; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2
; CHECK-NEXT: v_mul_lo_u32 v6, s7, v4 ; CHECK-NEXT: v_mul_lo_u32 v6, s6, v4
; CHECK-NEXT: v_mul_hi_u32 v8, s7, v2 ; CHECK-NEXT: v_mul_hi_u32 v8, s6, v2
; CHECK-NEXT: v_mul_lo_u32 v7, s7, v2 ; CHECK-NEXT: v_mul_lo_u32 v7, s6, v2
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v8 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; CHECK-NEXT: v_mul_lo_u32 v6, v4, v7 ; CHECK-NEXT: v_mul_lo_u32 v6, v4, v7
; CHECK-NEXT: v_mul_lo_u32 v8, v2, v5 ; CHECK-NEXT: v_mul_lo_u32 v8, v2, v5
; CHECK-NEXT: v_mul_hi_u32 v9, v2, v7 ; CHECK-NEXT: v_mul_hi_u32 v9, v2, v7
; CHECK-NEXT: v_mul_hi_u32 v7, v4, v7 ; CHECK-NEXT: v_mul_hi_u32 v7, v4, v7
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
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; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; CHECK-NEXT: v_addc_u32_e64 v6, s[4:5], v4, v5, vcc ; CHECK-NEXT: v_addc_u32_e64 v6, s[4:5], v4, v5, vcc
; CHECK-NEXT: v_mul_lo_u32 v7, -1, v2 ; CHECK-NEXT: v_mul_lo_u32 v7, -1, v2
; CHECK-NEXT: v_mul_lo_u32 v8, s7, v6 ; CHECK-NEXT: v_mul_lo_u32 v8, s6, v6
; CHECK-NEXT: v_mul_hi_u32 v10, s7, v2 ; CHECK-NEXT: v_mul_hi_u32 v10, s6, v2
; CHECK-NEXT: v_mul_lo_u32 v9, s7, v2 ; CHECK-NEXT: v_mul_lo_u32 v9, s6, v2
; CHECK-NEXT: v_add_i32_e64 v4, s[4:5], v4, v5 ; CHECK-NEXT: v_add_i32_e64 v4, s[4:5], v4, v5
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v8 ; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v8
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v10 ; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v10
; CHECK-NEXT: v_mul_lo_u32 v8, v6, v9 ; CHECK-NEXT: v_mul_lo_u32 v8, v6, v9
; CHECK-NEXT: v_mul_lo_u32 v10, v2, v7 ; CHECK-NEXT: v_mul_lo_u32 v10, v2, v7
; CHECK-NEXT: v_mul_hi_u32 v5, v2, v9 ; CHECK-NEXT: v_mul_hi_u32 v5, v2, v9
; CHECK-NEXT: v_mul_hi_u32 v9, v6, v9 ; CHECK-NEXT: v_mul_hi_u32 v9, v6, v9
; CHECK-NEXT: s_movk_i32 s6, 0x1000
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v10 ; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v10
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5]
; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v8, v5 ; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v8, v5
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[4:5]
; CHECK-NEXT: v_mul_lo_u32 v8, v6, v7 ; CHECK-NEXT: v_mul_lo_u32 v8, v6, v7
; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v10, v5 ; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v10, v5
; CHECK-NEXT: v_mul_hi_u32 v10, v2, v7 ; CHECK-NEXT: v_mul_hi_u32 v10, v2, v7
; CHECK-NEXT: v_mul_hi_u32 v6, v6, v7 ; CHECK-NEXT: v_mul_hi_u32 v6, v6, v7
▲ Show 20 Lines • Show All 368 Lines • ▼ Show 20 Lines
; GISEL-NEXT: v_xor_b32_e32 v3, v3, v7 ; GISEL-NEXT: v_xor_b32_e32 v3, v3, v7
; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v7 ; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v7
; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v7, vcc ; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v7, vcc
; GISEL-NEXT: s_setpc_b64 s[30:31] ; GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; CGP-LABEL: v_srem_v2i64_pow2k_denom: ; CGP-LABEL: v_srem_v2i64_pow2k_denom:
; CGP: ; %bb.0: ; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CGP-NEXT: s_movk_i32 s6, 0x1000 ; CGP-NEXT: v_cvt_f32_u32_e32 v4, 0x1000
; CGP-NEXT: v_cvt_f32_u32_e32 v4, s6
; CGP-NEXT: v_cvt_f32_ubyte0_e32 v6, 0 ; CGP-NEXT: v_cvt_f32_ubyte0_e32 v6, 0
; CGP-NEXT: s_mov_b32 s7, 0xfffff000 ; CGP-NEXT: s_movk_i32 s6, 0xf000
; CGP-NEXT: v_ashrrev_i32_e32 v5, 31, v1 ; CGP-NEXT: v_ashrrev_i32_e32 v5, 31, v1
; CGP-NEXT: v_mov_b32_e32 v7, v4 ; CGP-NEXT: v_mov_b32_e32 v7, v4
; CGP-NEXT: v_mac_f32_e32 v7, 0x4f800000, v6 ; CGP-NEXT: v_mac_f32_e32 v7, 0x4f800000, v6
; CGP-NEXT: v_rcp_iflag_f32_e32 v7, v7 ; CGP-NEXT: v_rcp_iflag_f32_e32 v7, v7
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v5 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v5
; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v5, vcc ; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v5, vcc
; CGP-NEXT: v_xor_b32_e32 v0, v0, v5 ; CGP-NEXT: v_xor_b32_e32 v0, v0, v5
; CGP-NEXT: v_mul_f32_e32 v7, 0x5f7ffffc, v7 ; CGP-NEXT: v_mul_f32_e32 v7, 0x5f7ffffc, v7
; CGP-NEXT: v_mul_f32_e32 v8, 0x2f800000, v7 ; CGP-NEXT: v_mul_f32_e32 v8, 0x2f800000, v7
; CGP-NEXT: v_trunc_f32_e32 v8, v8 ; CGP-NEXT: v_trunc_f32_e32 v8, v8
; CGP-NEXT: v_mac_f32_e32 v7, 0xcf800000, v8 ; CGP-NEXT: v_mac_f32_e32 v7, 0xcf800000, v8
; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7 ; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7
; CGP-NEXT: v_cvt_u32_f32_e32 v8, v8 ; CGP-NEXT: v_cvt_u32_f32_e32 v8, v8
; CGP-NEXT: v_xor_b32_e32 v1, v1, v5 ; CGP-NEXT: v_xor_b32_e32 v1, v1, v5
; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v6 ; CGP-NEXT: s_movk_i32 s7, 0x1000
; CGP-NEXT: v_mul_lo_u32 v9, -1, v7 ; CGP-NEXT: v_mul_lo_u32 v9, -1, v7
; CGP-NEXT: v_mul_lo_u32 v10, s7, v8 ; CGP-NEXT: v_mul_lo_u32 v10, s6, v8
; CGP-NEXT: v_mul_hi_u32 v12, s7, v7 ; CGP-NEXT: v_mul_hi_u32 v12, s6, v7
; CGP-NEXT: v_mul_lo_u32 v11, s7, v7 ; CGP-NEXT: v_mul_lo_u32 v11, s6, v7
; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4 ; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v6
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_mul_lo_u32 v10, v8, v11 ; CGP-NEXT: v_mul_lo_u32 v10, v8, v11
; CGP-NEXT: v_mul_lo_u32 v12, v7, v9 ; CGP-NEXT: v_mul_lo_u32 v12, v7, v9
; CGP-NEXT: v_mul_hi_u32 v13, v7, v11 ; CGP-NEXT: v_mul_hi_u32 v13, v7, v11
; CGP-NEXT: v_mul_hi_u32 v11, v8, v11 ; CGP-NEXT: v_mul_hi_u32 v11, v8, v11
; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v13 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v13
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_mul_lo_u32 v13, v8, v9 ; CGP-NEXT: v_mul_lo_u32 v13, v8, v9
; CGP-NEXT: v_add_i32_e32 v10, vcc, v12, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v12, v10
; CGP-NEXT: v_mul_hi_u32 v12, v7, v9 ; CGP-NEXT: v_mul_hi_u32 v12, v7, v9
; CGP-NEXT: v_mul_hi_u32 v9, v8, v9 ; CGP-NEXT: v_mul_hi_u32 v9, v8, v9
; CGP-NEXT: v_add_i32_e32 v11, vcc, v13, v11 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v13, v11
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; CGP-NEXT: v_addc_u32_e64 v10, s[4:5], v8, v9, vcc ; CGP-NEXT: v_addc_u32_e64 v10, s[4:5], v8, v9, vcc
; CGP-NEXT: v_mul_lo_u32 v11, -1, v7 ; CGP-NEXT: v_mul_lo_u32 v11, -1, v7
; CGP-NEXT: v_mul_lo_u32 v12, s7, v10 ; CGP-NEXT: v_mul_lo_u32 v12, s6, v10
; CGP-NEXT: v_mul_hi_u32 v14, s7, v7 ; CGP-NEXT: v_mul_hi_u32 v14, s6, v7
; CGP-NEXT: v_mul_lo_u32 v13, s7, v7 ; CGP-NEXT: v_mul_lo_u32 v13, s6, v7
; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9 ; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12 ; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14 ; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14
; CGP-NEXT: v_mul_lo_u32 v12, v10, v13 ; CGP-NEXT: v_mul_lo_u32 v12, v10, v13
; CGP-NEXT: v_mul_lo_u32 v14, v7, v11 ; CGP-NEXT: v_mul_lo_u32 v14, v7, v11
; CGP-NEXT: v_mul_hi_u32 v9, v7, v13 ; CGP-NEXT: v_mul_hi_u32 v9, v7, v13
; CGP-NEXT: v_mul_hi_u32 v13, v10, v13 ; CGP-NEXT: v_mul_hi_u32 v13, v10, v13
; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v3 ; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14 ; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9 ; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5]
; CGP-NEXT: v_mul_lo_u32 v12, v10, v11 ; CGP-NEXT: v_mul_lo_u32 v12, v10, v11
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v14, v9 ; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v14, v9
; CGP-NEXT: v_mul_hi_u32 v14, v7, v11 ; CGP-NEXT: v_mul_hi_u32 v14, v7, v11
; CGP-NEXT: v_mul_hi_u32 v10, v10, v11 ; CGP-NEXT: v_mul_hi_u32 v10, v10, v11
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v13 ; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v13
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14 ; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v13, v14 ; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v13, v14
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9 ; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v13, v12 ; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v13, v12
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11 ; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11
; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v10, vcc ; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v10, vcc
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v9 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; CGP-NEXT: v_addc_u32_e32 v8, vcc, 0, v8, vcc ; CGP-NEXT: v_addc_u32_e32 v8, vcc, 0, v8, vcc
; CGP-NEXT: v_mul_lo_u32 v9, v1, v7 ; CGP-NEXT: v_mul_lo_u32 v9, v1, v7
; CGP-NEXT: v_mul_lo_u32 v10, v0, v8 ; CGP-NEXT: v_mul_lo_u32 v10, v0, v8
; CGP-NEXT: v_mul_hi_u32 v11, v0, v7 ; CGP-NEXT: v_mul_hi_u32 v11, v0, v7
; CGP-NEXT: v_mul_hi_u32 v7, v1, v7 ; CGP-NEXT: v_mul_hi_u32 v7, v1, v7
; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v3
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CGP-NEXT: v_mul_lo_u32 v11, v1, v8 ; CGP-NEXT: v_mul_lo_u32 v11, v1, v8
; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CGP-NEXT: v_mul_hi_u32 v10, v0, v8 ; CGP-NEXT: v_mul_hi_u32 v10, v0, v8
; CGP-NEXT: v_mul_hi_u32 v8, v1, v8 ; CGP-NEXT: v_mul_hi_u32 v8, v1, v8
; CGP-NEXT: v_add_i32_e32 v7, vcc, v11, v7 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v11, v7
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v9 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CGP-NEXT: v_mul_lo_u32 v9, 0, v7 ; CGP-NEXT: v_mul_lo_u32 v9, 0, v7
; CGP-NEXT: v_mul_lo_u32 v8, s6, v8 ; CGP-NEXT: v_mul_lo_u32 v8, s7, v8
; CGP-NEXT: v_mul_lo_u32 v10, s6, v7 ; CGP-NEXT: v_mul_lo_u32 v10, s7, v7
; CGP-NEXT: v_mul_hi_u32 v7, s6, v7 ; CGP-NEXT: v_mul_hi_u32 v7, s7, v7
; CGP-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CGP-NEXT: v_add_i32_e32 v7, vcc, v8, v7 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v10 ; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v10
; CGP-NEXT: v_subb_u32_e64 v8, s[4:5], v1, v7, vcc ; CGP-NEXT: v_subb_u32_e64 v8, s[4:5], v1, v7, vcc
; CGP-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v7 ; CGP-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v7
; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v8 ; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v8
; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v0 ; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v0
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v8 ; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v8
; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[4:5]
; CGP-NEXT: v_subrev_i32_e32 v9, vcc, s6, v0 ; CGP-NEXT: v_subrev_i32_e32 v9, vcc, s7, v0
; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v1 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v1
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s6, v9 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, s7, v9
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc
; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; CGP-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc ; CGP-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc
; CGP-NEXT: v_subrev_i32_e32 v11, vcc, s6, v9 ; CGP-NEXT: v_subrev_i32_e32 v11, vcc, s7, v9
; CGP-NEXT: v_subbrev_u32_e32 v12, vcc, 0, v1, vcc ; CGP-NEXT: v_subbrev_u32_e32 v12, vcc, 0, v1, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; CGP-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc ; CGP-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v12, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v12, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; CGP-NEXT: v_mul_f32_e32 v7, 0x2f800000, v4 ; CGP-NEXT: v_mul_f32_e32 v7, 0x2f800000, v4
; CGP-NEXT: v_trunc_f32_e32 v7, v7 ; CGP-NEXT: v_trunc_f32_e32 v7, v7
; CGP-NEXT: v_mac_f32_e32 v4, 0xcf800000, v7 ; CGP-NEXT: v_mac_f32_e32 v4, 0xcf800000, v7
; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4 ; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4
; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7 ; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc
; CGP-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
; CGP-NEXT: v_mul_lo_u32 v8, -1, v4 ; CGP-NEXT: v_mul_lo_u32 v8, -1, v4
; CGP-NEXT: v_mul_lo_u32 v9, s7, v7 ; CGP-NEXT: v_mul_lo_u32 v9, s6, v7
; CGP-NEXT: v_mul_hi_u32 v11, s7, v4 ; CGP-NEXT: v_mul_hi_u32 v11, s6, v4
; CGP-NEXT: v_mul_lo_u32 v10, s7, v4 ; CGP-NEXT: v_mul_lo_u32 v10, s6, v4
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v6 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v6, vcc ; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v6, vcc
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v11 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; CGP-NEXT: v_mul_lo_u32 v9, v7, v10 ; CGP-NEXT: v_mul_lo_u32 v9, v7, v10
; CGP-NEXT: v_mul_lo_u32 v11, v4, v8 ; CGP-NEXT: v_mul_lo_u32 v11, v4, v8
; CGP-NEXT: v_mul_hi_u32 v12, v4, v10 ; CGP-NEXT: v_mul_hi_u32 v12, v4, v10
; CGP-NEXT: v_mul_hi_u32 v10, v7, v10 ; CGP-NEXT: v_mul_hi_u32 v10, v7, v10
Show All 13 Lines
; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v10 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v9 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v9
; CGP-NEXT: v_addc_u32_e64 v9, s[4:5], v7, v8, vcc ; CGP-NEXT: v_addc_u32_e64 v9, s[4:5], v7, v8, vcc
; CGP-NEXT: v_mul_lo_u32 v10, -1, v4 ; CGP-NEXT: v_mul_lo_u32 v10, -1, v4
; CGP-NEXT: v_mul_lo_u32 v11, s7, v9 ; CGP-NEXT: v_mul_lo_u32 v11, s6, v9
; CGP-NEXT: v_mul_hi_u32 v13, s7, v4 ; CGP-NEXT: v_mul_hi_u32 v13, s6, v4
; CGP-NEXT: v_mul_lo_u32 v12, s7, v4 ; CGP-NEXT: v_mul_lo_u32 v12, s6, v4
; CGP-NEXT: v_add_i32_e64 v7, s[4:5], v7, v8 ; CGP-NEXT: v_add_i32_e64 v7, s[4:5], v7, v8
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11 ; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v13 ; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v13
; CGP-NEXT: v_mul_lo_u32 v11, v9, v12 ; CGP-NEXT: v_mul_lo_u32 v11, v9, v12
; CGP-NEXT: v_mul_lo_u32 v13, v4, v10 ; CGP-NEXT: v_mul_lo_u32 v13, v4, v10
; CGP-NEXT: v_mul_hi_u32 v8, v4, v12 ; CGP-NEXT: v_mul_hi_u32 v8, v4, v12
; CGP-NEXT: v_mul_hi_u32 v12, v9, v12 ; CGP-NEXT: v_mul_hi_u32 v12, v9, v12
; CGP-NEXT: v_xor_b32_e32 v2, v2, v6 ; CGP-NEXT: v_xor_b32_e32 v2, v2, v6
Show All 38 Lines
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v9 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v9
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v5 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v5
; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v5, vcc, v8, v5 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v8, v5
; CGP-NEXT: v_add_i32_e32 v5, vcc, v7, v5 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v7, v5
; CGP-NEXT: v_mul_lo_u32 v7, 0, v4 ; CGP-NEXT: v_mul_lo_u32 v7, 0, v4
; CGP-NEXT: v_mul_lo_u32 v5, s6, v5 ; CGP-NEXT: v_mul_lo_u32 v5, s7, v5
; CGP-NEXT: v_mul_lo_u32 v8, s6, v4 ; CGP-NEXT: v_mul_lo_u32 v8, s7, v4
; CGP-NEXT: v_mul_hi_u32 v4, s6, v4 ; CGP-NEXT: v_mul_hi_u32 v4, s7, v4
; CGP-NEXT: v_add_i32_e32 v5, vcc, v7, v5 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v7, v5
; CGP-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v8 ; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v8
; CGP-NEXT: v_subb_u32_e64 v5, s[4:5], v3, v4, vcc ; CGP-NEXT: v_subb_u32_e64 v5, s[4:5], v3, v4, vcc
; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v4 ; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v4
; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v5 ; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v5
; CGP-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v2 ; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v2
; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v5 ; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v5
; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc ; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
; CGP-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[4:5]
; CGP-NEXT: v_subrev_i32_e32 v7, vcc, s6, v2 ; CGP-NEXT: v_subrev_i32_e32 v7, vcc, s7, v2
; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc ; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v3 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v3
; CGP-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s6, v7 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, s7, v7
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc
; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 ; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; CGP-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc ; CGP-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc
; CGP-NEXT: v_subrev_i32_e32 v9, vcc, s6, v7 ; CGP-NEXT: v_subrev_i32_e32 v9, vcc, s7, v7
; CGP-NEXT: v_subbrev_u32_e32 v10, vcc, 0, v3, vcc ; CGP-NEXT: v_subbrev_u32_e32 v10, vcc, 0, v3, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; CGP-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc ; CGP-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v10, vcc ; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v10, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
; CGP-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc ; CGP-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; CGP-NEXT: v_xor_b32_e32 v2, v2, v6 ; CGP-NEXT: v_xor_b32_e32 v2, v2, v6
; CGP-NEXT: v_xor_b32_e32 v3, v3, v6 ; CGP-NEXT: v_xor_b32_e32 v3, v3, v6
; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v6 ; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v6
; CGP-NEXT: v_subb_u32_e32 v3, vcc, v3, v6, vcc ; CGP-NEXT: v_subb_u32_e32 v3, vcc, v3, v6, vcc
; CGP-NEXT: s_setpc_b64 s[30:31] ; CGP-NEXT: s_setpc_b64 s[30:31]
%result = srem <2 x i64> %num, <i64 4096, i64 4096> %result = srem <2 x i64> %num, <i64 4096, i64 4096>
ret <2 x i64> %result ret <2 x i64> %result
} }
define i64 @v_srem_i64_oddk_denom(i64 %num) { define i64 @v_srem_i64_oddk_denom(i64 %num) {
; CHECK-LABEL: v_srem_i64_oddk_denom: ; CHECK-LABEL: v_srem_i64_oddk_denom:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_mov_b32 s6, 0x12d8fb ; CHECK-NEXT: v_cvt_f32_u32_e32 v2, 0x12d8fb
; CHECK-NEXT: v_cvt_f32_u32_e32 v2, s6
; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v4, 0 ; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v4, 0
; CHECK-NEXT: s_mov_b32 s7, 0xffed2705 ; CHECK-NEXT: s_mov_b32 s6, 0xffed2705
; CHECK-NEXT: v_ashrrev_i32_e32 v3, 31, v1 ; CHECK-NEXT: v_ashrrev_i32_e32 v3, 31, v1
; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v4 ; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v4
; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3 ; CHECK-NEXT: v_add_i32_e32 v0, vcc, v0, v3
; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc ; CHECK-NEXT: v_addc_u32_e32 v1, vcc, v1, v3, vcc
; CHECK-NEXT: v_xor_b32_e32 v0, v0, v3 ; CHECK-NEXT: v_xor_b32_e32 v0, v0, v3
; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 ; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
; CHECK-NEXT: v_mul_f32_e32 v4, 0x2f800000, v2 ; CHECK-NEXT: v_mul_f32_e32 v4, 0x2f800000, v2
; CHECK-NEXT: v_trunc_f32_e32 v4, v4 ; CHECK-NEXT: v_trunc_f32_e32 v4, v4
; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v4 ; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v4
; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2 ; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4 ; CHECK-NEXT: v_cvt_u32_f32_e32 v4, v4
; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3 ; CHECK-NEXT: v_xor_b32_e32 v1, v1, v3
; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2 ; CHECK-NEXT: v_mul_lo_u32 v5, -1, v2
; CHECK-NEXT: v_mul_lo_u32 v6, s7, v4 ; CHECK-NEXT: v_mul_lo_u32 v6, s6, v4
; CHECK-NEXT: v_mul_hi_u32 v8, s7, v2 ; CHECK-NEXT: v_mul_hi_u32 v8, s6, v2
; CHECK-NEXT: v_mul_lo_u32 v7, s7, v2 ; CHECK-NEXT: v_mul_lo_u32 v7, s6, v2
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v8 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v8
; CHECK-NEXT: v_mul_lo_u32 v6, v4, v7 ; CHECK-NEXT: v_mul_lo_u32 v6, v4, v7
; CHECK-NEXT: v_mul_lo_u32 v8, v2, v5 ; CHECK-NEXT: v_mul_lo_u32 v8, v2, v5
; CHECK-NEXT: v_mul_hi_u32 v9, v2, v7 ; CHECK-NEXT: v_mul_hi_u32 v9, v2, v7
; CHECK-NEXT: v_mul_hi_u32 v7, v4, v7 ; CHECK-NEXT: v_mul_hi_u32 v7, v4, v7
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v6, v8
; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v8, 0, 1, vcc
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; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v7 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v7
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; CHECK-NEXT: v_addc_u32_e64 v6, s[4:5], v4, v5, vcc ; CHECK-NEXT: v_addc_u32_e64 v6, s[4:5], v4, v5, vcc
; CHECK-NEXT: v_mul_lo_u32 v7, -1, v2 ; CHECK-NEXT: v_mul_lo_u32 v7, -1, v2
; CHECK-NEXT: v_mul_lo_u32 v8, s7, v6 ; CHECK-NEXT: v_mul_lo_u32 v8, s6, v6
; CHECK-NEXT: v_mul_hi_u32 v10, s7, v2 ; CHECK-NEXT: v_mul_hi_u32 v10, s6, v2
; CHECK-NEXT: v_mul_lo_u32 v9, s7, v2 ; CHECK-NEXT: v_mul_lo_u32 v9, s6, v2
; CHECK-NEXT: v_add_i32_e64 v4, s[4:5], v4, v5 ; CHECK-NEXT: v_add_i32_e64 v4, s[4:5], v4, v5
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v8 ; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v8
; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v10 ; CHECK-NEXT: v_add_i32_e64 v7, s[4:5], v7, v10
; CHECK-NEXT: v_mul_lo_u32 v8, v6, v9 ; CHECK-NEXT: v_mul_lo_u32 v8, v6, v9
; CHECK-NEXT: v_mul_lo_u32 v10, v2, v7 ; CHECK-NEXT: v_mul_lo_u32 v10, v2, v7
; CHECK-NEXT: v_mul_hi_u32 v5, v2, v9 ; CHECK-NEXT: v_mul_hi_u32 v5, v2, v9
; CHECK-NEXT: v_mul_hi_u32 v9, v6, v9 ; CHECK-NEXT: v_mul_hi_u32 v9, v6, v9
; CHECK-NEXT: s_mov_b32 s6, 0x12d8fb
; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v10 ; CHECK-NEXT: v_add_i32_e64 v8, s[4:5], v8, v10
; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v10, 0, 1, s[4:5]
; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v8, v5 ; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v8, v5
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, s[4:5]
; CHECK-NEXT: v_mul_lo_u32 v8, v6, v7 ; CHECK-NEXT: v_mul_lo_u32 v8, v6, v7
; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v10, v5 ; CHECK-NEXT: v_add_i32_e64 v5, s[4:5], v10, v5
; CHECK-NEXT: v_mul_hi_u32 v10, v2, v7 ; CHECK-NEXT: v_mul_hi_u32 v10, v2, v7
; CHECK-NEXT: v_mul_hi_u32 v6, v6, v7 ; CHECK-NEXT: v_mul_hi_u32 v6, v6, v7
▲ Show 20 Lines • Show All 368 Lines • ▼ Show 20 Lines
; GISEL-NEXT: v_xor_b32_e32 v3, v3, v7 ; GISEL-NEXT: v_xor_b32_e32 v3, v3, v7
; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v7 ; GISEL-NEXT: v_sub_i32_e32 v2, vcc, v2, v7
; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v7, vcc ; GISEL-NEXT: v_subb_u32_e32 v3, vcc, v3, v7, vcc
; GISEL-NEXT: s_setpc_b64 s[30:31] ; GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; CGP-LABEL: v_srem_v2i64_oddk_denom: ; CGP-LABEL: v_srem_v2i64_oddk_denom:
; CGP: ; %bb.0: ; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CGP-NEXT: s_mov_b32 s6, 0x12d8fb ; CGP-NEXT: v_cvt_f32_u32_e32 v4, 0x12d8fb
; CGP-NEXT: v_cvt_f32_u32_e32 v4, s6
; CGP-NEXT: v_cvt_f32_ubyte0_e32 v6, 0 ; CGP-NEXT: v_cvt_f32_ubyte0_e32 v6, 0
; CGP-NEXT: s_mov_b32 s7, 0xffed2705 ; CGP-NEXT: s_mov_b32 s6, 0xffed2705
; CGP-NEXT: v_ashrrev_i32_e32 v5, 31, v1 ; CGP-NEXT: v_ashrrev_i32_e32 v5, 31, v1
; CGP-NEXT: v_mov_b32_e32 v7, v4 ; CGP-NEXT: v_mov_b32_e32 v7, v4
; CGP-NEXT: v_mac_f32_e32 v7, 0x4f800000, v6 ; CGP-NEXT: v_mac_f32_e32 v7, 0x4f800000, v6
; CGP-NEXT: v_rcp_iflag_f32_e32 v7, v7 ; CGP-NEXT: v_rcp_iflag_f32_e32 v7, v7
; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v5 ; CGP-NEXT: v_add_i32_e32 v0, vcc, v0, v5
; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v5, vcc ; CGP-NEXT: v_addc_u32_e32 v1, vcc, v1, v5, vcc
; CGP-NEXT: v_xor_b32_e32 v0, v0, v5 ; CGP-NEXT: v_xor_b32_e32 v0, v0, v5
; CGP-NEXT: v_mul_f32_e32 v7, 0x5f7ffffc, v7 ; CGP-NEXT: v_mul_f32_e32 v7, 0x5f7ffffc, v7
; CGP-NEXT: v_mul_f32_e32 v8, 0x2f800000, v7 ; CGP-NEXT: v_mul_f32_e32 v8, 0x2f800000, v7
; CGP-NEXT: v_trunc_f32_e32 v8, v8 ; CGP-NEXT: v_trunc_f32_e32 v8, v8
; CGP-NEXT: v_mac_f32_e32 v7, 0xcf800000, v8 ; CGP-NEXT: v_mac_f32_e32 v7, 0xcf800000, v8
; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7 ; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7
; CGP-NEXT: v_cvt_u32_f32_e32 v8, v8 ; CGP-NEXT: v_cvt_u32_f32_e32 v8, v8
; CGP-NEXT: v_xor_b32_e32 v1, v1, v5 ; CGP-NEXT: v_xor_b32_e32 v1, v1, v5
; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v6 ; CGP-NEXT: s_mov_b32 s7, 0x12d8fb
; CGP-NEXT: v_mul_lo_u32 v9, -1, v7 ; CGP-NEXT: v_mul_lo_u32 v9, -1, v7
; CGP-NEXT: v_mul_lo_u32 v10, s7, v8 ; CGP-NEXT: v_mul_lo_u32 v10, s6, v8
; CGP-NEXT: v_mul_hi_u32 v12, s7, v7 ; CGP-NEXT: v_mul_hi_u32 v12, s6, v7
; CGP-NEXT: v_mul_lo_u32 v11, s7, v7 ; CGP-NEXT: v_mul_lo_u32 v11, s6, v7
; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4 ; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v6
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v12
; CGP-NEXT: v_mul_lo_u32 v10, v8, v11 ; CGP-NEXT: v_mul_lo_u32 v10, v8, v11
; CGP-NEXT: v_mul_lo_u32 v12, v7, v9 ; CGP-NEXT: v_mul_lo_u32 v12, v7, v9
; CGP-NEXT: v_mul_hi_u32 v13, v7, v11 ; CGP-NEXT: v_mul_hi_u32 v13, v7, v11
; CGP-NEXT: v_mul_hi_u32 v11, v8, v11 ; CGP-NEXT: v_mul_hi_u32 v11, v8, v11
; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v13 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v10, v13
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_mul_lo_u32 v13, v8, v9 ; CGP-NEXT: v_mul_lo_u32 v13, v8, v9
; CGP-NEXT: v_add_i32_e32 v10, vcc, v12, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v12, v10
; CGP-NEXT: v_mul_hi_u32 v12, v7, v9 ; CGP-NEXT: v_mul_hi_u32 v12, v7, v9
; CGP-NEXT: v_mul_hi_u32 v9, v8, v9 ; CGP-NEXT: v_mul_hi_u32 v9, v8, v9
; CGP-NEXT: v_add_i32_e32 v11, vcc, v13, v11 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v13, v11
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v11, v12
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12 ; CGP-NEXT: v_add_i32_e32 v12, vcc, v13, v12
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; CGP-NEXT: v_addc_u32_e64 v10, s[4:5], v8, v9, vcc ; CGP-NEXT: v_addc_u32_e64 v10, s[4:5], v8, v9, vcc
; CGP-NEXT: v_mul_lo_u32 v11, -1, v7 ; CGP-NEXT: v_mul_lo_u32 v11, -1, v7
; CGP-NEXT: v_mul_lo_u32 v12, s7, v10 ; CGP-NEXT: v_mul_lo_u32 v12, s6, v10
; CGP-NEXT: v_mul_hi_u32 v14, s7, v7 ; CGP-NEXT: v_mul_hi_u32 v14, s6, v7
; CGP-NEXT: v_mul_lo_u32 v13, s7, v7 ; CGP-NEXT: v_mul_lo_u32 v13, s6, v7
; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9 ; CGP-NEXT: v_add_i32_e64 v8, s[4:5], v8, v9
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12 ; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v12
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14 ; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v11, v14
; CGP-NEXT: v_mul_lo_u32 v12, v10, v13 ; CGP-NEXT: v_mul_lo_u32 v12, v10, v13
; CGP-NEXT: v_mul_lo_u32 v14, v7, v11 ; CGP-NEXT: v_mul_lo_u32 v14, v7, v11
; CGP-NEXT: v_mul_hi_u32 v9, v7, v13 ; CGP-NEXT: v_mul_hi_u32 v9, v7, v13
; CGP-NEXT: v_mul_hi_u32 v13, v10, v13 ; CGP-NEXT: v_mul_hi_u32 v13, v10, v13
; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v3 ; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14 ; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9 ; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, s[4:5]
; CGP-NEXT: v_mul_lo_u32 v12, v10, v11 ; CGP-NEXT: v_mul_lo_u32 v12, v10, v11
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v14, v9 ; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v14, v9
; CGP-NEXT: v_mul_hi_u32 v14, v7, v11 ; CGP-NEXT: v_mul_hi_u32 v14, v7, v11
; CGP-NEXT: v_mul_hi_u32 v10, v10, v11 ; CGP-NEXT: v_mul_hi_u32 v10, v10, v11
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v13 ; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v13
; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v13, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14 ; CGP-NEXT: v_add_i32_e64 v12, s[4:5], v12, v14
; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v14, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v13, v14 ; CGP-NEXT: v_add_i32_e64 v13, s[4:5], v13, v14
; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9 ; CGP-NEXT: v_add_i32_e64 v9, s[4:5], v12, v9
; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v12, 0, 1, s[4:5]
; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v13, v12 ; CGP-NEXT: v_add_i32_e64 v11, s[4:5], v13, v12
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11 ; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11
; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v10, vcc ; CGP-NEXT: v_addc_u32_e32 v8, vcc, v8, v10, vcc
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v9 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; CGP-NEXT: v_addc_u32_e32 v8, vcc, 0, v8, vcc ; CGP-NEXT: v_addc_u32_e32 v8, vcc, 0, v8, vcc
; CGP-NEXT: v_mul_lo_u32 v9, v1, v7 ; CGP-NEXT: v_mul_lo_u32 v9, v1, v7
; CGP-NEXT: v_mul_lo_u32 v10, v0, v8 ; CGP-NEXT: v_mul_lo_u32 v10, v0, v8
; CGP-NEXT: v_mul_hi_u32 v11, v0, v7 ; CGP-NEXT: v_mul_hi_u32 v11, v0, v7
; CGP-NEXT: v_mul_hi_u32 v7, v1, v7 ; CGP-NEXT: v_mul_hi_u32 v7, v1, v7
; CGP-NEXT: v_ashrrev_i32_e32 v6, 31, v3
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v10
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v9, v11
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CGP-NEXT: v_mul_lo_u32 v11, v1, v8 ; CGP-NEXT: v_mul_lo_u32 v11, v1, v8
; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CGP-NEXT: v_mul_hi_u32 v10, v0, v8 ; CGP-NEXT: v_mul_hi_u32 v10, v0, v8
; CGP-NEXT: v_mul_hi_u32 v8, v1, v8 ; CGP-NEXT: v_mul_hi_u32 v8, v1, v8
; CGP-NEXT: v_add_i32_e32 v7, vcc, v11, v7 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v11, v7
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v10
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v9 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v7, v9
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CGP-NEXT: v_mul_lo_u32 v9, 0, v7 ; CGP-NEXT: v_mul_lo_u32 v9, 0, v7
; CGP-NEXT: v_mul_lo_u32 v8, s6, v8 ; CGP-NEXT: v_mul_lo_u32 v8, s7, v8
; CGP-NEXT: v_mul_lo_u32 v10, s6, v7 ; CGP-NEXT: v_mul_lo_u32 v10, s7, v7
; CGP-NEXT: v_mul_hi_u32 v7, s6, v7 ; CGP-NEXT: v_mul_hi_u32 v7, s7, v7
; CGP-NEXT: v_add_i32_e32 v8, vcc, v9, v8 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v9, v8
; CGP-NEXT: v_add_i32_e32 v7, vcc, v8, v7 ; CGP-NEXT: v_add_i32_e32 v7, vcc, v8, v7
; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v10 ; CGP-NEXT: v_sub_i32_e32 v0, vcc, v0, v10
; CGP-NEXT: v_subb_u32_e64 v8, s[4:5], v1, v7, vcc ; CGP-NEXT: v_subb_u32_e64 v8, s[4:5], v1, v7, vcc
; CGP-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v7 ; CGP-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v7
; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v8 ; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v8
; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v0 ; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v0
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v8 ; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v8
; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CGP-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v7, v7, v9, s[4:5]
; CGP-NEXT: v_subrev_i32_e32 v9, vcc, s6, v0 ; CGP-NEXT: v_subrev_i32_e32 v9, vcc, s7, v0
; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CGP-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v1 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v1
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, -1, vcc
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s6, v9 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, s7, v9
; CGP-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v11, 0, -1, vcc
; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; CGP-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc ; CGP-NEXT: v_cndmask_b32_e32 v10, v10, v11, vcc
; CGP-NEXT: v_subrev_i32_e32 v11, vcc, s6, v9 ; CGP-NEXT: v_subrev_i32_e32 v11, vcc, s7, v9
; CGP-NEXT: v_subbrev_u32_e32 v12, vcc, 0, v1, vcc ; CGP-NEXT: v_subbrev_u32_e32 v12, vcc, 0, v1, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v10
; CGP-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc ; CGP-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc
; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v12, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v1, v12, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v7
; CGP-NEXT: v_mul_f32_e32 v7, 0x2f800000, v4 ; CGP-NEXT: v_mul_f32_e32 v7, 0x2f800000, v4
; CGP-NEXT: v_trunc_f32_e32 v7, v7 ; CGP-NEXT: v_trunc_f32_e32 v7, v7
; CGP-NEXT: v_mac_f32_e32 v4, 0xcf800000, v7 ; CGP-NEXT: v_mac_f32_e32 v4, 0xcf800000, v7
; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4 ; CGP-NEXT: v_cvt_u32_f32_e32 v4, v4
; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7 ; CGP-NEXT: v_cvt_u32_f32_e32 v7, v7
; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc ; CGP-NEXT: v_cndmask_b32_e32 v0, v0, v9, vcc
; CGP-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc ; CGP-NEXT: v_cndmask_b32_e32 v1, v8, v1, vcc
; CGP-NEXT: v_mul_lo_u32 v8, -1, v4 ; CGP-NEXT: v_mul_lo_u32 v8, -1, v4
; CGP-NEXT: v_mul_lo_u32 v9, s7, v7 ; CGP-NEXT: v_mul_lo_u32 v9, s6, v7
; CGP-NEXT: v_mul_hi_u32 v11, s7, v4 ; CGP-NEXT: v_mul_hi_u32 v11, s6, v4
; CGP-NEXT: v_mul_lo_u32 v10, s7, v4 ; CGP-NEXT: v_mul_lo_u32 v10, s6, v4
; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v6 ; CGP-NEXT: v_add_i32_e32 v2, vcc, v2, v6
; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v6, vcc ; CGP-NEXT: v_addc_u32_e32 v3, vcc, v3, v6, vcc
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v11 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v11
; CGP-NEXT: v_mul_lo_u32 v9, v7, v10 ; CGP-NEXT: v_mul_lo_u32 v9, v7, v10
; CGP-NEXT: v_mul_lo_u32 v11, v4, v8 ; CGP-NEXT: v_mul_lo_u32 v11, v4, v8
; CGP-NEXT: v_mul_hi_u32 v12, v4, v10 ; CGP-NEXT: v_mul_hi_u32 v12, v4, v10
; CGP-NEXT: v_mul_hi_u32 v10, v7, v10 ; CGP-NEXT: v_mul_hi_u32 v10, v7, v10
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; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11 ; CGP-NEXT: v_add_i32_e32 v11, vcc, v12, v11
; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9 ; CGP-NEXT: v_add_i32_e32 v9, vcc, v10, v9
; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v10, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10 ; CGP-NEXT: v_add_i32_e32 v10, vcc, v11, v10
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v10 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v10
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v9 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v9
; CGP-NEXT: v_addc_u32_e64 v9, s[4:5], v7, v8, vcc ; CGP-NEXT: v_addc_u32_e64 v9, s[4:5], v7, v8, vcc
; CGP-NEXT: v_mul_lo_u32 v10, -1, v4 ; CGP-NEXT: v_mul_lo_u32 v10, -1, v4
; CGP-NEXT: v_mul_lo_u32 v11, s7, v9 ; CGP-NEXT: v_mul_lo_u32 v11, s6, v9
; CGP-NEXT: v_mul_hi_u32 v13, s7, v4 ; CGP-NEXT: v_mul_hi_u32 v13, s6, v4
; CGP-NEXT: v_mul_lo_u32 v12, s7, v4 ; CGP-NEXT: v_mul_lo_u32 v12, s6, v4
; CGP-NEXT: v_add_i32_e64 v7, s[4:5], v7, v8 ; CGP-NEXT: v_add_i32_e64 v7, s[4:5], v7, v8
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11 ; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v11
; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v13 ; CGP-NEXT: v_add_i32_e64 v10, s[4:5], v10, v13
; CGP-NEXT: v_mul_lo_u32 v11, v9, v12 ; CGP-NEXT: v_mul_lo_u32 v11, v9, v12
; CGP-NEXT: v_mul_lo_u32 v13, v4, v10 ; CGP-NEXT: v_mul_lo_u32 v13, v4, v10
; CGP-NEXT: v_mul_hi_u32 v8, v4, v12 ; CGP-NEXT: v_mul_hi_u32 v8, v4, v12
; CGP-NEXT: v_mul_hi_u32 v12, v9, v12 ; CGP-NEXT: v_mul_hi_u32 v12, v9, v12
; CGP-NEXT: v_xor_b32_e32 v2, v2, v6 ; CGP-NEXT: v_xor_b32_e32 v2, v2, v6
Show All 38 Lines
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v9 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v9
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9 ; CGP-NEXT: v_add_i32_e32 v8, vcc, v8, v9
; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v5 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v4, v5
; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; CGP-NEXT: v_add_i32_e32 v5, vcc, v8, v5 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v8, v5
; CGP-NEXT: v_add_i32_e32 v5, vcc, v7, v5 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v7, v5
; CGP-NEXT: v_mul_lo_u32 v7, 0, v4 ; CGP-NEXT: v_mul_lo_u32 v7, 0, v4
; CGP-NEXT: v_mul_lo_u32 v5, s6, v5 ; CGP-NEXT: v_mul_lo_u32 v5, s7, v5
; CGP-NEXT: v_mul_lo_u32 v8, s6, v4 ; CGP-NEXT: v_mul_lo_u32 v8, s7, v4
; CGP-NEXT: v_mul_hi_u32 v4, s6, v4 ; CGP-NEXT: v_mul_hi_u32 v4, s7, v4
; CGP-NEXT: v_add_i32_e32 v5, vcc, v7, v5 ; CGP-NEXT: v_add_i32_e32 v5, vcc, v7, v5
; CGP-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; CGP-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v8 ; CGP-NEXT: v_sub_i32_e32 v2, vcc, v2, v8
; CGP-NEXT: v_subb_u32_e64 v5, s[4:5], v3, v4, vcc ; CGP-NEXT: v_subb_u32_e64 v5, s[4:5], v3, v4, vcc
; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v4 ; CGP-NEXT: v_sub_i32_e64 v3, s[4:5], v3, v4
; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v5 ; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v5
; CGP-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v2 ; CGP-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v2
; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v5 ; CGP-NEXT: v_cmp_eq_u32_e64 s[4:5], 0, v5
; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc ; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
; CGP-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[4:5] ; CGP-NEXT: v_cndmask_b32_e64 v4, v4, v7, s[4:5]
; CGP-NEXT: v_subrev_i32_e32 v7, vcc, s6, v2 ; CGP-NEXT: v_subrev_i32_e32 v7, vcc, s7, v2
; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc ; CGP-NEXT: v_subbrev_u32_e32 v3, vcc, 0, v3, vcc
; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v3 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, 0, v3
; CGP-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v8, 0, -1, vcc
; CGP-NEXT: v_cmp_le_u32_e32 vcc, s6, v7 ; CGP-NEXT: v_cmp_le_u32_e32 vcc, s7, v7
; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc ; CGP-NEXT: v_cndmask_b32_e64 v9, 0, -1, vcc
; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 ; CGP-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; CGP-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc ; CGP-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc
; CGP-NEXT: v_subrev_i32_e32 v9, vcc, s6, v7 ; CGP-NEXT: v_subrev_i32_e32 v9, vcc, s7, v7
; CGP-NEXT: v_subbrev_u32_e32 v10, vcc, 0, v3, vcc ; CGP-NEXT: v_subbrev_u32_e32 v10, vcc, 0, v3, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; CGP-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc ; CGP-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc
; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v10, vcc ; CGP-NEXT: v_cndmask_b32_e32 v3, v3, v10, vcc
; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4 ; CGP-NEXT: v_cmp_ne_u32_e32 vcc, 0, v4
; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc ; CGP-NEXT: v_cndmask_b32_e32 v2, v2, v7, vcc
; CGP-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc ; CGP-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc
; CGP-NEXT: v_xor_b32_e32 v2, v2, v6 ; CGP-NEXT: v_xor_b32_e32 v2, v2, v6
▲ Show 20 Lines • Show All 1,229 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll

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Show First 20 Lines • Show All 4,978 Lines • ▼ Show 20 Lines
; GFX6-LABEL: v_ssubsat_v2i64: ; GFX6-LABEL: v_ssubsat_v2i64:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX6-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v0, v4 ; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v0, v4
; GFX6-NEXT: v_subb_u32_e32 v9, vcc, v1, v5, vcc ; GFX6-NEXT: v_subb_u32_e32 v9, vcc, v1, v5, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[8:9], v[0:1] ; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[8:9], v[0:1]
; GFX6-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[4:5] ; GFX6-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[4:5]
; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v9 ; GFX6-NEXT: v_ashrrev_i32_e32 v0, 31, v9
; GFX6-NEXT: s_brev_b32 s8, 1 ; GFX6-NEXT: v_bfrev_b32_e32 v10, 1
; GFX6-NEXT: v_mov_b32_e32 v1, s8 ; GFX6-NEXT: v_add_i32_e64 v1, s[6:7], 0, v0
; GFX6-NEXT: v_add_i32_e64 v4, s[6:7], 0, v0
; GFX6-NEXT: s_xor_b64 vcc, s[4:5], vcc ; GFX6-NEXT: s_xor_b64 vcc, s[4:5], vcc
; GFX6-NEXT: v_addc_u32_e64 v1, s[6:7], v0, v1, s[6:7] ; GFX6-NEXT: v_addc_u32_e64 v4, s[6:7], v0, v10, s[6:7]
; GFX6-NEXT: v_cndmask_b32_e32 v0, v8, v4, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v8, v1, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc
; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v2, v6 ; GFX6-NEXT: v_sub_i32_e32 v4, vcc, v2, v6
; GFX6-NEXT: v_subb_u32_e32 v5, vcc, v3, v7, vcc ; GFX6-NEXT: v_subb_u32_e32 v5, vcc, v3, v7, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[2:3] ; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[2:3]
; GFX6-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[6:7] ; GFX6-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[6:7]
; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v5 ; GFX6-NEXT: v_ashrrev_i32_e32 v2, 31, v5
; GFX6-NEXT: v_mov_b32_e32 v3, s8 ; GFX6-NEXT: v_add_i32_e64 v3, s[6:7], 0, v2
; GFX6-NEXT: v_add_i32_e64 v6, s[6:7], 0, v2 ; GFX6-NEXT: v_addc_u32_e64 v6, s[6:7], v2, v10, s[6:7]
; GFX6-NEXT: v_addc_u32_e64 v3, s[6:7], v2, v3, s[6:7]
; GFX6-NEXT: s_xor_b64 vcc, s[4:5], vcc ; GFX6-NEXT: s_xor_b64 vcc, s[4:5], vcc
; GFX6-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v2, v4, v3, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31] ; GFX6-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX8-LABEL: v_ssubsat_v2i64: ; GFX8-LABEL: v_ssubsat_v2i64:
; GFX8: ; %bb.0: ; GFX8: ; %bb.0:
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_sub_u32_e32 v8, vcc, v0, v4 ; GFX8-NEXT: v_sub_u32_e32 v8, vcc, v0, v4
; GFX8-NEXT: v_subb_u32_e32 v9, vcc, v1, v5, vcc ; GFX8-NEXT: v_subb_u32_e32 v9, vcc, v1, v5, vcc
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[8:9], v[0:1] ; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[8:9], v[0:1]
; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[4:5] ; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[4:5]
; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v9 ; GFX8-NEXT: v_ashrrev_i32_e32 v0, 31, v9
; GFX8-NEXT: s_brev_b32 s8, 1 ; GFX8-NEXT: v_bfrev_b32_e32 v10, 1
; GFX8-NEXT: v_mov_b32_e32 v1, s8 ; GFX8-NEXT: v_add_u32_e64 v1, s[6:7], 0, v0
; GFX8-NEXT: v_add_u32_e64 v4, s[6:7], 0, v0
; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
; GFX8-NEXT: v_addc_u32_e64 v1, s[6:7], v0, v1, s[6:7] ; GFX8-NEXT: v_addc_u32_e64 v4, s[6:7], v0, v10, s[6:7]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v8, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v8, v1, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc
; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v2, v6 ; GFX8-NEXT: v_sub_u32_e32 v4, vcc, v2, v6
; GFX8-NEXT: v_subb_u32_e32 v5, vcc, v3, v7, vcc ; GFX8-NEXT: v_subb_u32_e32 v5, vcc, v3, v7, vcc
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[2:3] ; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[2:3]
; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[6:7] ; GFX8-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[6:7]
; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v5 ; GFX8-NEXT: v_ashrrev_i32_e32 v2, 31, v5
; GFX8-NEXT: v_mov_b32_e32 v3, s8 ; GFX8-NEXT: v_add_u32_e64 v3, s[6:7], 0, v2
; GFX8-NEXT: v_add_u32_e64 v6, s[6:7], 0, v2 ; GFX8-NEXT: v_addc_u32_e64 v6, s[6:7], v2, v10, s[6:7]
; GFX8-NEXT: v_addc_u32_e64 v3, s[6:7], v2, v3, s[6:7]
; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc ; GFX8-NEXT: s_xor_b64 vcc, s[4:5], vcc
; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v2, v4, v3, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX9-LABEL: v_ssubsat_v2i64: ; GFX9-LABEL: v_ssubsat_v2i64:
; GFX9: ; %bb.0: ; GFX9: ; %bb.0:
; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX9-NEXT: v_sub_co_u32_e32 v8, vcc, v0, v4 ; GFX9-NEXT: v_sub_co_u32_e32 v8, vcc, v0, v4
; GFX9-NEXT: v_subb_co_u32_e32 v9, vcc, v1, v5, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v9, vcc, v1, v5, vcc
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[8:9], v[0:1] ; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[8:9], v[0:1]
; GFX9-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[4:5] ; GFX9-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[4:5]
; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v9 ; GFX9-NEXT: v_ashrrev_i32_e32 v0, 31, v9
; GFX9-NEXT: s_brev_b32 s8, 1 ; GFX9-NEXT: v_bfrev_b32_e32 v10, 1
; GFX9-NEXT: v_mov_b32_e32 v1, s8 ; GFX9-NEXT: v_add_co_u32_e64 v1, s[6:7], 0, v0
; GFX9-NEXT: v_add_co_u32_e64 v4, s[6:7], 0, v0
; GFX9-NEXT: s_xor_b64 vcc, s[4:5], vcc ; GFX9-NEXT: s_xor_b64 vcc, s[4:5], vcc
; GFX9-NEXT: v_addc_co_u32_e64 v1, s[6:7], v0, v1, s[6:7] ; GFX9-NEXT: v_addc_co_u32_e64 v4, s[6:7], v0, v10, s[6:7]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v8, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v8, v1, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc
; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v2, v6 ; GFX9-NEXT: v_sub_co_u32_e32 v4, vcc, v2, v6
; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v3, v7, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v5, vcc, v3, v7, vcc
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[2:3] ; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[4:5], v[2:3]
; GFX9-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[6:7] ; GFX9-NEXT: v_cmp_lt_i64_e64 s[4:5], 0, v[6:7]
; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v5 ; GFX9-NEXT: v_ashrrev_i32_e32 v2, 31, v5
; GFX9-NEXT: v_mov_b32_e32 v3, s8 ; GFX9-NEXT: v_add_co_u32_e64 v3, s[6:7], 0, v2
; GFX9-NEXT: v_add_co_u32_e64 v6, s[6:7], 0, v2 ; GFX9-NEXT: v_addc_co_u32_e64 v6, s[6:7], v2, v10, s[6:7]
; GFX9-NEXT: v_addc_co_u32_e64 v3, s[6:7], v2, v3, s[6:7]
; GFX9-NEXT: s_xor_b64 vcc, s[4:5], vcc ; GFX9-NEXT: s_xor_b64 vcc, s[4:5], vcc
; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v4, v3, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v5, v6, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
; GFX10-LABEL: v_ssubsat_v2i64: ; GFX10-LABEL: v_ssubsat_v2i64:
; GFX10: ; %bb.0: ; GFX10: ; %bb.0:
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: s_waitcnt_vscnt null, 0x0 ; GFX10-NEXT: s_waitcnt_vscnt null, 0x0
; GFX10-NEXT: v_mov_b32_e32 v9, v0 ; GFX10-NEXT: v_mov_b32_e32 v14, v0
; GFX10-NEXT: v_mov_b32_e32 v10, v1 ; GFX10-NEXT: v_mov_b32_e32 v15, v1
; GFX10-NEXT: v_mov_b32_e32 v13, v2 ; GFX10-NEXT: v_mov_b32_e32 v17, v2
; GFX10-NEXT: v_mov_b32_e32 v14, v3 ; GFX10-NEXT: v_mov_b32_e32 v18, v3
; GFX10-NEXT: v_cmp_lt_i64_e64 s4, 0, v[4:5] ; GFX10-NEXT: v_cmp_lt_i64_e64 s4, 0, v[4:5]
; GFX10-NEXT: v_sub_co_u32_e64 v19, vcc_lo, v9, v4 ; GFX10-NEXT: v_sub_co_u32_e64 v8, vcc_lo, v14, v4
; GFX10-NEXT: s_brev_b32 s8, 1
; GFX10-NEXT: v_sub_co_ci_u32_e32 v20, vcc_lo, v10, v5, vcc_lo
; GFX10-NEXT: v_sub_co_u32_e64 v23, vcc_lo, v13, v6
; GFX10-NEXT: v_cmp_lt_i64_e64 s6, 0, v[6:7] ; GFX10-NEXT: v_cmp_lt_i64_e64 s6, 0, v[6:7]
; GFX10-NEXT: v_sub_co_ci_u32_e32 v24, vcc_lo, v14, v7, vcc_lo ; GFX10-NEXT: v_sub_co_ci_u32_e32 v9, vcc_lo, v15, v5, vcc_lo
; GFX10-NEXT: v_sub_co_u32_e64 v19, vcc_lo, v17, v6
; GFX10-NEXT: ; implicit-def: $vcc_hi ; GFX10-NEXT: ; implicit-def: $vcc_hi
; GFX10-NEXT: v_sub_co_ci_u32_e32 v20, vcc_lo, v18, v7, vcc_lo
; GFX10-NEXT: v_ashrrev_i32_e32 v12, 31, v9
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[8:9], v[14:15]
; GFX10-NEXT: v_ashrrev_i32_e32 v0, 31, v20 ; GFX10-NEXT: v_ashrrev_i32_e32 v0, 31, v20
; GFX10-NEXT: v_cmp_lt_i64_e32 vcc_lo, v[19:20], v[9:10] ; GFX10-NEXT: v_add_co_u32_e64 v1, s5, v12, 0
; GFX10-NEXT: v_ashrrev_i32_e32 v1, 31, v24 ; GFX10-NEXT: v_add_co_ci_u32_e64 v4, s5, 0x80000000, v12, s5
; GFX10-NEXT: v_add_co_u32_e64 v4, s5, v0, 0 ; GFX10-NEXT: v_cmp_lt_i64_e64 s5, v[19:20], v[17:18]
; GFX10-NEXT: v_add_co_ci_u32_e64 v5, s5, s8, v0, s5 ; GFX10-NEXT: v_add_co_u32_e64 v2, s7, v0, 0
; GFX10-NEXT: v_cmp_lt_i64_e64 s5, v[23:24], v[13:14]
; GFX10-NEXT: v_add_co_u32_e64 v2, s7, v1, 0
; GFX10-NEXT: s_xor_b32 vcc_lo, s4, vcc_lo ; GFX10-NEXT: s_xor_b32 vcc_lo, s4, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s7, s8, v1, s7 ; GFX10-NEXT: v_add_co_ci_u32_e64 v3, s7, 0x80000000, v0, s7
; GFX10-NEXT: v_cndmask_b32_e32 v0, v19, v4, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v8, v1, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v1, v20, v5, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v9, v4, vcc_lo
; GFX10-NEXT: s_xor_b32 vcc_lo, s6, s5 ; GFX10-NEXT: s_xor_b32 vcc_lo, s6, s5
; GFX10-NEXT: v_cndmask_b32_e32 v2, v23, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v19, v2, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v3, v24, v3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v20, v3, vcc_lo
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs) %result = call <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64> %lhs, <2 x i64> %rhs)
ret <2 x i64> %result ret <2 x i64> %result
} }
define amdgpu_ps <2 x i64> @s_ssubsat_v2i64(<2 x i64> inreg %lhs, <2 x i64> inreg %rhs) { define amdgpu_ps <2 x i64> @s_ssubsat_v2i64(<2 x i64> inreg %lhs, <2 x i64> inreg %rhs) {
; GFX6-LABEL: s_ssubsat_v2i64: ; GFX6-LABEL: s_ssubsat_v2i64:
; GFX6: ; %bb.0: ; GFX6: ; %bb.0:
▲ Show 20 Lines • Show All 1,104 Lines • ▼ Show 20 Lines
; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 ; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX6-NEXT: s_and_b32 s4, 1, s5 ; GFX6-NEXT: s_and_b32 s4, 1, s5
; GFX6-NEXT: v_ashr_i64 v[8:9], v[18:19], s6 ; GFX6-NEXT: v_ashr_i64 v[8:9], v[18:19], s6
; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX6-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, s4 ; GFX6-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, s4
; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX6-NEXT: v_ashrrev_i32_e32 v11, 31, v19 ; GFX6-NEXT: v_ashrrev_i32_e32 v11, 31, v19
; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v16, s[4:5] ; GFX6-NEXT: v_cndmask_b32_e64 v0, v0, v16, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v17, s[4:5]
; GFX6-NEXT: v_cndmask_b32_e32 v2, v11, v8, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v2, v11, v8, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc
; GFX6-NEXT: v_cndmask_b32_e64 v1, v1, v17, s[4:5]
; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0, v0 ; GFX6-NEXT: v_add_i32_e32 v0, vcc, 0, v0
; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX6-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX6-NEXT: s_brev_b32 s4, 1 ; GFX6-NEXT: v_bfrev_b32_e32 v20, 1
; GFX6-NEXT: v_mov_b32_e32 v8, s4
; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc ; GFX6-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc
; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc ; GFX6-NEXT: v_addc_u32_e32 v3, vcc, v3, v20, vcc
; GFX6-NEXT: v_and_b32_e32 v8, 1, v10 ; GFX6-NEXT: v_and_b32_e32 v8, 1, v10
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX6-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v4, v12 ; GFX6-NEXT: v_sub_i32_e32 v8, vcc, v4, v12
; GFX6-NEXT: v_subb_u32_e32 v9, vcc, v5, v13, vcc ; GFX6-NEXT: v_subb_u32_e32 v9, vcc, v5, v13, vcc
; GFX6-NEXT: v_subb_u32_e32 v10, vcc, v6, v14, vcc ; GFX6-NEXT: v_subb_u32_e32 v10, vcc, v6, v14, vcc
; GFX6-NEXT: v_subb_u32_e32 v11, vcc, v7, v15, vcc ; GFX6-NEXT: v_subb_u32_e32 v11, vcc, v7, v15, vcc
; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] ; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
; GFX6-NEXT: s_cmp_lt_u32 s6, 64 ; GFX6-NEXT: s_cmp_lt_u32 s6, 64
; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7] ; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7]
; GFX6-NEXT: s_cselect_b32 s5, 1, 0 ; GFX6-NEXT: s_cselect_b32 s4, 1, 0
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7] ; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7]
; GFX6-NEXT: s_cmp_eq_u32 s6, 0 ; GFX6-NEXT: s_cmp_eq_u32 s6, 0
; GFX6-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[12:13] ; GFX6-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[12:13]
; GFX6-NEXT: s_cselect_b32 s9, 1, 0 ; GFX6-NEXT: s_cselect_b32 s5, 1, 0
; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[14:15] ; GFX6-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[14:15]
; GFX6-NEXT: v_ashr_i64 v[12:13], v[10:11], s6 ; GFX6-NEXT: v_ashr_i64 v[12:13], v[10:11], s6
; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX6-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15] ; GFX6-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15]
; GFX6-NEXT: v_ashrrev_i32_e32 v15, 31, v11 ; GFX6-NEXT: s_and_b32 s5, 1, s5
; GFX6-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
; GFX6-NEXT: v_xor_b32_e32 v14, v5, v4 ; GFX6-NEXT: v_xor_b32_e32 v14, v5, v4
; GFX6-NEXT: v_lshr_b64 v[4:5], v[8:9], s6 ; GFX6-NEXT: v_lshr_b64 v[4:5], v[8:9], s6
; GFX6-NEXT: v_lshl_b64 v[6:7], v[10:11], s8 ; GFX6-NEXT: v_lshl_b64 v[6:7], v[10:11], s8
; GFX6-NEXT: s_and_b32 s6, 1, s5 ; GFX6-NEXT: s_and_b32 s6, 1, s4
; GFX6-NEXT: v_or_b32_e32 v6, v4, v6 ; GFX6-NEXT: v_or_b32_e32 v6, v4, v6
; GFX6-NEXT: v_or_b32_e32 v7, v5, v7 ; GFX6-NEXT: v_or_b32_e32 v7, v5, v7
; GFX6-NEXT: v_ashr_i64 v[4:5], v[10:11], s7 ; GFX6-NEXT: v_ashr_i64 v[4:5], v[10:11], s7
; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6 ; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6
; GFX6-NEXT: s_and_b32 s6, 1, s9
; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6 ; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5
; GFX6-NEXT: s_and_b32 s5, 1, s5 ; GFX6-NEXT: s_and_b32 s4, 1, s4
; GFX6-NEXT: v_ashrrev_i32_e32 v15, 31, v11
; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc
; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5 ; GFX6-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX6-NEXT: v_cndmask_b32_e32 v6, v15, v12, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v6, v15, v12, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v7, v15, v13, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v7, v15, v13, vcc
; GFX6-NEXT: v_add_i32_e32 v4, vcc, 0, v4 ; GFX6-NEXT: v_add_i32_e32 v4, vcc, 0, v4
; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc ; GFX6-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; GFX6-NEXT: v_mov_b32_e32 v12, s4
; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc ; GFX6-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc
; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v7, v12, vcc ; GFX6-NEXT: v_addc_u32_e32 v7, vcc, v7, v20, vcc
; GFX6-NEXT: v_and_b32_e32 v12, 1, v14 ; GFX6-NEXT: v_and_b32_e32 v12, 1, v14
; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 ; GFX6-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; GFX6-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc
; GFX6-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc ; GFX6-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc
; GFX6-NEXT: s_setpc_b64 s[30:31] ; GFX6-NEXT: s_setpc_b64 s[30:31]
; ;
Show All 33 Lines
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX8-NEXT: s_and_b32 s4, 1, s5 ; GFX8-NEXT: s_and_b32 s4, 1, s5
; GFX8-NEXT: v_ashrrev_i64 v[8:9], s6, v[18:19] ; GFX8-NEXT: v_ashrrev_i64 v[8:9], s6, v[18:19]
; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX8-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, s4 ; GFX8-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, s4
; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX8-NEXT: v_ashrrev_i32_e32 v11, 31, v19 ; GFX8-NEXT: v_ashrrev_i32_e32 v11, 31, v19
; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v16, s[4:5] ; GFX8-NEXT: v_cndmask_b32_e64 v0, v0, v16, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v17, s[4:5]
; GFX8-NEXT: v_cndmask_b32_e32 v2, v11, v8, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v2, v11, v8, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc
; GFX8-NEXT: v_cndmask_b32_e64 v1, v1, v17, s[4:5]
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0, v0 ; GFX8-NEXT: v_add_u32_e32 v0, vcc, 0, v0
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: s_brev_b32 s4, 1 ; GFX8-NEXT: v_bfrev_b32_e32 v20, 1
; GFX8-NEXT: v_mov_b32_e32 v8, s4
; GFX8-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc ; GFX8-NEXT: v_addc_u32_e32 v2, vcc, 0, v2, vcc
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v3, v8, vcc ; GFX8-NEXT: v_addc_u32_e32 v3, vcc, v3, v20, vcc
; GFX8-NEXT: v_and_b32_e32 v8, 1, v10 ; GFX8-NEXT: v_and_b32_e32 v8, 1, v10
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX8-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
; GFX8-NEXT: v_sub_u32_e32 v8, vcc, v4, v12 ; GFX8-NEXT: v_sub_u32_e32 v8, vcc, v4, v12
; GFX8-NEXT: v_subb_u32_e32 v9, vcc, v5, v13, vcc ; GFX8-NEXT: v_subb_u32_e32 v9, vcc, v5, v13, vcc
; GFX8-NEXT: v_subb_u32_e32 v10, vcc, v6, v14, vcc ; GFX8-NEXT: v_subb_u32_e32 v10, vcc, v6, v14, vcc
; GFX8-NEXT: v_subb_u32_e32 v11, vcc, v7, v15, vcc ; GFX8-NEXT: v_subb_u32_e32 v11, vcc, v7, v15, vcc
; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] ; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
; GFX8-NEXT: s_cmp_lt_u32 s6, 64 ; GFX8-NEXT: s_cmp_lt_u32 s6, 64
; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7] ; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7]
; GFX8-NEXT: s_cselect_b32 s5, 1, 0 ; GFX8-NEXT: s_cselect_b32 s4, 1, 0
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7] ; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7]
; GFX8-NEXT: s_cmp_eq_u32 s6, 0 ; GFX8-NEXT: s_cmp_eq_u32 s6, 0
; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[12:13] ; GFX8-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[12:13]
; GFX8-NEXT: s_cselect_b32 s9, 1, 0 ; GFX8-NEXT: s_cselect_b32 s5, 1, 0
; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[14:15] ; GFX8-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[14:15]
; GFX8-NEXT: v_ashrrev_i64 v[12:13], s6, v[10:11] ; GFX8-NEXT: v_ashrrev_i64 v[12:13], s6, v[10:11]
; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX8-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15] ; GFX8-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15]
; GFX8-NEXT: v_ashrrev_i32_e32 v15, 31, v11 ; GFX8-NEXT: s_and_b32 s5, 1, s5
; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
; GFX8-NEXT: v_xor_b32_e32 v14, v5, v4 ; GFX8-NEXT: v_xor_b32_e32 v14, v5, v4
; GFX8-NEXT: v_lshrrev_b64 v[4:5], s6, v[8:9] ; GFX8-NEXT: v_lshrrev_b64 v[4:5], s6, v[8:9]
; GFX8-NEXT: v_lshlrev_b64 v[6:7], s8, v[10:11] ; GFX8-NEXT: v_lshlrev_b64 v[6:7], s8, v[10:11]
; GFX8-NEXT: s_and_b32 s6, 1, s5 ; GFX8-NEXT: s_and_b32 s6, 1, s4
; GFX8-NEXT: v_or_b32_e32 v6, v4, v6 ; GFX8-NEXT: v_or_b32_e32 v6, v4, v6
; GFX8-NEXT: v_or_b32_e32 v7, v5, v7 ; GFX8-NEXT: v_or_b32_e32 v7, v5, v7
; GFX8-NEXT: v_ashrrev_i64 v[4:5], s7, v[10:11] ; GFX8-NEXT: v_ashrrev_i64 v[4:5], s7, v[10:11]
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6 ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6
; GFX8-NEXT: s_and_b32 s6, 1, s9
; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6 ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5
; GFX8-NEXT: s_and_b32 s5, 1, s5 ; GFX8-NEXT: s_and_b32 s4, 1, s4
; GFX8-NEXT: v_ashrrev_i32_e32 v15, 31, v11
; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc
; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5 ; GFX8-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX8-NEXT: v_cndmask_b32_e32 v6, v15, v12, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v6, v15, v12, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v7, v15, v13, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v7, v15, v13, vcc
; GFX8-NEXT: v_add_u32_e32 v4, vcc, 0, v4 ; GFX8-NEXT: v_add_u32_e32 v4, vcc, 0, v4
; GFX8-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc ; GFX8-NEXT: v_addc_u32_e32 v5, vcc, 0, v5, vcc
; GFX8-NEXT: v_mov_b32_e32 v12, s4
; GFX8-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc ; GFX8-NEXT: v_addc_u32_e32 v6, vcc, 0, v6, vcc
; GFX8-NEXT: v_addc_u32_e32 v7, vcc, v7, v12, vcc ; GFX8-NEXT: v_addc_u32_e32 v7, vcc, v7, v20, vcc
; GFX8-NEXT: v_and_b32_e32 v12, 1, v14 ; GFX8-NEXT: v_and_b32_e32 v12, 1, v14
; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 ; GFX8-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; GFX8-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc
; GFX8-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc ; GFX8-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc
; GFX8-NEXT: s_setpc_b64 s[30:31] ; GFX8-NEXT: s_setpc_b64 s[30:31]
; ;
Show All 33 Lines
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4 ; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX9-NEXT: s_and_b32 s4, 1, s5 ; GFX9-NEXT: s_and_b32 s4, 1, s5
; GFX9-NEXT: v_ashrrev_i64 v[8:9], s6, v[18:19] ; GFX9-NEXT: v_ashrrev_i64 v[8:9], s6, v[18:19]
; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v0, v2, vcc
; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, s4 ; GFX9-NEXT: v_cmp_ne_u32_e64 s[4:5], 0, s4
; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v1, v3, vcc
; GFX9-NEXT: v_ashrrev_i32_e32 v11, 31, v19 ; GFX9-NEXT: v_ashrrev_i32_e32 v11, 31, v19
; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v16, s[4:5] ; GFX9-NEXT: v_cndmask_b32_e64 v0, v0, v16, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v17, s[4:5]
; GFX9-NEXT: v_cndmask_b32_e32 v2, v11, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v11, v8, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v11, v9, vcc
; GFX9-NEXT: v_cndmask_b32_e64 v1, v1, v17, s[4:5]
; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0 ; GFX9-NEXT: v_add_co_u32_e32 v0, vcc, 0, v0
; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc
; GFX9-NEXT: s_brev_b32 s4, 1 ; GFX9-NEXT: v_bfrev_b32_e32 v20, 1
; GFX9-NEXT: v_mov_b32_e32 v8, s4
; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v2, vcc, 0, v2, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v8, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v3, vcc, v3, v20, vcc
; GFX9-NEXT: v_and_b32_e32 v8, 1, v10 ; GFX9-NEXT: v_and_b32_e32 v8, 1, v10
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v8
; GFX9-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v0, v16, v0, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v1, v17, v1, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v2, v18, v2, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v3, v19, v3, vcc
; GFX9-NEXT: v_sub_co_u32_e32 v8, vcc, v4, v12 ; GFX9-NEXT: v_sub_co_u32_e32 v8, vcc, v4, v12
; GFX9-NEXT: v_subb_co_u32_e32 v9, vcc, v5, v13, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v9, vcc, v5, v13, vcc
; GFX9-NEXT: v_subb_co_u32_e32 v10, vcc, v6, v14, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v10, vcc, v6, v14, vcc
; GFX9-NEXT: v_subb_co_u32_e32 v11, vcc, v7, v15, vcc ; GFX9-NEXT: v_subb_co_u32_e32 v11, vcc, v7, v15, vcc
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5] ; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, v[8:9], v[4:5]
; GFX9-NEXT: s_cmp_lt_u32 s6, 64 ; GFX9-NEXT: s_cmp_lt_u32 s6, 64
; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7] ; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, v[10:11], v[6:7]
; GFX9-NEXT: s_cselect_b32 s5, 1, 0 ; GFX9-NEXT: s_cselect_b32 s4, 1, 0
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7] ; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, v[10:11], v[6:7]
; GFX9-NEXT: s_cmp_eq_u32 s6, 0 ; GFX9-NEXT: s_cmp_eq_u32 s6, 0
; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc
; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[12:13] ; GFX9-NEXT: v_cmp_lt_u64_e32 vcc, 0, v[12:13]
; GFX9-NEXT: s_cselect_b32 s9, 1, 0 ; GFX9-NEXT: s_cselect_b32 s5, 1, 0
; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[14:15] ; GFX9-NEXT: v_cmp_lt_i64_e32 vcc, 0, v[14:15]
; GFX9-NEXT: v_ashrrev_i64 v[12:13], s6, v[10:11] ; GFX9-NEXT: v_ashrrev_i64 v[12:13], s6, v[10:11]
; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; GFX9-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15] ; GFX9-NEXT: v_cmp_eq_u64_e32 vcc, 0, v[14:15]
; GFX9-NEXT: v_ashrrev_i32_e32 v15, 31, v11 ; GFX9-NEXT: s_and_b32 s5, 1, s5
; GFX9-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
; GFX9-NEXT: v_xor_b32_e32 v14, v5, v4 ; GFX9-NEXT: v_xor_b32_e32 v14, v5, v4
; GFX9-NEXT: v_lshrrev_b64 v[4:5], s6, v[8:9] ; GFX9-NEXT: v_lshrrev_b64 v[4:5], s6, v[8:9]
; GFX9-NEXT: v_lshlrev_b64 v[6:7], s8, v[10:11] ; GFX9-NEXT: v_lshlrev_b64 v[6:7], s8, v[10:11]
; GFX9-NEXT: s_and_b32 s6, 1, s5 ; GFX9-NEXT: s_and_b32 s6, 1, s4
; GFX9-NEXT: v_or_b32_e32 v6, v4, v6 ; GFX9-NEXT: v_or_b32_e32 v6, v4, v6
; GFX9-NEXT: v_or_b32_e32 v7, v5, v7 ; GFX9-NEXT: v_or_b32_e32 v7, v5, v7
; GFX9-NEXT: v_ashrrev_i64 v[4:5], s7, v[10:11] ; GFX9-NEXT: v_ashrrev_i64 v[4:5], s7, v[10:11]
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6 ; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6
; GFX9-NEXT: s_and_b32 s6, 1, s9
; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s6 ; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5
; GFX9-NEXT: s_and_b32 s5, 1, s5 ; GFX9-NEXT: s_and_b32 s4, 1, s4
; GFX9-NEXT: v_ashrrev_i32_e32 v15, 31, v11
; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, v4, v8, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v5, v5, v9, vcc
; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s5 ; GFX9-NEXT: v_cmp_ne_u32_e64 vcc, 0, s4
; GFX9-NEXT: v_cndmask_b32_e32 v6, v15, v12, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v6, v15, v12, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v7, v15, v13, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v7, v15, v13, vcc
; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 0, v4 ; GFX9-NEXT: v_add_co_u32_e32 v4, vcc, 0, v4
; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v5, vcc, 0, v5, vcc
; GFX9-NEXT: v_mov_b32_e32 v12, s4
; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v6, vcc, 0, v6, vcc
; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v12, vcc ; GFX9-NEXT: v_addc_co_u32_e32 v7, vcc, v7, v20, vcc
; GFX9-NEXT: v_and_b32_e32 v12, 1, v14 ; GFX9-NEXT: v_and_b32_e32 v12, 1, v14
; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12 ; GFX9-NEXT: v_cmp_ne_u32_e32 vcc, 0, v12
; GFX9-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v4, v8, v4, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v5, v9, v5, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v6, v10, v6, vcc
; GFX9-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc ; GFX9-NEXT: v_cndmask_b32_e32 v7, v11, v7, vcc
; GFX9-NEXT: s_setpc_b64 s[30:31] ; GFX9-NEXT: s_setpc_b64 s[30:31]
; ;
▲ Show 20 Lines • Show All 42 Lines • ▼ Show 20 Lines
; GFX10-NEXT: s_cselect_b32 s4, 1, 0 ; GFX10-NEXT: s_cselect_b32 s4, 1, 0
; GFX10-NEXT: s_and_b32 s8, 1, vcc_lo ; GFX10-NEXT: s_and_b32 s8, 1, vcc_lo
; GFX10-NEXT: s_and_b32 s4, 1, s4 ; GFX10-NEXT: s_and_b32 s4, 1, s4
; GFX10-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v9, v3, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v8, v2, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4 ; GFX10-NEXT: v_cmp_ne_u32_e64 vcc_lo, 0, s4
; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, s8 ; GFX10-NEXT: v_cmp_ne_u32_e64 s4, 0, s8
; GFX10-NEXT: v_xor_b32_e32 v9, v10, v20 ; GFX10-NEXT: v_xor_b32_e32 v9, v10, v20
; GFX10-NEXT: s_brev_b32 s8, 1
; GFX10-NEXT: s_cmp_lt_u32 s5, 64 ; GFX10-NEXT: s_cmp_lt_u32 s5, 64
; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v16, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v2, v2, v16, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v17, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v3, v17, vcc_lo
; GFX10-NEXT: v_cndmask_b32_e64 v0, v11, v0, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v0, v11, v0, s4
; GFX10-NEXT: v_cndmask_b32_e64 v1, v11, v1, s4 ; GFX10-NEXT: v_cndmask_b32_e64 v1, v11, v1, s4
; GFX10-NEXT: v_and_b32_e32 v8, 1, v9 ; GFX10-NEXT: v_and_b32_e32 v8, 1, v9
; GFX10-NEXT: v_add_co_u32_e64 v2, vcc_lo, v2, 0 ; GFX10-NEXT: v_add_co_u32_e64 v2, vcc_lo, v2, 0
; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v3, vcc_lo, 0, v3, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e32 v20, vcc_lo, 0, v0, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v20, vcc_lo, 0, v0, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e32 v21, vcc_lo, s8, v1, vcc_lo ; GFX10-NEXT: v_add_co_ci_u32_e32 v21, vcc_lo, 0x80000000, v1, vcc_lo
; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8 ; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v8
; GFX10-NEXT: v_sub_co_u32_e64 v8, s4, v26, v12 ; GFX10-NEXT: v_sub_co_u32_e64 v8, s4, v26, v12
; GFX10-NEXT: v_sub_co_ci_u32_e64 v9, s4, v27, v13, s4 ; GFX10-NEXT: v_sub_co_ci_u32_e64 v9, s4, v27, v13, s4
; GFX10-NEXT: v_sub_co_ci_u32_e64 v10, s4, v24, v14, s4 ; GFX10-NEXT: v_sub_co_ci_u32_e64 v10, s4, v24, v14, s4
; GFX10-NEXT: v_cndmask_b32_e32 v0, v16, v2, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v0, v16, v2, vcc_lo
; GFX10-NEXT: v_sub_co_ci_u32_e64 v11, s4, v25, v15, s4 ; GFX10-NEXT: v_sub_co_ci_u32_e64 v11, s4, v25, v15, s4
; GFX10-NEXT: v_cmp_lt_u64_e64 s4, v[8:9], v[26:27] ; GFX10-NEXT: v_cmp_lt_u64_e64 s4, v[8:9], v[26:27]
; GFX10-NEXT: v_cndmask_b32_e32 v1, v17, v3, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v1, v17, v3, vcc_lo
Show All 31 Lines
; GFX10-NEXT: v_and_b32_e32 v7, 1, v7 ; GFX10-NEXT: v_and_b32_e32 v7, 1, v7
; GFX10-NEXT: v_cndmask_b32_e64 v3, v18, v3, s5 ; GFX10-NEXT: v_cndmask_b32_e64 v3, v18, v3, s5
; GFX10-NEXT: v_cndmask_b32_e64 v4, v18, v4, s5 ; GFX10-NEXT: v_cndmask_b32_e64 v4, v18, v4, s5
; GFX10-NEXT: v_add_co_u32_e64 v5, s4, v5, 0 ; GFX10-NEXT: v_add_co_u32_e64 v5, s4, v5, 0
; GFX10-NEXT: v_add_co_ci_u32_e64 v6, s4, 0, v6, s4 ; GFX10-NEXT: v_add_co_ci_u32_e64 v6, s4, 0, v6, s4
; GFX10-NEXT: v_cmp_ne_u32_e64 s5, 0, v7 ; GFX10-NEXT: v_cmp_ne_u32_e64 s5, 0, v7
; GFX10-NEXT: v_add_co_ci_u32_e64 v7, s4, 0, v3, s4 ; GFX10-NEXT: v_add_co_ci_u32_e64 v7, s4, 0, v3, s4
; GFX10-NEXT: v_cndmask_b32_e32 v3, v19, v21, vcc_lo ; GFX10-NEXT: v_cndmask_b32_e32 v3, v19, v21, vcc_lo
; GFX10-NEXT: v_add_co_ci_u32_e64 v12, s4, s8, v4, s4 ; GFX10-NEXT: v_add_co_ci_u32_e64 v12, s4, 0x80000000, v4, s4
; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, v5, s5 ; GFX10-NEXT: v_cndmask_b32_e64 v4, v8, v5, s5
; GFX10-NEXT: v_cndmask_b32_e64 v5, v9, v6, s5 ; GFX10-NEXT: v_cndmask_b32_e64 v5, v9, v6, s5
; GFX10-NEXT: v_cndmask_b32_e64 v6, v10, v7, s5 ; GFX10-NEXT: v_cndmask_b32_e64 v6, v10, v7, s5
; GFX10-NEXT: v_cndmask_b32_e64 v7, v11, v12, s5 ; GFX10-NEXT: v_cndmask_b32_e64 v7, v11, v12, s5
; GFX10-NEXT: s_setpc_b64 s[30:31] ; GFX10-NEXT: s_setpc_b64 s[30:31]
%result = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs) %result = call <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128> %lhs, <2 x i128> %rhs)
ret <2 x i128> %result ret <2 x i128> %result
} }
▲ Show 20 Lines • Show All 731 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/udiv.i64.ll

Show First 20 Lines • Show All 956 Lines • ▼ Show 20 Lines; CGP-NEXT: s_setpc_b64 s[30:31]
%result = udiv <2 x i64> %num, %den %result = udiv <2 x i64> %num, %den
ret <2 x i64> %result ret <2 x i64> %result
} }
define i64 @v_udiv_i64_pow2k_denom(i64 %num) { define i64 @v_udiv_i64_pow2k_denom(i64 %num) {
; CHECK-LABEL: v_udiv_i64_pow2k_denom: ; CHECK-LABEL: v_udiv_i64_pow2k_denom:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_movk_i32 s6, 0x1000 ; CHECK-NEXT: v_cvt_f32_u32_e32 v2, 0x1000
; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v2, 0 ; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v3, 0
; CHECK-NEXT: s_mov_b32 s7, 0xfffff000 ; CHECK-NEXT: s_movk_i32 s6, 0xf000
; CHECK-NEXT: v_cvt_f32_u32_e32 v3, s6 ; CHECK-NEXT: s_movk_i32 s7, 0x1000
; CHECK-NEXT: v_mac_f32_e32 v3, 0x4f800000, v2 ; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v3 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 ; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
; CHECK-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 ; CHECK-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
; CHECK-NEXT: v_trunc_f32_e32 v3, v3 ; CHECK-NEXT: v_trunc_f32_e32 v3, v3
; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3 ; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3
; CHECK-NEXT: v_cvt_u32_f32_e32 v3, v3 ; CHECK-NEXT: v_cvt_u32_f32_e32 v3, v3
; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2 ; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
; CHECK-NEXT: v_mul_lo_u32 v4, s7, v3 ; CHECK-NEXT: v_mul_lo_u32 v4, s6, v3
; CHECK-NEXT: v_mul_lo_u32 v5, s7, v2 ; CHECK-NEXT: v_mul_lo_u32 v5, s6, v2
; CHECK-NEXT: v_mul_lo_u32 v6, -1, v2 ; CHECK-NEXT: v_mul_lo_u32 v6, -1, v2
; CHECK-NEXT: v_mul_hi_u32 v7, s7, v2 ; CHECK-NEXT: v_mul_hi_u32 v7, s6, v2
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; CHECK-NEXT: v_mul_lo_u32 v6, v3, v5 ; CHECK-NEXT: v_mul_lo_u32 v6, v3, v5
; CHECK-NEXT: v_mul_hi_u32 v8, v2, v5 ; CHECK-NEXT: v_mul_hi_u32 v8, v2, v5
; CHECK-NEXT: v_mul_hi_u32 v5, v3, v5 ; CHECK-NEXT: v_mul_hi_u32 v5, v3, v5
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v7 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v7
; CHECK-NEXT: v_mul_lo_u32 v7, v2, v4 ; CHECK-NEXT: v_mul_lo_u32 v7, v2, v4
; CHECK-NEXT: v_mul_lo_u32 v9, v3, v4 ; CHECK-NEXT: v_mul_lo_u32 v9, v3, v4
; CHECK-NEXT: v_mul_hi_u32 v10, v2, v4 ; CHECK-NEXT: v_mul_hi_u32 v10, v2, v4
Show All 10 Lines
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v8 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v8
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v5 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; CHECK-NEXT: v_addc_u32_e64 v5, s[4:5], v3, v4, vcc ; CHECK-NEXT: v_addc_u32_e64 v5, s[4:5], v3, v4, vcc
; CHECK-NEXT: v_add_i32_e64 v3, s[4:5], v3, v4 ; CHECK-NEXT: v_add_i32_e64 v3, s[4:5], v3, v4
; CHECK-NEXT: v_mul_lo_u32 v4, s7, v2 ; CHECK-NEXT: v_mul_lo_u32 v4, s6, v2
; CHECK-NEXT: v_mul_lo_u32 v6, -1, v2 ; CHECK-NEXT: v_mul_lo_u32 v6, -1, v2
; CHECK-NEXT: v_mul_hi_u32 v7, s7, v2 ; CHECK-NEXT: v_mul_hi_u32 v7, s6, v2
; CHECK-NEXT: v_mul_lo_u32 v8, s7, v5 ; CHECK-NEXT: v_mul_lo_u32 v8, s6, v5
; CHECK-NEXT: v_mul_lo_u32 v9, v5, v4 ; CHECK-NEXT: v_mul_lo_u32 v9, v5, v4
; CHECK-NEXT: v_mul_hi_u32 v10, v2, v4 ; CHECK-NEXT: v_mul_hi_u32 v10, v2, v4
; CHECK-NEXT: v_mul_hi_u32 v4, v5, v4 ; CHECK-NEXT: v_mul_hi_u32 v4, v5, v4
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v8 ; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v8
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v7 ; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v7
; CHECK-NEXT: v_mul_lo_u32 v7, v2, v6 ; CHECK-NEXT: v_mul_lo_u32 v7, v2, v6
; CHECK-NEXT: v_mul_lo_u32 v8, v5, v6 ; CHECK-NEXT: v_mul_lo_u32 v8, v5, v6
; CHECK-NEXT: v_mul_hi_u32 v11, v2, v6 ; CHECK-NEXT: v_mul_hi_u32 v11, v2, v6
Show All 30 Lines
; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v7, v5 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v7, v5
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; CHECK-NEXT: v_mul_lo_u32 v5, s6, v2 ; CHECK-NEXT: v_mul_lo_u32 v5, s7, v2
; CHECK-NEXT: v_mul_lo_u32 v6, 0, v2 ; CHECK-NEXT: v_mul_lo_u32 v6, 0, v2
; CHECK-NEXT: v_mul_hi_u32 v7, s6, v2 ; CHECK-NEXT: v_mul_hi_u32 v7, s7, v2
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v4 ; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; CHECK-NEXT: v_mul_lo_u32 v4, s6, v3 ; CHECK-NEXT: v_mul_lo_u32 v4, s7, v3
; CHECK-NEXT: v_add_i32_e32 v8, vcc, 1, v2 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, 1, v2
; CHECK-NEXT: v_addc_u32_e32 v9, vcc, 0, v3, vcc ; CHECK-NEXT: v_addc_u32_e32 v9, vcc, 0, v3, vcc
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; CHECK-NEXT: v_add_i32_e32 v6, vcc, 1, v8 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, 1, v8
; CHECK-NEXT: v_addc_u32_e32 v10, vcc, 0, v9, vcc ; CHECK-NEXT: v_addc_u32_e32 v10, vcc, 0, v9, vcc
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v7 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v7
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v5 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v5
; CHECK-NEXT: v_subb_u32_e64 v5, s[4:5], v1, v4, vcc ; CHECK-NEXT: v_subb_u32_e64 v5, s[4:5], v1, v4, vcc
; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v4 ; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v4
; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v0 ; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v0
; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5]
; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v5 ; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v5
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5 ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
; CHECK-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc
; CHECK-NEXT: v_subrev_i32_e32 v0, vcc, s6, v0 ; CHECK-NEXT: v_subrev_i32_e32 v0, vcc, s7, v0
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v0 ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s7, v0
; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, 0, v1 ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, 0, v1
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; CHECK-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v8, v6, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v8, v6, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
▲ Show 20 Lines • Show All 269 Lines • ▼ Show 20 Lines
; GISEL-NEXT: v_cndmask_b32_e64 v0, v5, v0, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v0, v5, v0, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v1, v7, v1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v1, v7, v1, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
; GISEL-NEXT: s_setpc_b64 s[30:31] ; GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; CGP-LABEL: v_udiv_v2i64_pow2k_denom: ; CGP-LABEL: v_udiv_v2i64_pow2k_denom:
; CGP: ; %bb.0: ; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CGP-NEXT: v_cvt_f32_u32_e32 v4, 0x1000
; CGP-NEXT: v_cvt_f32_ubyte0_e32 v5, 0
; CGP-NEXT: s_movk_i32 s8, 0xf000
; CGP-NEXT: s_movk_i32 s10, 0x1000 ; CGP-NEXT: s_movk_i32 s10, 0x1000
; CGP-NEXT: v_cvt_f32_ubyte0_e32 v4, 0 ; CGP-NEXT: v_mov_b32_e32 v6, v4
; CGP-NEXT: v_cvt_f32_u32_e32 v5, s10 ; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
; CGP-NEXT: s_mov_b32 s8, 0xfffff000 ; CGP-NEXT: v_mac_f32_e32 v6, 0x4f800000, v5
; CGP-NEXT: v_mov_b32_e32 v6, v5 ; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4
; CGP-NEXT: v_mac_f32_e32 v5, 0x4f800000, v4
; CGP-NEXT: v_mac_f32_e32 v6, 0x4f800000, v4
; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v5
; CGP-NEXT: v_rcp_iflag_f32_e32 v5, v6 ; CGP-NEXT: v_rcp_iflag_f32_e32 v5, v6
; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
; CGP-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5 ; CGP-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5
; CGP-NEXT: v_mul_f32_e32 v6, 0x2f800000, v4 ; CGP-NEXT: v_mul_f32_e32 v6, 0x2f800000, v4
; CGP-NEXT: v_mul_f32_e32 v7, 0x2f800000, v5 ; CGP-NEXT: v_mul_f32_e32 v7, 0x2f800000, v5
; CGP-NEXT: v_trunc_f32_e32 v6, v6 ; CGP-NEXT: v_trunc_f32_e32 v6, v6
; CGP-NEXT: v_trunc_f32_e32 v7, v7 ; CGP-NEXT: v_trunc_f32_e32 v7, v7
; CGP-NEXT: v_mac_f32_e32 v4, 0xcf800000, v6 ; CGP-NEXT: v_mac_f32_e32 v4, 0xcf800000, v6
▲ Show 20 Lines • Show All 236 Lines • ▼ Show 20 Lines; CGP-NEXT: s_setpc_b64 s[30:31]
%result = udiv <2 x i64> %num, <i64 4096, i64 4096> %result = udiv <2 x i64> %num, <i64 4096, i64 4096>
ret <2 x i64> %result ret <2 x i64> %result
} }
define i64 @v_udiv_i64_oddk_denom(i64 %num) { define i64 @v_udiv_i64_oddk_denom(i64 %num) {
; CHECK-LABEL: v_udiv_i64_oddk_denom: ; CHECK-LABEL: v_udiv_i64_oddk_denom:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_mov_b32 s6, 0x12d8fb ; CHECK-NEXT: v_cvt_f32_u32_e32 v2, 0x12d8fb
; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v2, 0 ; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v3, 0
; CHECK-NEXT: s_mov_b32 s7, 0xffed2705 ; CHECK-NEXT: s_mov_b32 s6, 0xffed2705
; CHECK-NEXT: v_cvt_f32_u32_e32 v3, s6 ; CHECK-NEXT: s_mov_b32 s7, 0x12d8fb
; CHECK-NEXT: v_mac_f32_e32 v3, 0x4f800000, v2 ; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v3 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 ; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
; CHECK-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 ; CHECK-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
; CHECK-NEXT: v_trunc_f32_e32 v3, v3 ; CHECK-NEXT: v_trunc_f32_e32 v3, v3
; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3 ; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3
; CHECK-NEXT: v_cvt_u32_f32_e32 v3, v3 ; CHECK-NEXT: v_cvt_u32_f32_e32 v3, v3
; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2 ; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
; CHECK-NEXT: v_mul_lo_u32 v4, s7, v3 ; CHECK-NEXT: v_mul_lo_u32 v4, s6, v3
; CHECK-NEXT: v_mul_lo_u32 v5, s7, v2 ; CHECK-NEXT: v_mul_lo_u32 v5, s6, v2
; CHECK-NEXT: v_mul_lo_u32 v6, -1, v2 ; CHECK-NEXT: v_mul_lo_u32 v6, -1, v2
; CHECK-NEXT: v_mul_hi_u32 v7, s7, v2 ; CHECK-NEXT: v_mul_hi_u32 v7, s6, v2
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; CHECK-NEXT: v_mul_lo_u32 v6, v3, v5 ; CHECK-NEXT: v_mul_lo_u32 v6, v3, v5
; CHECK-NEXT: v_mul_hi_u32 v8, v2, v5 ; CHECK-NEXT: v_mul_hi_u32 v8, v2, v5
; CHECK-NEXT: v_mul_hi_u32 v5, v3, v5 ; CHECK-NEXT: v_mul_hi_u32 v5, v3, v5
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v7 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v7
; CHECK-NEXT: v_mul_lo_u32 v7, v2, v4 ; CHECK-NEXT: v_mul_lo_u32 v7, v2, v4
; CHECK-NEXT: v_mul_lo_u32 v9, v3, v4 ; CHECK-NEXT: v_mul_lo_u32 v9, v3, v4
; CHECK-NEXT: v_mul_hi_u32 v10, v2, v4 ; CHECK-NEXT: v_mul_hi_u32 v10, v2, v4
Show All 10 Lines
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v8 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v8
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v5 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; CHECK-NEXT: v_addc_u32_e64 v5, s[4:5], v3, v4, vcc ; CHECK-NEXT: v_addc_u32_e64 v5, s[4:5], v3, v4, vcc
; CHECK-NEXT: v_add_i32_e64 v3, s[4:5], v3, v4 ; CHECK-NEXT: v_add_i32_e64 v3, s[4:5], v3, v4
; CHECK-NEXT: v_mul_lo_u32 v4, s7, v2 ; CHECK-NEXT: v_mul_lo_u32 v4, s6, v2
; CHECK-NEXT: v_mul_lo_u32 v6, -1, v2 ; CHECK-NEXT: v_mul_lo_u32 v6, -1, v2
; CHECK-NEXT: v_mul_hi_u32 v7, s7, v2 ; CHECK-NEXT: v_mul_hi_u32 v7, s6, v2
; CHECK-NEXT: v_mul_lo_u32 v8, s7, v5 ; CHECK-NEXT: v_mul_lo_u32 v8, s6, v5
; CHECK-NEXT: v_mul_lo_u32 v9, v5, v4 ; CHECK-NEXT: v_mul_lo_u32 v9, v5, v4
; CHECK-NEXT: v_mul_hi_u32 v10, v2, v4 ; CHECK-NEXT: v_mul_hi_u32 v10, v2, v4
; CHECK-NEXT: v_mul_hi_u32 v4, v5, v4 ; CHECK-NEXT: v_mul_hi_u32 v4, v5, v4
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v8 ; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v8
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v7 ; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v7
; CHECK-NEXT: v_mul_lo_u32 v7, v2, v6 ; CHECK-NEXT: v_mul_lo_u32 v7, v2, v6
; CHECK-NEXT: v_mul_lo_u32 v8, v5, v6 ; CHECK-NEXT: v_mul_lo_u32 v8, v5, v6
; CHECK-NEXT: v_mul_hi_u32 v11, v2, v6 ; CHECK-NEXT: v_mul_hi_u32 v11, v2, v6
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; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v7, v5 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v7, v5
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; CHECK-NEXT: v_mul_lo_u32 v5, s6, v2 ; CHECK-NEXT: v_mul_lo_u32 v5, s7, v2
; CHECK-NEXT: v_mul_lo_u32 v6, 0, v2 ; CHECK-NEXT: v_mul_lo_u32 v6, 0, v2
; CHECK-NEXT: v_mul_hi_u32 v7, s6, v2 ; CHECK-NEXT: v_mul_hi_u32 v7, s7, v2
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v4 ; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; CHECK-NEXT: v_mul_lo_u32 v4, s6, v3 ; CHECK-NEXT: v_mul_lo_u32 v4, s7, v3
; CHECK-NEXT: v_add_i32_e32 v8, vcc, 1, v2 ; CHECK-NEXT: v_add_i32_e32 v8, vcc, 1, v2
; CHECK-NEXT: v_addc_u32_e32 v9, vcc, 0, v3, vcc ; CHECK-NEXT: v_addc_u32_e32 v9, vcc, 0, v3, vcc
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; CHECK-NEXT: v_add_i32_e32 v6, vcc, 1, v8 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, 1, v8
; CHECK-NEXT: v_addc_u32_e32 v10, vcc, 0, v9, vcc ; CHECK-NEXT: v_addc_u32_e32 v10, vcc, 0, v9, vcc
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v7 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v7
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v5 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v5
; CHECK-NEXT: v_subb_u32_e64 v5, s[4:5], v1, v4, vcc ; CHECK-NEXT: v_subb_u32_e64 v5, s[4:5], v1, v4, vcc
; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v4 ; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v4
; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v0 ; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v0
; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5]
; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v5 ; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v5
; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v7, 0, -1, s[4:5]
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5 ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v5
; CHECK-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v4, v7, v4, vcc
; CHECK-NEXT: v_subrev_i32_e32 v0, vcc, s6, v0 ; CHECK-NEXT: v_subrev_i32_e32 v0, vcc, s7, v0
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v0 ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s7, v0
; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v0, 0, -1, vcc
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, 0, v1 ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, 0, v1
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; CHECK-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v5, v0, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v0
; CHECK-NEXT: v_cndmask_b32_e32 v0, v8, v6, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v8, v6, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v9, v10, vcc
▲ Show 20 Lines • Show All 269 Lines • ▼ Show 20 Lines
; GISEL-NEXT: v_cndmask_b32_e64 v0, v5, v0, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v0, v5, v0, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v1, v7, v1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v1, v7, v1, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
; GISEL-NEXT: s_setpc_b64 s[30:31] ; GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; CGP-LABEL: v_udiv_v2i64_oddk_denom: ; CGP-LABEL: v_udiv_v2i64_oddk_denom:
; CGP: ; %bb.0: ; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CGP-NEXT: s_mov_b32 s10, 0x12d8fb ; CGP-NEXT: v_cvt_f32_u32_e32 v4, 0x12d8fb
; CGP-NEXT: v_cvt_f32_ubyte0_e32 v4, 0 ; CGP-NEXT: v_cvt_f32_ubyte0_e32 v5, 0
; CGP-NEXT: v_cvt_f32_u32_e32 v5, s10
; CGP-NEXT: s_mov_b32 s8, 0xffed2705 ; CGP-NEXT: s_mov_b32 s8, 0xffed2705
; CGP-NEXT: v_mov_b32_e32 v6, v5 ; CGP-NEXT: s_mov_b32 s10, 0x12d8fb
; CGP-NEXT: v_mac_f32_e32 v5, 0x4f800000, v4 ; CGP-NEXT: v_mov_b32_e32 v6, v4
; CGP-NEXT: v_mac_f32_e32 v6, 0x4f800000, v4 ; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v5 ; CGP-NEXT: v_mac_f32_e32 v6, 0x4f800000, v5
; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4
; CGP-NEXT: v_rcp_iflag_f32_e32 v5, v6 ; CGP-NEXT: v_rcp_iflag_f32_e32 v5, v6
; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
; CGP-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5 ; CGP-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5
; CGP-NEXT: v_mul_f32_e32 v6, 0x2f800000, v4 ; CGP-NEXT: v_mul_f32_e32 v6, 0x2f800000, v4
; CGP-NEXT: v_mul_f32_e32 v7, 0x2f800000, v5 ; CGP-NEXT: v_mul_f32_e32 v7, 0x2f800000, v5
; CGP-NEXT: v_trunc_f32_e32 v6, v6 ; CGP-NEXT: v_trunc_f32_e32 v6, v6
; CGP-NEXT: v_trunc_f32_e32 v7, v7 ; CGP-NEXT: v_trunc_f32_e32 v7, v7
; CGP-NEXT: v_mac_f32_e32 v4, 0xcf800000, v6 ; CGP-NEXT: v_mac_f32_e32 v4, 0xcf800000, v6
▲ Show 20 Lines • Show All 1,378 Lines • Show Last 20 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/urem.i64.ll

Show First 20 Lines • Show All 942 Lines • ▼ Show 20 Lines; CGP-NEXT: s_setpc_b64 s[30:31]
%result = urem <2 x i64> %num, %den %result = urem <2 x i64> %num, %den
ret <2 x i64> %result ret <2 x i64> %result
} }
define i64 @v_urem_i64_pow2k_denom(i64 %num) { define i64 @v_urem_i64_pow2k_denom(i64 %num) {
; CHECK-LABEL: v_urem_i64_pow2k_denom: ; CHECK-LABEL: v_urem_i64_pow2k_denom:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_movk_i32 s6, 0x1000 ; CHECK-NEXT: v_cvt_f32_u32_e32 v2, 0x1000
; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v2, 0 ; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v3, 0
; CHECK-NEXT: s_mov_b32 s7, 0xfffff000 ; CHECK-NEXT: s_movk_i32 s6, 0xf000
; CHECK-NEXT: v_cvt_f32_u32_e32 v3, s6 ; CHECK-NEXT: s_movk_i32 s7, 0x1000
; CHECK-NEXT: v_mac_f32_e32 v3, 0x4f800000, v2 ; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v3 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 ; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
; CHECK-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 ; CHECK-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
; CHECK-NEXT: v_trunc_f32_e32 v3, v3 ; CHECK-NEXT: v_trunc_f32_e32 v3, v3
; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3 ; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3
; CHECK-NEXT: v_cvt_u32_f32_e32 v3, v3 ; CHECK-NEXT: v_cvt_u32_f32_e32 v3, v3
; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2 ; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
; CHECK-NEXT: v_mul_lo_u32 v4, s7, v3 ; CHECK-NEXT: v_mul_lo_u32 v4, s6, v3
; CHECK-NEXT: v_mul_lo_u32 v5, s7, v2 ; CHECK-NEXT: v_mul_lo_u32 v5, s6, v2
; CHECK-NEXT: v_mul_lo_u32 v6, -1, v2 ; CHECK-NEXT: v_mul_lo_u32 v6, -1, v2
; CHECK-NEXT: v_mul_hi_u32 v7, s7, v2 ; CHECK-NEXT: v_mul_hi_u32 v7, s6, v2
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; CHECK-NEXT: v_mul_lo_u32 v6, v3, v5 ; CHECK-NEXT: v_mul_lo_u32 v6, v3, v5
; CHECK-NEXT: v_mul_hi_u32 v8, v2, v5 ; CHECK-NEXT: v_mul_hi_u32 v8, v2, v5
; CHECK-NEXT: v_mul_hi_u32 v5, v3, v5 ; CHECK-NEXT: v_mul_hi_u32 v5, v3, v5
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v7 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v7
; CHECK-NEXT: v_mul_lo_u32 v7, v2, v4 ; CHECK-NEXT: v_mul_lo_u32 v7, v2, v4
; CHECK-NEXT: v_mul_lo_u32 v9, v3, v4 ; CHECK-NEXT: v_mul_lo_u32 v9, v3, v4
; CHECK-NEXT: v_mul_hi_u32 v10, v2, v4 ; CHECK-NEXT: v_mul_hi_u32 v10, v2, v4
Show All 10 Lines
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v8 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v8
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v5 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; CHECK-NEXT: v_addc_u32_e64 v5, s[4:5], v3, v4, vcc ; CHECK-NEXT: v_addc_u32_e64 v5, s[4:5], v3, v4, vcc
; CHECK-NEXT: v_add_i32_e64 v3, s[4:5], v3, v4 ; CHECK-NEXT: v_add_i32_e64 v3, s[4:5], v3, v4
; CHECK-NEXT: v_mul_lo_u32 v4, s7, v2 ; CHECK-NEXT: v_mul_lo_u32 v4, s6, v2
; CHECK-NEXT: v_mul_lo_u32 v6, -1, v2 ; CHECK-NEXT: v_mul_lo_u32 v6, -1, v2
; CHECK-NEXT: v_mul_hi_u32 v7, s7, v2 ; CHECK-NEXT: v_mul_hi_u32 v7, s6, v2
; CHECK-NEXT: v_mul_lo_u32 v8, s7, v5 ; CHECK-NEXT: v_mul_lo_u32 v8, s6, v5
; CHECK-NEXT: v_mul_lo_u32 v9, v5, v4 ; CHECK-NEXT: v_mul_lo_u32 v9, v5, v4
; CHECK-NEXT: v_mul_hi_u32 v10, v2, v4 ; CHECK-NEXT: v_mul_hi_u32 v10, v2, v4
; CHECK-NEXT: v_mul_hi_u32 v4, v5, v4 ; CHECK-NEXT: v_mul_hi_u32 v4, v5, v4
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v8 ; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v8
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v7 ; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v7
; CHECK-NEXT: v_mul_lo_u32 v7, v2, v6 ; CHECK-NEXT: v_mul_lo_u32 v7, v2, v6
; CHECK-NEXT: v_mul_lo_u32 v8, v5, v6 ; CHECK-NEXT: v_mul_lo_u32 v8, v5, v6
; CHECK-NEXT: v_mul_hi_u32 v11, v2, v6 ; CHECK-NEXT: v_mul_hi_u32 v11, v2, v6
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; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v7, v5 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v7, v5
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; CHECK-NEXT: v_mul_lo_u32 v5, s6, v2 ; CHECK-NEXT: v_mul_lo_u32 v5, s7, v2
; CHECK-NEXT: v_mul_lo_u32 v6, 0, v2 ; CHECK-NEXT: v_mul_lo_u32 v6, 0, v2
; CHECK-NEXT: v_mul_hi_u32 v2, s6, v2 ; CHECK-NEXT: v_mul_hi_u32 v2, s7, v2
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v4 ; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; CHECK-NEXT: v_mul_lo_u32 v3, s6, v3 ; CHECK-NEXT: v_mul_lo_u32 v3, s7, v3
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v6, v3 ; CHECK-NEXT: v_add_i32_e32 v3, vcc, v6, v3
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v5 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v5
; CHECK-NEXT: v_subb_u32_e64 v3, s[4:5], v1, v2, vcc ; CHECK-NEXT: v_subb_u32_e64 v3, s[4:5], v1, v2, vcc
; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v2 ; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v2
; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v0 ; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v0
; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, -1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, -1, s[4:5]
; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v3 ; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v3
; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5]
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; CHECK-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; CHECK-NEXT: v_subrev_i32_e32 v4, vcc, s6, v0 ; CHECK-NEXT: v_subrev_i32_e32 v4, vcc, s7, v0
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v4 ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s7, v4
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, 0, v1 ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, 0, v1
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; CHECK-NEXT: v_subrev_i32_e32 v7, vcc, s6, v4 ; CHECK-NEXT: v_subrev_i32_e32 v7, vcc, s7, v4
; CHECK-NEXT: v_subbrev_u32_e32 v8, vcc, 0, v1, vcc ; CHECK-NEXT: v_subbrev_u32_e32 v8, vcc, 0, v1, vcc
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; CHECK-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
▲ Show 20 Lines • Show All 263 Lines • ▼ Show 20 Lines
; GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v9, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v9, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v1, v7, v1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v1, v7, v1, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
; GISEL-NEXT: s_setpc_b64 s[30:31] ; GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; CGP-LABEL: v_urem_v2i64_pow2k_denom: ; CGP-LABEL: v_urem_v2i64_pow2k_denom:
; CGP: ; %bb.0: ; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CGP-NEXT: v_cvt_f32_u32_e32 v4, 0x1000
; CGP-NEXT: v_cvt_f32_ubyte0_e32 v5, 0
; CGP-NEXT: s_movk_i32 s8, 0xf000
; CGP-NEXT: s_movk_i32 s10, 0x1000 ; CGP-NEXT: s_movk_i32 s10, 0x1000
; CGP-NEXT: v_cvt_f32_ubyte0_e32 v4, 0 ; CGP-NEXT: v_mov_b32_e32 v6, v4
; CGP-NEXT: v_cvt_f32_u32_e32 v5, s10 ; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
; CGP-NEXT: s_mov_b32 s8, 0xfffff000 ; CGP-NEXT: v_mac_f32_e32 v6, 0x4f800000, v5
; CGP-NEXT: v_mov_b32_e32 v6, v5 ; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4
; CGP-NEXT: v_mac_f32_e32 v5, 0x4f800000, v4
; CGP-NEXT: v_mac_f32_e32 v6, 0x4f800000, v4
; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v5
; CGP-NEXT: v_rcp_iflag_f32_e32 v5, v6 ; CGP-NEXT: v_rcp_iflag_f32_e32 v5, v6
; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
; CGP-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5 ; CGP-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5
; CGP-NEXT: v_mul_f32_e32 v6, 0x2f800000, v4 ; CGP-NEXT: v_mul_f32_e32 v6, 0x2f800000, v4
; CGP-NEXT: v_mul_f32_e32 v7, 0x2f800000, v5 ; CGP-NEXT: v_mul_f32_e32 v7, 0x2f800000, v5
; CGP-NEXT: v_trunc_f32_e32 v6, v6 ; CGP-NEXT: v_trunc_f32_e32 v6, v6
; CGP-NEXT: v_trunc_f32_e32 v7, v7 ; CGP-NEXT: v_trunc_f32_e32 v7, v7
; CGP-NEXT: v_mac_f32_e32 v4, 0xcf800000, v6 ; CGP-NEXT: v_mac_f32_e32 v4, 0xcf800000, v6
▲ Show 20 Lines • Show All 232 Lines • ▼ Show 20 Lines; CGP-NEXT: s_setpc_b64 s[30:31]
%result = urem <2 x i64> %num, <i64 4096, i64 4096> %result = urem <2 x i64> %num, <i64 4096, i64 4096>
ret <2 x i64> %result ret <2 x i64> %result
} }
define i64 @v_urem_i64_oddk_denom(i64 %num) { define i64 @v_urem_i64_oddk_denom(i64 %num) {
; CHECK-LABEL: v_urem_i64_oddk_denom: ; CHECK-LABEL: v_urem_i64_oddk_denom:
; CHECK: ; %bb.0: ; CHECK: ; %bb.0:
; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CHECK-NEXT: s_mov_b32 s6, 0x12d8fb ; CHECK-NEXT: v_cvt_f32_u32_e32 v2, 0x12d8fb
; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v2, 0 ; CHECK-NEXT: v_cvt_f32_ubyte0_e32 v3, 0
; CHECK-NEXT: s_mov_b32 s7, 0xffed2705 ; CHECK-NEXT: s_mov_b32 s6, 0xffed2705
; CHECK-NEXT: v_cvt_f32_u32_e32 v3, s6 ; CHECK-NEXT: s_mov_b32 s7, 0x12d8fb
; CHECK-NEXT: v_mac_f32_e32 v3, 0x4f800000, v2 ; CHECK-NEXT: v_mac_f32_e32 v2, 0x4f800000, v3
; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v3 ; CHECK-NEXT: v_rcp_iflag_f32_e32 v2, v2
; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2 ; CHECK-NEXT: v_mul_f32_e32 v2, 0x5f7ffffc, v2
; CHECK-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2 ; CHECK-NEXT: v_mul_f32_e32 v3, 0x2f800000, v2
; CHECK-NEXT: v_trunc_f32_e32 v3, v3 ; CHECK-NEXT: v_trunc_f32_e32 v3, v3
; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3 ; CHECK-NEXT: v_mac_f32_e32 v2, 0xcf800000, v3
; CHECK-NEXT: v_cvt_u32_f32_e32 v3, v3 ; CHECK-NEXT: v_cvt_u32_f32_e32 v3, v3
; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2 ; CHECK-NEXT: v_cvt_u32_f32_e32 v2, v2
; CHECK-NEXT: v_mul_lo_u32 v4, s7, v3 ; CHECK-NEXT: v_mul_lo_u32 v4, s6, v3
; CHECK-NEXT: v_mul_lo_u32 v5, s7, v2 ; CHECK-NEXT: v_mul_lo_u32 v5, s6, v2
; CHECK-NEXT: v_mul_lo_u32 v6, -1, v2 ; CHECK-NEXT: v_mul_lo_u32 v6, -1, v2
; CHECK-NEXT: v_mul_hi_u32 v7, s7, v2 ; CHECK-NEXT: v_mul_hi_u32 v7, s6, v2
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; CHECK-NEXT: v_mul_lo_u32 v6, v3, v5 ; CHECK-NEXT: v_mul_lo_u32 v6, v3, v5
; CHECK-NEXT: v_mul_hi_u32 v8, v2, v5 ; CHECK-NEXT: v_mul_hi_u32 v8, v2, v5
; CHECK-NEXT: v_mul_hi_u32 v5, v3, v5 ; CHECK-NEXT: v_mul_hi_u32 v5, v3, v5
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v7 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v7
; CHECK-NEXT: v_mul_lo_u32 v7, v2, v4 ; CHECK-NEXT: v_mul_lo_u32 v7, v2, v4
; CHECK-NEXT: v_mul_lo_u32 v9, v3, v4 ; CHECK-NEXT: v_mul_lo_u32 v9, v3, v4
; CHECK-NEXT: v_mul_hi_u32 v10, v2, v4 ; CHECK-NEXT: v_mul_hi_u32 v10, v2, v4
Show All 10 Lines
; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v8 ; CHECK-NEXT: v_add_i32_e32 v7, vcc, v9, v8
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v5, v6
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6 ; CHECK-NEXT: v_add_i32_e32 v6, vcc, v7, v6
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v6 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v4, v6
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v5 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v5
; CHECK-NEXT: v_addc_u32_e64 v5, s[4:5], v3, v4, vcc ; CHECK-NEXT: v_addc_u32_e64 v5, s[4:5], v3, v4, vcc
; CHECK-NEXT: v_add_i32_e64 v3, s[4:5], v3, v4 ; CHECK-NEXT: v_add_i32_e64 v3, s[4:5], v3, v4
; CHECK-NEXT: v_mul_lo_u32 v4, s7, v2 ; CHECK-NEXT: v_mul_lo_u32 v4, s6, v2
; CHECK-NEXT: v_mul_lo_u32 v6, -1, v2 ; CHECK-NEXT: v_mul_lo_u32 v6, -1, v2
; CHECK-NEXT: v_mul_hi_u32 v7, s7, v2 ; CHECK-NEXT: v_mul_hi_u32 v7, s6, v2
; CHECK-NEXT: v_mul_lo_u32 v8, s7, v5 ; CHECK-NEXT: v_mul_lo_u32 v8, s6, v5
; CHECK-NEXT: v_mul_lo_u32 v9, v5, v4 ; CHECK-NEXT: v_mul_lo_u32 v9, v5, v4
; CHECK-NEXT: v_mul_hi_u32 v10, v2, v4 ; CHECK-NEXT: v_mul_hi_u32 v10, v2, v4
; CHECK-NEXT: v_mul_hi_u32 v4, v5, v4 ; CHECK-NEXT: v_mul_hi_u32 v4, v5, v4
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v8 ; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v8
; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v7 ; CHECK-NEXT: v_add_i32_e64 v6, s[4:5], v6, v7
; CHECK-NEXT: v_mul_lo_u32 v7, v2, v6 ; CHECK-NEXT: v_mul_lo_u32 v7, v2, v6
; CHECK-NEXT: v_mul_lo_u32 v8, v5, v6 ; CHECK-NEXT: v_mul_lo_u32 v8, v5, v6
; CHECK-NEXT: v_mul_hi_u32 v11, v2, v6 ; CHECK-NEXT: v_mul_hi_u32 v11, v2, v6
Show All 30 Lines
; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v8
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v6, v4
; CHECK-NEXT: v_add_i32_e32 v5, vcc, v7, v5 ; CHECK-NEXT: v_add_i32_e32 v5, vcc, v7, v5
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v4 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v2, v4
; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, 1, vcc
; CHECK-NEXT: v_add_i32_e32 v4, vcc, v5, v4 ; CHECK-NEXT: v_add_i32_e32 v4, vcc, v5, v4
; CHECK-NEXT: v_mul_lo_u32 v5, s6, v2 ; CHECK-NEXT: v_mul_lo_u32 v5, s7, v2
; CHECK-NEXT: v_mul_lo_u32 v6, 0, v2 ; CHECK-NEXT: v_mul_lo_u32 v6, 0, v2
; CHECK-NEXT: v_mul_hi_u32 v2, s6, v2 ; CHECK-NEXT: v_mul_hi_u32 v2, s7, v2
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v4 ; CHECK-NEXT: v_add_i32_e32 v3, vcc, v3, v4
; CHECK-NEXT: v_mul_lo_u32 v3, s6, v3 ; CHECK-NEXT: v_mul_lo_u32 v3, s7, v3
; CHECK-NEXT: v_add_i32_e32 v3, vcc, v6, v3 ; CHECK-NEXT: v_add_i32_e32 v3, vcc, v6, v3
; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2 ; CHECK-NEXT: v_add_i32_e32 v2, vcc, v3, v2
; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v5 ; CHECK-NEXT: v_sub_i32_e32 v0, vcc, v0, v5
; CHECK-NEXT: v_subb_u32_e64 v3, s[4:5], v1, v2, vcc ; CHECK-NEXT: v_subb_u32_e64 v3, s[4:5], v1, v2, vcc
; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v2 ; CHECK-NEXT: v_sub_i32_e64 v1, s[4:5], v1, v2
; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s6, v0 ; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], s7, v0
; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, -1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v2, 0, -1, s[4:5]
; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v3 ; CHECK-NEXT: v_cmp_le_u32_e64 s[4:5], 0, v3
; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5] ; CHECK-NEXT: v_cndmask_b32_e64 v4, 0, -1, s[4:5]
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3 ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v3
; CHECK-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v2, v4, v2, vcc
; CHECK-NEXT: v_subrev_i32_e32 v4, vcc, s6, v0 ; CHECK-NEXT: v_subrev_i32_e32 v4, vcc, s7, v0
; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc ; CHECK-NEXT: v_subbrev_u32_e32 v1, vcc, 0, v1, vcc
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s6, v4 ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, s7, v4
; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v5, 0, -1, vcc
; CHECK-NEXT: v_cmp_le_u32_e32 vcc, 0, v1 ; CHECK-NEXT: v_cmp_le_u32_e32 vcc, 0, v1
; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc ; CHECK-NEXT: v_cndmask_b32_e64 v6, 0, -1, vcc
; CHECK-NEXT: v_subrev_i32_e32 v7, vcc, s6, v4 ; CHECK-NEXT: v_subrev_i32_e32 v7, vcc, s7, v4
; CHECK-NEXT: v_subbrev_u32_e32 v8, vcc, 0, v1, vcc ; CHECK-NEXT: v_subbrev_u32_e32 v8, vcc, 0, v1, vcc
; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1 ; CHECK-NEXT: v_cmp_eq_u32_e32 vcc, 0, v1
; CHECK-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v5
; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc
; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v8, vcc
; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2 ; CHECK-NEXT: v_cmp_ne_u32_e32 vcc, 0, v2
; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc ; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v4, vcc
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; GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v9, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v0, v0, v9, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e64 v1, v7, v1, s[4:5] ; GISEL-NEXT: v_cndmask_b32_e64 v1, v7, v1, s[4:5]
; GISEL-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc ; GISEL-NEXT: v_cndmask_b32_e32 v3, v6, v3, vcc
; GISEL-NEXT: s_setpc_b64 s[30:31] ; GISEL-NEXT: s_setpc_b64 s[30:31]
; ;
; CGP-LABEL: v_urem_v2i64_oddk_denom: ; CGP-LABEL: v_urem_v2i64_oddk_denom:
; CGP: ; %bb.0: ; CGP: ; %bb.0:
; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; CGP-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; CGP-NEXT: s_mov_b32 s10, 0x12d8fb ; CGP-NEXT: v_cvt_f32_u32_e32 v4, 0x12d8fb
; CGP-NEXT: v_cvt_f32_ubyte0_e32 v4, 0 ; CGP-NEXT: v_cvt_f32_ubyte0_e32 v5, 0
; CGP-NEXT: v_cvt_f32_u32_e32 v5, s10
; CGP-NEXT: s_mov_b32 s8, 0xffed2705 ; CGP-NEXT: s_mov_b32 s8, 0xffed2705
; CGP-NEXT: v_mov_b32_e32 v6, v5 ; CGP-NEXT: s_mov_b32 s10, 0x12d8fb
; CGP-NEXT: v_mac_f32_e32 v5, 0x4f800000, v4 ; CGP-NEXT: v_mov_b32_e32 v6, v4
; CGP-NEXT: v_mac_f32_e32 v6, 0x4f800000, v4 ; CGP-NEXT: v_mac_f32_e32 v4, 0x4f800000, v5
; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v5 ; CGP-NEXT: v_mac_f32_e32 v6, 0x4f800000, v5
; CGP-NEXT: v_rcp_iflag_f32_e32 v4, v4
; CGP-NEXT: v_rcp_iflag_f32_e32 v5, v6 ; CGP-NEXT: v_rcp_iflag_f32_e32 v5, v6
; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4 ; CGP-NEXT: v_mul_f32_e32 v4, 0x5f7ffffc, v4
; CGP-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5 ; CGP-NEXT: v_mul_f32_e32 v5, 0x5f7ffffc, v5
; CGP-NEXT: v_mul_f32_e32 v6, 0x2f800000, v4 ; CGP-NEXT: v_mul_f32_e32 v6, 0x2f800000, v4
; CGP-NEXT: v_mul_f32_e32 v7, 0x2f800000, v5 ; CGP-NEXT: v_mul_f32_e32 v7, 0x2f800000, v5
; CGP-NEXT: v_trunc_f32_e32 v6, v6 ; CGP-NEXT: v_trunc_f32_e32 v6, v6
; CGP-NEXT: v_trunc_f32_e32 v7, v7 ; CGP-NEXT: v_trunc_f32_e32 v7, v7
; CGP-NEXT: v_mac_f32_e32 v4, 0xcf800000, v6 ; CGP-NEXT: v_mac_f32_e32 v4, 0xcf800000, v6
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