GlobalISel: Combine out redundant sext_inreg

[arsenm]

Summary

The scalar tests don't work yet, since computeNumSignBits apparently
doesn't handle sextload yet, and sext folds into the load first.

[aemerson]

computeNumSignBits() does not mean that the value was sign extended. It only returns you the number of top-most bits that are known to be the same. As a result, this also ends up matching G_ZEXTLOAD which is a bug I hit in an earlier attempt at this.

[arsenm]

In D86786#2244814, @aemerson wrote:

computeNumSignBits() does not mean that the value was sign extended. It only returns you the number of top-most bits that are known to be the same. As a result, this also ends up matching G_ZEXTLOAD which is a bug I hit in an earlier attempt at this.

It is correct to match zextload though, you just know 1 fewer bit vs. sextload. It doesn't matter what the source is. This is exactly what DAGCombiner does: https://github.com/llvm/llvm-project/blob/master/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L11054

[aemerson]

In D86786#2244826, @arsenm wrote:

In D86786#2244814, @aemerson wrote:

computeNumSignBits() does not mean that the value was sign extended. It only returns you the number of top-most bits that are known to be the same. As a result, this also ends up matching G_ZEXTLOAD which is a bug I hit in an earlier attempt at this.

It is correct to match zextload though, you just know 1 fewer bit vs. sextload. It doesn't matter what the source is. This is exactly what DAGCombiner does: https://github.com/llvm/llvm-project/blob/master/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L11054

Ah, I think the bug may have been an off by one issue then. So this combine can be deleted then: 64eb3a4915f0?

[arsenm]

In D86786#2244835, @aemerson wrote:

In D86786#2244826, @arsenm wrote:

In D86786#2244814, @aemerson wrote:

computeNumSignBits() does not mean that the value was sign extended. It only returns you the number of top-most bits that are known to be the same. As a result, this also ends up matching G_ZEXTLOAD which is a bug I hit in an earlier attempt at this.

It is correct to match zextload though, you just know 1 fewer bit vs. sextload. It doesn't matter what the source is. This is exactly what DAGCombiner does: https://github.com/llvm/llvm-project/blob/master/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L11054

Ah, I think the bug may have been an off by one issue then. So this combine can be deleted then: 64eb3a4915f0?

In D86786#2244835, @aemerson wrote:

In D86786#2244826, @arsenm wrote:

In D86786#2244814, @aemerson wrote:

computeNumSignBits() does not mean that the value was sign extended. It only returns you the number of top-most bits that are known to be the same. As a result, this also ends up matching G_ZEXTLOAD which is a bug I hit in an earlier attempt at this.

It is correct to match zextload though, you just know 1 fewer bit vs. sextload. It doesn't matter what the source is. This is exactly what DAGCombiner does: https://github.com/llvm/llvm-project/blob/master/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp#L11054

Ah, I think the bug may have been an off by one issue then. So this combine can be deleted then: 64eb3a4915f0?

Yes, I think so. I'll try to delete those after D86787

[arsenm]

1b201914b5a481b17a85dacc3cb675a35a9a7b97

llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h

public:
   /// \return true if \p MI is a G_AND instruction whose RHS is a mask where
   /// LHS & mask == LHS. (E.g., an all-ones value.)
   ///
   /// \param [in] MI - The G_AND instruction.
   /// \param [out] Replacement - A register the G_AND should be replaced with on
   /// success.
   bool matchAndWithTrivialMask(MachineInstr &MI, Register &Replacement);
 
+  /// \return true if \p MI is a G_SEXT_INREG that can be erased.
+  bool matchRedundantSExtInReg(MachineInstr &MI);
+
   /// Try to transform \p MI by using all of the above
   /// combine functions. Returns true if changed.
   bool tryCombine(MachineInstr &MI);
 
 private:
   // Memcpy family optimization helpers.
   bool optimizeMemcpy(MachineInstr &MI, Register Dst, Register Src,
                       unsigned KnownLen, Align DstAlign, Align SrcAlign,

llvm/include/llvm/Target/GlobalISel/Combine.td

 def and_trivial_mask_matchinfo : GIDefMatchData<"Register">;
 def and_trivial_mask: GICombineRule <
   (defs root:$root, and_trivial_mask_matchinfo:$matchinfo),
   (match (wip_match_opcode G_AND):$root,
          [{ return Helper.matchAndWithTrivialMask(*${root}, ${matchinfo}); }]),
   (apply [{ return Helper.replaceSingleDefInstWithReg(*${root}, ${matchinfo}); }])
 >;
 
+// If the input is already sign extended, just drop the extension.
+// sext_inreg x, K ->
+//   if computeNumSignBits(x) >= (x.getScalarSizeInBits() - K + 1)
+def redundant_sext_inreg: GICombineRule <
+  (defs root:$root),
+  (match (wip_match_opcode G_SEXT_INREG):$root,
+         [{ return Helper.matchRedundantSExtInReg(*${root}); }]),
+     (apply [{ return Helper.replaceSingleDefInstWithOperand(*${root}, 1); }])
+>;
+
 // FIXME: These should use the custom predicate feature once it lands.
 def undef_combines : GICombineGroup<[undef_to_fp_zero, undef_to_int_zero,
                                      undef_to_negative_one,
                                      propagate_undef_any_op,
                                      propagate_undef_all_ops,
                                      propagate_undef_shuffle_mask,
                                      erase_undef_store]>;
 
 def identity_combines : GICombineGroup<[select_same_val, right_identity_zero,
                                         binop_same_val, binop_left_to_zero,
                                         binop_right_to_zero, p2i_to_i2p,
                                         i2p_to_p2i]>;
 
-def known_bits_simplifications : GICombineGroup<[and_trivial_mask]>;
+def known_bits_simplifications : GICombineGroup<[
+  and_trivial_mask, redundant_sext_inreg]>;
 
 def width_reduction_combines : GICombineGroup<[reduce_shl_of_extend]>;
 
 def select_combines : GICombineGroup<[select_undef_cmp, select_constant_cmp]>;
 
 def trivial_combines : GICombineGroup<[copy_prop, mul_to_shl, add_p2i_to_ptradd]>;
 def all_combines : GICombineGroup<[trivial_combines, ptr_add_immed_chain,
     combines_for_extload, combine_indexed_load_store, undef_combines,
     identity_combines, simplify_add_to_sub,
     hoist_logic_op_with_same_opcode_hands,
     shl_ashr_to_sext_inreg, sext_inreg_of_load,
     width_reduction_combines, select_combines,
     known_bits_simplifications]>;

llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp

bool CombinerHelper::matchAndWithTrivialMask(MachineInstr &MI,
   APInt Mask(DstTy.getSizeInBits(), Cst);
   if (!Mask.isMask())
     return false;
 
   // Now, let's check that x & Mask == x. If this is true, then x & ~Mask == 0.
   return KB->maskedValueIsZero(Replacement, ~Mask);
 }
 
+bool CombinerHelper::matchRedundantSExtInReg(MachineInstr &MI) {
+  // If the input is already sign extended, just drop the extension.
+  Register Src = MI.getOperand(1).getReg();
+  unsigned ExtBits = MI.getOperand(2).getImm();
+  unsigned TypeSize = MRI.getType(Src).getScalarSizeInBits();
+  return KB->computeNumSignBits(Src) >= (TypeSize - ExtBits + 1);
+}
+
 bool CombinerHelper::tryCombine(MachineInstr &MI) {
   if (tryCombineCopy(MI))
     return true;
   if (tryCombineExtendingLoads(MI))
     return true;
   if (tryCombineIndexedLoadStore(MI))
     return true;
   return false;
 }

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-inreg.mir

+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
+
+---
+name: sext_inreg_s32_7_sextload_from_1
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+    ; GCN-LABEL: name: sext_inreg_s32_7_sextload_from_1
+    ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+    ; GCN: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+    ; GCN: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
+    ; GCN: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SEXTLOAD]], 7
+    ; GCN: $vgpr0 = COPY [[SEXT_INREG]](s32)
+    %0:_(p1) = COPY $vgpr0_vgpr1
+    %1:_(s32) = G_SEXTLOAD %0 :: (load 1, addrspace 1)
+    %2:_(s32) = G_SEXT_INREG %1, 7
+    $vgpr0 = COPY %2
+
+...
+
+---
+name: sext_inreg_s32_8_sextload_from_1
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+    ; GCN-LABEL: name: sext_inreg_s32_8_sextload_from_1
+    ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+    ; GCN: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+    ; GCN: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
+    ; GCN: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SEXTLOAD]], 8
+    ; GCN: $vgpr0 = COPY [[SEXT_INREG]](s32)
+    %0:_(p1) = COPY $vgpr0_vgpr1
+    %1:_(s32) = G_SEXTLOAD %0 :: (load 1, addrspace 1)
+    %2:_(s32) = G_SEXT_INREG %1, 8
+    $vgpr0 = COPY %2
+
+...
+
+---
+name: sext_inreg_s32_9_sextload_from_1
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+    ; GCN-LABEL: name: sext_inreg_s32_9_sextload_from_1
+    ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+    ; GCN: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+    ; GCN: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
+    ; GCN: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SEXTLOAD]], 9
+    ; GCN: $vgpr0 = COPY [[SEXT_INREG]](s32)
+    %0:_(p1) = COPY $vgpr0_vgpr1
+    %1:_(s32) = G_SEXTLOAD %0 :: (load 1, addrspace 1)
+    %2:_(s32) = G_SEXT_INREG %1, 9
+    $vgpr0 = COPY %2
+
+...
+
+---
+name: sext_inreg_s32_7_sext_from_s8
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+    ; GCN-LABEL: name: sext_inreg_s32_7_sext_from_s8
+    ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+    ; GCN: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+    ; GCN: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
+    ; GCN: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SEXTLOAD]], 7
+    ; GCN: $vgpr0 = COPY [[SEXT_INREG]](s32)
+    %0:_(p1) = COPY $vgpr0_vgpr1
+    %1:_(s8) = G_LOAD %0 :: (load 1, addrspace 1)
+    %2:_(s32) = G_SEXT %1
+    %3:_(s32) = G_SEXT_INREG %2, 7
+    $vgpr0 = COPY %3
+
+...
+
+---
+name: sext_inreg_s32_8_sext_from_s8
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+    ; GCN-LABEL: name: sext_inreg_s32_8_sext_from_s8
+    ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+    ; GCN: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+    ; GCN: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
+    ; GCN: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SEXTLOAD]], 8
+    ; GCN: $vgpr0 = COPY [[SEXT_INREG]](s32)
+    %0:_(p1) = COPY $vgpr0_vgpr1
+    %1:_(s8) = G_LOAD %0 :: (load 1, addrspace 1)
+    %2:_(s32) = G_SEXT %1
+    %3:_(s32) = G_SEXT_INREG %2, 8
+    $vgpr0 = COPY %3
+
+...
+
+---
+name: sext_inreg_s32_8_sext_from_s9
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+    ; GCN-LABEL: name: sext_inreg_s32_8_sext_from_s9
+    ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+    ; GCN: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+    ; GCN: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
+    ; GCN: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SEXTLOAD]], 9
+    ; GCN: $vgpr0 = COPY [[SEXT_INREG]](s32)
+    %0:_(p1) = COPY $vgpr0_vgpr1
+    %1:_(s8) = G_LOAD %0 :: (load 1, addrspace 1)
+    %2:_(s32) = G_SEXT %1
+    %3:_(s32) = G_SEXT_INREG %2, 9
+    $vgpr0 = COPY %3
+
+...
+
+---
+name: sext_inreg_v2s32_7_sext_from_v2s8
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+    ; GCN-LABEL: name: sext_inreg_v2s32_7_sext_from_v2s8
+    ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+    ; GCN: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+    ; GCN: [[LOAD:%[0-9]+]]:_(<2 x s8>) = G_LOAD [[COPY]](p1) :: (load 2, addrspace 1)
+    ; GCN: [[SEXT:%[0-9]+]]:_(<2 x s32>) = G_SEXT [[LOAD]](<2 x s8>)
+    ; GCN: [[SEXT_INREG:%[0-9]+]]:_(<2 x s32>) = G_SEXT_INREG [[SEXT]], 7
+    ; GCN: $vgpr0_vgpr1 = COPY [[SEXT_INREG]](<2 x s32>)
+    %0:_(p1) = COPY $vgpr0_vgpr1
+    %1:_(<2 x s8>) = G_LOAD %0 :: (load 2, addrspace 1)
+    %2:_(<2 x s32>) = G_SEXT %1
+    %3:_(<2 x s32>) = G_SEXT_INREG %2, 7
+    $vgpr0_vgpr1 = COPY %3
+
+...
+
+---
+name: sext_inreg_v2s32_8_sext_from_v2s8
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+    ; GCN-LABEL: name: sext_inreg_v2s32_8_sext_from_v2s8
+    ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+    ; GCN: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+    ; GCN: [[LOAD:%[0-9]+]]:_(<2 x s8>) = G_LOAD [[COPY]](p1) :: (load 2, addrspace 1)
+    ; GCN: [[SEXT:%[0-9]+]]:_(<2 x s32>) = G_SEXT [[LOAD]](<2 x s8>)
+    ; GCN: $vgpr0_vgpr1 = COPY [[SEXT]](<2 x s32>)
+    %0:_(p1) = COPY $vgpr0_vgpr1
+    %1:_(<2 x s8>) = G_LOAD %0 :: (load 2, addrspace 1)
+    %2:_(<2 x s32>) = G_SEXT %1
+    %3:_(<2 x s32>) = G_SEXT_INREG %2, 8
+    $vgpr0_vgpr1 = COPY %3
+
+...
+
+---
+name: sext_inreg_v2s32_9_sext_from_v2s8
+tracksRegLiveness: true
+body:             |
+  bb.0:
+    liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+
+    ; GCN-LABEL: name: sext_inreg_v2s32_9_sext_from_v2s8
+    ; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3
+    ; GCN: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
+    ; GCN: [[LOAD:%[0-9]+]]:_(<2 x s8>) = G_LOAD [[COPY]](p1) :: (load 2, addrspace 1)
+    ; GCN: [[SEXT:%[0-9]+]]:_(<2 x s32>) = G_SEXT [[LOAD]](<2 x s8>)
+    ; GCN: $vgpr0_vgpr1 = COPY [[SEXT]](<2 x s32>)
+    %0:_(p1) = COPY $vgpr0_vgpr1
+    %1:_(<2 x s8>) = G_LOAD %0 :: (load 2, addrspace 1)
+    %2:_(<2 x s32>) = G_SEXT %1
+    %3:_(<2 x s32>) = G_SEXT_INREG %2, 9
+    $vgpr0_vgpr1 = COPY %3
+
+...

llvm/test/CodeGen/AMDGPU/GlobalISel/saddsat.ll

 ; GFX8-LABEL: v_saddsat_i24:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX8-NEXT:    v_add_u32_e32 v2, vcc, v0, v1
 ; GFX8-NEXT:    v_bfe_i32 v3, v2, 0, 24
 ; GFX8-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v3, v0
 ; GFX8-NEXT:    v_bfe_i32 v0, v1, 0, 24
-; GFX8-NEXT:    s_bfe_i32 s6, 0, 0x180000
-; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], s6, v0
+; GFX8-NEXT:    v_cmp_gt_i32_e64 s[6:7], 0, v0
 ; GFX8-NEXT:    v_ashrrev_i32_e32 v0, 23, v3
 ; GFX8-NEXT:    v_add_u32_e32 v0, vcc, 0xff800000, v0
 ; GFX8-NEXT:    s_xor_b64 vcc, s[6:7], s[4:5]
 ; GFX8-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_saddsat_i24:
 ; GFX9:       ; %bb.0:

 ; GFX8-LABEL: s_saddsat_i24:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_add_i32 s2, s0, s1
 ; GFX8-NEXT:    s_bfe_i32 s3, s2, 0x180000
 ; GFX8-NEXT:    s_bfe_i32 s0, s0, 0x180000
 ; GFX8-NEXT:    s_cmp_lt_i32 s3, s0
 ; GFX8-NEXT:    s_cselect_b32 s0, 1, 0
 ; GFX8-NEXT:    s_bfe_i32 s1, s1, 0x180000
-; GFX8-NEXT:    s_bfe_i32 s4, 0, 0x180000
-; GFX8-NEXT:    s_cmp_lt_i32 s1, s4
+; GFX8-NEXT:    s_cmp_lt_i32 s1, 0
 ; GFX8-NEXT:    s_cselect_b32 s1, 1, 0
 ; GFX8-NEXT:    s_xor_b32 s0, s1, s0
 ; GFX8-NEXT:    s_ashr_i32 s1, s3, 23
 ; GFX8-NEXT:    s_add_i32 s1, s1, 0xff800000
 ; GFX8-NEXT:    s_and_b32 s0, s0, 1
 ; GFX8-NEXT:    s_cmp_lg_u32 s0, 0
 ; GFX8-NEXT:    s_cselect_b32 s0, s1, s2
 ; GFX8-NEXT:    ; return to shader part epilog

llvm/test/CodeGen/AMDGPU/GlobalISel/ssubsat.ll

 ; GFX8-LABEL: v_ssubsat_i24:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
 ; GFX8-NEXT:    v_sub_u32_e32 v2, vcc, v0, v1
 ; GFX8-NEXT:    v_bfe_i32 v3, v2, 0, 24
 ; GFX8-NEXT:    v_bfe_i32 v0, v0, 0, 24
 ; GFX8-NEXT:    v_cmp_lt_i32_e64 s[4:5], v3, v0
 ; GFX8-NEXT:    v_bfe_i32 v0, v1, 0, 24
-; GFX8-NEXT:    s_bfe_i32 s6, 0, 0x180000
-; GFX8-NEXT:    v_cmp_lt_i32_e64 s[6:7], s6, v0
+; GFX8-NEXT:    v_cmp_lt_i32_e64 s[6:7], 0, v0
 ; GFX8-NEXT:    v_ashrrev_i32_e32 v0, 23, v3
 ; GFX8-NEXT:    v_add_u32_e32 v0, vcc, 0xff800000, v0
 ; GFX8-NEXT:    s_xor_b64 vcc, s[6:7], s[4:5]
 ; GFX8-NEXT:    v_cndmask_b32_e32 v0, v2, v0, vcc
 ; GFX8-NEXT:    s_setpc_b64 s[30:31]
 ;
 ; GFX9-LABEL: v_ssubsat_i24:
 ; GFX9:       ; %bb.0:

 ; GFX8-LABEL: s_ssubsat_i24:
 ; GFX8:       ; %bb.0:
 ; GFX8-NEXT:    s_sub_i32 s2, s0, s1
 ; GFX8-NEXT:    s_bfe_i32 s3, s2, 0x180000
 ; GFX8-NEXT:    s_bfe_i32 s0, s0, 0x180000
 ; GFX8-NEXT:    s_cmp_lt_i32 s3, s0
 ; GFX8-NEXT:    s_cselect_b32 s0, 1, 0
 ; GFX8-NEXT:    s_bfe_i32 s1, s1, 0x180000
-; GFX8-NEXT:    s_bfe_i32 s4, 0, 0x180000
-; GFX8-NEXT:    s_cmp_gt_i32 s1, s4
+; GFX8-NEXT:    s_cmp_gt_i32 s1, 0
 ; GFX8-NEXT:    s_cselect_b32 s1, 1, 0
 ; GFX8-NEXT:    s_xor_b32 s0, s1, s0
 ; GFX8-NEXT:    s_ashr_i32 s1, s3, 23
 ; GFX8-NEXT:    s_add_i32 s1, s1, 0xff800000
 ; GFX8-NEXT:    s_and_b32 s0, s0, 1
 ; GFX8-NEXT:    s_cmp_lg_u32 s0, 0
 ; GFX8-NEXT:    s_cselect_b32 s0, s1, s2
 ; GFX8-NEXT:    ; return to shader part epilog