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Differential D86788

GlobalISel: Implement computeNumSignBits for G_SELECT
ClosedPublic

Authored by arsenm on Aug 28 2020, 8:13 AM.

Details

Reviewers
paquette
aemerson
aditya_nandakumar
dsanders
volkan

Diff Detail

Revision Contents

PathSize
llvm/
include/
llvm/
CodeGen/
GlobalISel/
3 lines
lib/
CodeGen/
GlobalISel/
16 lines
test/
CodeGen/
AMDGPU/
GlobalISel/
95 lines

Diff 288613

llvm/include/llvm/CodeGen/GlobalISel/GISelKnownBits.h

Show All 32 Linesclass GISelKnownBits : public GISelChangeObserver {
unsigned MaxDepth; unsigned MaxDepth;
/// Cache maintained during a computeKnownBits request. /// Cache maintained during a computeKnownBits request.
SmallDenseMap<Register, KnownBits, 16> ComputeKnownBitsCache; SmallDenseMap<Register, KnownBits, 16> ComputeKnownBitsCache;
void computeKnownBitsMin(Register Src0, Register Src1, KnownBits &Known, void computeKnownBitsMin(Register Src0, Register Src1, KnownBits &Known,
const APInt &DemandedElts, const APInt &DemandedElts,
unsigned Depth = 0); unsigned Depth = 0);
unsigned computeNumSignBitsMin(Register Src0, Register Src1,
const APInt &DemandedElts, unsigned Depth = 0);
public: public:
GISelKnownBits(MachineFunction &MF, unsigned MaxDepth = 6); GISelKnownBits(MachineFunction &MF, unsigned MaxDepth = 6);
virtual ~GISelKnownBits() = default; virtual ~GISelKnownBits() = default;
void setMF(MachineFunction &MF); void setMF(MachineFunction &MF);
const MachineFunction &getMachineFunction() const { const MachineFunction &getMachineFunction() const {
return MF; return MF;
} }
▲ Show 20 Lines • Show All 81 Lines • Show Last 20 Lines

llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp

Show First 20 Lines • Show All 482 Lines • ▼ Show 20 Linesvoid GISelKnownBits::computeKnownBitsImpl(Register R, KnownBits &Known,
assert(!Known.hasConflict() && "Bits known to be one AND zero?"); assert(!Known.hasConflict() && "Bits known to be one AND zero?");
LLVM_DEBUG(dumpResult(MI, Known, Depth)); LLVM_DEBUG(dumpResult(MI, Known, Depth));
// Update the cache. // Update the cache.
ComputeKnownBitsCache[R] = Known; ComputeKnownBitsCache[R] = Known;
} }
/// Compute number of sign bits for the intersection of \p Src0 and \p Src1
unsigned GISelKnownBits::computeNumSignBitsMin(Register Src0, Register Src1,
const APInt &DemandedElts,
unsigned Depth) {
// Test src1 first, since we canonicalize simpler expressions to the RHS.
unsigned Src1SignBits = computeNumSignBits(Src1, DemandedElts, Depth);
if (Src1SignBits == 1)
return 1;
return std::min(computeNumSignBits(Src0, DemandedElts, Depth), Src1SignBits);
}
unsigned GISelKnownBits::computeNumSignBits(Register R, unsigned GISelKnownBits::computeNumSignBits(Register R,
const APInt &DemandedElts, const APInt &DemandedElts,
unsigned Depth) { unsigned Depth) {
MachineInstr &MI = *MRI.getVRegDef(R); MachineInstr &MI = *MRI.getVRegDef(R);
unsigned Opcode = MI.getOpcode(); unsigned Opcode = MI.getOpcode();
if (Opcode == TargetOpcode::G_CONSTANT) if (Opcode == TargetOpcode::G_CONSTANT)
return MI.getOperand(1).getCImm()->getValue().getNumSignBits(); return MI.getOperand(1).getCImm()->getValue().getNumSignBits();
▲ Show 20 Lines • Show All 64 Lines • ▼ Show 20 Lines case TargetOpcode::G_TRUNC: {
// Check if the sign bits of source go down as far as the truncated value. // Check if the sign bits of source go down as far as the truncated value.
unsigned DstTyBits = DstTy.getScalarSizeInBits(); unsigned DstTyBits = DstTy.getScalarSizeInBits();
unsigned NumSrcBits = SrcTy.getScalarSizeInBits(); unsigned NumSrcBits = SrcTy.getScalarSizeInBits();
unsigned NumSrcSignBits = computeNumSignBits(Src, DemandedElts, Depth + 1); unsigned NumSrcSignBits = computeNumSignBits(Src, DemandedElts, Depth + 1);
if (NumSrcSignBits > (NumSrcBits - DstTyBits)) if (NumSrcSignBits > (NumSrcBits - DstTyBits))
return NumSrcSignBits - (NumSrcBits - DstTyBits); return NumSrcSignBits - (NumSrcBits - DstTyBits);
break; break;
} }
case TargetOpcode::G_SELECT: {
return computeNumSignBitsMin(MI.getOperand(2).getReg(),
MI.getOperand(3).getReg(), DemandedElts,
Depth + 1);
}
case TargetOpcode::G_INTRINSIC: case TargetOpcode::G_INTRINSIC:
case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS: case TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS:
default: { default: {
unsigned NumBits = unsigned NumBits =
TL.computeNumSignBitsForTargetInstr(*this, R, DemandedElts, MRI, Depth); TL.computeNumSignBitsForTargetInstr(*this, R, DemandedElts, MRI, Depth);
if (NumBits > 1) if (NumBits > 1)
FirstAnswer = std::max(FirstAnswer, NumBits); FirstAnswer = std::max(FirstAnswer, NumBits);
break; break;
Show All 38 Lines

llvm/test/CodeGen/AMDGPU/GlobalISel/combine-sext-inreg.mir

Show First 20 Lines • Show All 236 Lines • ▼ Show 20 Lines bb.0:
; GCN: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1) ; GCN: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
; GCN: $vgpr0 = COPY [[ZEXTLOAD]](s32) ; GCN: $vgpr0 = COPY [[ZEXTLOAD]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1 %0:_(p1) = COPY $vgpr0_vgpr1
%1:_(s32) = G_ZEXTLOAD %0 :: (load 1, addrspace 1) %1:_(s32) = G_ZEXTLOAD %0 :: (load 1, addrspace 1)
%2:_(s32) = G_SEXT_INREG %1, 9 %2:_(s32) = G_SEXT_INREG %1, 9
$vgpr0 = COPY %2 $vgpr0 = COPY %2
... ...
---
name: sext_inreg_s32_select_sextload_from_1
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4, $vgpr5
; GCN-LABEL: name: sext_inreg_s32_select_sextload_from_1
; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4, $vgpr5
; GCN: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GCN: [[COPY1:%[0-9]+]]:_(p1) = COPY $vgpr2_vgpr3
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr4
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr5
; GCN: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[COPY3]]
; GCN: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
; GCN: [[SEXTLOAD1:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY1]](p1) :: (load 1, addrspace 1)
; GCN: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SEXTLOAD]], [[SEXTLOAD1]]
; GCN: $vgpr0 = COPY [[SELECT]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(p1) = COPY $vgpr2_vgpr3
%2:_(s32) = COPY $vgpr4
%3:_(s32) = COPY $vgpr5
%4:_(s1) = G_ICMP intpred(eq), %2, %3
%5:_(s32) = G_SEXTLOAD %0 :: (load 1, addrspace 1)
%6:_(s32) = G_SEXTLOAD %1 :: (load 1, addrspace 1)
%7:_(s32) = G_SELECT %4, %5, %6
%8:_(s32) = G_SEXT_INREG %7, 8
$vgpr0 = COPY %8
...
---
name: sext_inreg_s32_select_sextload_from_1_fail_lhs
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4, $vgpr5
; GCN-LABEL: name: sext_inreg_s32_select_sextload_from_1_fail_lhs
; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4, $vgpr5
; GCN: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GCN: [[COPY1:%[0-9]+]]:_(p1) = COPY $vgpr2_vgpr3
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr4
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr5
; GCN: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[COPY3]]
; GCN: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load 4, addrspace 1)
; GCN: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY1]](p1) :: (load 1, addrspace 1)
; GCN: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[LOAD]], [[SEXTLOAD]]
; GCN: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SELECT]], 8
; GCN: $vgpr0 = COPY [[SEXT_INREG]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(p1) = COPY $vgpr2_vgpr3
%2:_(s32) = COPY $vgpr4
%3:_(s32) = COPY $vgpr5
%4:_(s1) = G_ICMP intpred(eq), %2, %3
%5:_(s32) = G_LOAD %0 :: (load 4, addrspace 1)
%6:_(s32) = G_SEXTLOAD %1 :: (load 1, addrspace 1)
%7:_(s32) = G_SELECT %4, %5, %6
%8:_(s32) = G_SEXT_INREG %7, 8
$vgpr0 = COPY %8
...
---
name: sext_inreg_s32_select_sextload_from_1_fail_rhs
tracksRegLiveness: true
body: |
bb.0:
liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4, $vgpr5
; GCN-LABEL: name: sext_inreg_s32_select_sextload_from_1_fail_rhs
; GCN: liveins: $vgpr0_vgpr1, $vgpr2_vgpr3, $vgpr4, $vgpr5
; GCN: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
; GCN: [[COPY1:%[0-9]+]]:_(p1) = COPY $vgpr2_vgpr3
; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr4
; GCN: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr5
; GCN: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(eq), [[COPY2]](s32), [[COPY3]]
; GCN: [[SEXTLOAD:%[0-9]+]]:_(s32) = G_SEXTLOAD [[COPY]](p1) :: (load 1, addrspace 1)
; GCN: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY1]](p1) :: (load 4, addrspace 1)
; GCN: [[SELECT:%[0-9]+]]:_(s32) = G_SELECT [[ICMP]](s1), [[SEXTLOAD]], [[LOAD]]
; GCN: [[SEXT_INREG:%[0-9]+]]:_(s32) = G_SEXT_INREG [[SELECT]], 8
; GCN: $vgpr0 = COPY [[SEXT_INREG]](s32)
%0:_(p1) = COPY $vgpr0_vgpr1
%1:_(p1) = COPY $vgpr2_vgpr3
%2:_(s32) = COPY $vgpr4
%3:_(s32) = COPY $vgpr5
%4:_(s1) = G_ICMP intpred(eq), %2, %3
%5:_(s32) = G_SEXTLOAD %0 :: (load 1, addrspace 1)
%6:_(s32) = G_LOAD %1 :: (load 4, addrspace 1)
%7:_(s32) = G_SELECT %4, %5, %6
%8:_(s32) = G_SEXT_INREG %7, 8
$vgpr0 = COPY %8
...