[AIX] Add support for non var_arg extended vector ABI calling convention on AIX

[ZarkoCA]

Summary

This patch enables passing non variadic vector type parameters on the caller and callee side and vector return on AIX that are passed in vector registers only.

So far, support is enabled for only the AIX extended Altivec ABI Calling convention.

[ZarkoCA]

Going to work on rebasing this patch.

[sfertile]

llvm/lib/Target/PowerPC/PPCSubtarget.h

329 ↗

(On Diff #287442)

Can I ask why this got modified?

[ZarkoCA]

llvm/lib/Target/PowerPC/PPCSubtarget.h

329 ↗

(On Diff #287442)

I was experimenting to see what differences that would make to some test cases I was trying. It shouldn't be in this patch. Sorry for the confusion.

[Xiangling_L]

Hi Zarko, could rebase this patch on the latest master?

[ZarkoCA]

In D86476#2298372, @Xiangling_L wrote:

Hi Zarko, could rebase this patch on the latest master?

Yes, the patch is in the changes planned state. I will rebase when I put it up again.

[sfertile]

We are in a poor position since this depends on D75059 which I never commit-ed since as I realized it was not really NFC because we were wrongly inserting VR_SAVE code for AIX. This had the effect of emitting a fatal error if we used vector arguments, return values and I believe if we selected any vector instructions. I never went back and updated it because there was always something higher priority to work on. I have a non-NFC update I haven't posted which relies on the calling convention lowering to emit an error when passing vector arguments, and I add an error when returning vector arguments. I will post that shortly.

This patch is trying implement 2 related but distinct things

1. Passing vector arguments.
2. Spilling and restoring of the vector.

The test for 1 will have a problem since the dependent patch will change to emitting an error for the return of a vector type. The second thing has no test coverage in this test. I suggest we put this patch on hold, and then proceed with:

1. I post the updated VRSAVE removal patch, which we can review and get commited first.
2. You split out the frame lowering changes from this patch and test them separately. We should be able to land that once D75059 lands.

Then we can either rework the lit test here to not return vector types and try to land this patch first, or enable vector returns (I think it will work as it, but we need lit test coverage).

[ZarkoCA]

This patch now only contains the ISel lowering portion of the previous version. Additionally, lowering on the callee side was implemented since with the work already contained in CC_AIX only the removal of the error in LowerCall_AIX() was required. Return vector types was also enabled. The test case checks the caller, callee and return assembly instructions.

[Xiangling_L]

Hi Zarko, the patch is out of sync with master branch, could you update it?

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

6929–6933

Just want to confirm that this would not lead to a warning when compiled with assertion off?

6952

If I understand correctly, isByVal() section is for aggregate parameter types only? Can we add some comments or even better an assertion here to indicate that?

7054

Are we using v2i64 to support vector long? As ABI says, the vector type with the long keyword are deprecated. Should we emit an error for this type instead?

[ZarkoCA]

Rebased based on new changes in https://reviews.llvm.org/D88676.
Added error for vector long type.

[ZarkoCA]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

6929–6933

I think so, but I wasn't looking to mess with that assert only to avoid it when using vectors.

6952

Yes, that sections only handles arguments that have the ByVal flag.

I think adding comments or an assertion is not related to this patch. We would need a separate review to handle that.

7054

Good catch, thanks.

[ZarkoCA]

Addressed comments and adding parent revisions.

[ZarkoCA]

Rebase to reflect changes in parent revisions.

[DiggerLin]

LGTM , but I think it need other person to approve it before commit

[sfertile]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

6988

I don;'t think we can determine if a v2i64 came from a vector long in the IR since vector long long is a v2i64 as well. Any error handling for the altivec type would have to be done in the front-end I believe.

[ZarkoCA]

Removed vector long error

[ZarkoCA]

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

6988

You're right, there was an clang patch that already handled this.

[ZarkoCA]

Removed passing vector parameters to the stack portion of patch, fixed test case and added test cases for errors.

[sfertile]

1 comment, but otherwise LGTM.

[sfertile]

Sorry Zarko, I must have deleted my comment before posting last night I've added it back now.

llvm/test/CodeGen/PowerPC/aix-cc-ext-vec-abi.ll

53

I think we should use a variable here to make sure the register used in the toc entry access is the same as used in the vector load:

lwz [[SCRATCH1:[0-9]+]], L..C0(2)
lxvw4x 1, 0, [[SCRATCH1]]

[ZarkoCA]

Updated regex in test cases to check register correct usage.

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

static bool CC_AIX(unsigned ValNo, MVT ValVT, MVT LocVT,
   const bool IsPPC64 = Subtarget.isPPC64();
   const Align PtrAlign = IsPPC64 ? Align(8) : Align(4);
   const MVT RegVT = IsPPC64 ? MVT::i64 : MVT::i32;
 
   if (ValVT.isVector() &&
       !State.getMachineFunction().getTarget().Options.AIXExtendedAltivecABI)
     report_fatal_error("the default Altivec AIX ABI is not yet supported.");
 
-  assert((!ValVT.isInteger() ||
-          (ValVT.getFixedSizeInBits() <= RegVT.getFixedSizeInBits())) &&
-         "Integer argument exceeds register size: should have been legalized");
+  if (ValVT.isInteger() && !ValVT.isVector())
+    assert(
+        (!ValVT.isInteger() ||
 
   if (ValVT == MVT::f128)
     report_fatal_error("f128 is unimplemented on AIX.");
 
   if (ArgFlags.isNest())
     report_fatal_error("Nest arguments are unimplemented.");
 
-  if (ValVT.isVector() || LocVT.isVector())
-    report_fatal_error("Vector arguments are unimplemented on AIX.");
-
   static const MCPhysReg GPR_32[] = {// 32-bit registers.
                                      PPC::R3, PPC::R4, PPC::R5, PPC::R6,
                                      PPC::R7, PPC::R8, PPC::R9, PPC::R10};
   static const MCPhysReg GPR_64[] = {// 64-bit registers.
                                      PPC::X3, PPC::X4, PPC::X5, PPC::X6,
                                      PPC::X7, PPC::X8, PPC::X9, PPC::X10};
+  static const MCPhysReg VR[] = {// Vector registers.
+                                 PPC::V2,  PPC::V3,  PPC::V4,  PPC::V5,
+                                 PPC::V6,  PPC::V7,  PPC::V8,  PPC::V9,
+                                 PPC::V10, PPC::V11, PPC::V12, PPC::V13};
 
   if (ArgFlags.isByVal()) {
     if (ArgFlags.getNonZeroByValAlign() > PtrAlign)
       report_fatal_error("Pass-by-value arguments with alignment greater than "
                          "register width are not supported.");
 
     const unsigned ByValSize = ArgFlags.getByValSize();
 
     // An empty aggregate parameter takes up no storage and no registers,
     // but needs a MemLoc for a stack slot for the formal arguments side.
if (ArgFlags.isByVal()) {
     }
     return false;
   }
 
   // Arguments always reserve parameter save area.
   switch (ValVT.SimpleTy) {
   default:
     report_fatal_error("Unhandled value type for argument.");
+  case MVT::v2i64:
+    report_fatal_error("vector long is deprecated on AIX");
   case MVT::i64:
     // i64 arguments should have been split to i32 for PPC32.
     assert(IsPPC64 && "PPC32 should have split i64 values.");
     LLVM_FALLTHROUGH;
   case MVT::i1:
   case MVT::i32: {
     const unsigned Offset = State.AllocateStack(PtrAlign.value(), PtrAlign);
     // AIX integer arguments are always passed in register width.
for (unsigned I = 0; I < StoreSize; I += PtrAlign.value()) {
                                              LocInfo)
                  : CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
         break;
       }
     }
 
     return false;
   }
+  case MVT::v4f32:
+  case MVT::v4i32:
+  case MVT::v8i16:
+  case MVT::v16i8:
+  case MVT::v2f64:
+  case MVT::v1i128: {
+    if (State.isVarArg())
+      report_fatal_error(
+          "variadic arguments for vector types are unimplemented for AIX");
+
+    const unsigned Offset = State.AllocateStack(16, Align(16));
+    if (unsigned VReg = State.AllocateReg(VR))
+      State.addLoc(CCValAssign::getReg(ValNo, ValVT, VReg, LocVT, LocInfo));
+    else
+      State.addLoc(CCValAssign::getMem(ValNo, ValVT, Offset, LocVT, LocInfo));
+    return false;
+  }
   }
   return true;
 }
 
 static const TargetRegisterClass *getRegClassForSVT(MVT::SimpleValueType SVT,
                                                     bool IsPPC64) {
   assert((IsPPC64 || SVT != MVT::i64) &&
          "i64 should have been split for 32-bit codegen.");
 
   switch (SVT) {
   default:
     report_fatal_error("Unexpected value type for formal argument");
+  case MVT::v2i64:
+    report_fatal_error("vector long is deprecated on AIX");
   case MVT::i1:
   case MVT::i32:
   case MVT::i64:
     return IsPPC64 ? &PPC::G8RCRegClass : &PPC::GPRCRegClass;
   case MVT::f32:
     return &PPC::F4RCRegClass;
   case MVT::f64:
     return &PPC::F8RCRegClass;
+  case MVT::v4f32:
+  case MVT::v4i32:
+  case MVT::v8i16:
+  case MVT::v16i8:
+  case MVT::v2f64:
+  case MVT::v1i128:
+    return &PPC::VRRCRegClass;
   }
 }
 
 static SDValue truncateScalarIntegerArg(ISD::ArgFlagsTy Flags, EVT ValVT,
                                         SelectionDAG &DAG, SDValue ArgValue,
                                         MVT LocVT, const SDLoc &dl) {
   assert(ValVT.isScalarInteger() && LocVT.isScalarInteger());
   assert(ValVT.getFixedSizeInBits() < LocVT.getFixedSizeInBits());
assert((CFlags.CallConv == CallingConv::C ||
           CFlags.CallConv == CallingConv::Fast) &&
          "Unexpected calling convention!");
 
   if (CFlags.IsPatchPoint)
     report_fatal_error("This call type is unimplemented on AIX.");
 
   const PPCSubtarget& Subtarget =
       static_cast<const PPCSubtarget&>(DAG.getSubtarget());
-  if (Subtarget.hasAltivec())
-    report_fatal_error("Altivec support is unimplemented on AIX.");
 
   MachineFunction &MF = DAG.getMachineFunction();
   SmallVector<CCValAssign, 16> ArgLocs;
   CCState CCInfo(CFlags.CallConv, CFlags.IsVarArg, MF, ArgLocs,
                  *DAG.getContext());
 
   // Reserve space for the linkage save area (LSA) on the stack.
   // In both PPC32 and PPC64 there are 6 reserved slots in the LSA:
PPCTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
 
   // Copy the result values into the output registers.
   for (unsigned i = 0, RealResIdx = 0; i != RVLocs.size(); ++i, ++RealResIdx) {
     CCValAssign &VA = RVLocs[i];
     assert(VA.isRegLoc() && "Can only return in registers!");
 
     SDValue Arg = OutVals[RealResIdx];
 
-    if (Subtarget.isAIXABI() &&
-        (VA.getLocVT().isVector() || VA.getValVT().isVector()))
-      report_fatal_error("Returning vector types not yet supported on AIX.");
-
     switch (VA.getLocInfo()) {
     default: llvm_unreachable("Unknown loc info!");
     case CCValAssign::Full: break;
     case CCValAssign::AExt:
       Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
       break;
     case CCValAssign::ZExt:
       Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);

llvm/test/CodeGen/PowerPC/aix-cc-altivec.ll

-; RUN: not --crash llc < %s -mtriple powerpc64-ibm-aix-xcoff -mcpu=pwr8 2>&1 | FileCheck %s
-; RUN: not --crash llc < %s -mtriple powerpc-ibm-aix-xcoff -mcpu=pwr8 2>&1 | FileCheck %s
-
-; This test expects a compiler diagnostic for an AIX limitation on Altivec
-; support.  When the Altivec limitation diagnostic is removed, this test
-; should compile clean and fail in order to alert the author to validate the
-; instructions emitted to initialize the GPR for the double vararg.
-; The mfvsrwz and mfvsrd instructions should be used to initialize the GPR for
-; the double vararg without going through memory.
+; RUN:  llc < %s -mtriple powerpc64-ibm-aix-xcoff -vecnvol -mcpu=pwr8 | \
+; RUN:    FileCheck %s --check-prefix=ASM64
+; RUN:  llc < %s -mtriple powerpc-ibm-aix-xcoff -vecnvol -mcpu=pwr8 | \ 
+; RUN:   FileCheck %s --check-prefix=ASM32
 
 @f1 = global float 0.000000e+00, align 4
 
 define void @call_test_vararg() {
 entry:
   %0 = load float, float* @f1, align 4
   %conv = fpext float %0 to double
   call void (i32, ...) @test_vararg(i32 42, double %conv, float %0)
   ret void
 }
 
 declare void @test_vararg(i32, ...)
 
-; CHECK: LLVM ERROR: Altivec support is unimplemented on AIX.
+
+; ASM64:           xscvdpspn
+; ASM64:           mffprd
+; ASM64:           xxsldwi
+; ASM64:           mffprwz
+
+
+; ASM32:           lfsx
+; ASM32:           fmr
+; ASM32:           stfs
+; ASM32:           lwz
+; ASM32:           stfd

llvm/test/CodeGen/PowerPC/aix-cc-ext-vec-abi.ll

+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mattr=+altivec \
+; RUN:     -mtriple powerpc-ibm-aix-xcoff < %s | \
+; RUN:   FileCheck --check-prefixes=ASM32 %s
+
+; RUN: llc -verify-machineinstrs -mcpu=pwr7 -vecnvol -mattr=+altivec \
+; RUN:     -mtriple powerpc64-ibm-aix-xcoff < %s | \
+; RUN:   FileCheck --check-prefixes=ASM64 %s
+
+define dso_local <4 x i32> @vec_callee(<4 x i32> %vec1, <4 x i32> %vec2, <4 x i32> %vec3, <4 x i32> %vec4, <4 x i32> %vec5, <4 x i32> %vec6, <4 x i32> %vec7, <4 x i32> %vec8, <4 x i32> %vec9, <4 x i32> %vec10, <4 x i32> %vec11, <4 x i32> %vec12, <4 x i32> %vec13, <4 x i32> %vec14) {
+entry:
+  %add = add <4 x i32> %vec1, %vec2
+  %add1 = add <4 x i32> %add, %vec3
+  %add2 = add <4 x i32> %add1, %vec4
+  %add3 = add <4 x i32> %add2, %vec5
+  %add4 = add <4 x i32> %add3, %vec6
+  %add5 = add <4 x i32> %add4, %vec7
+  %add6 = add <4 x i32> %add5, %vec8
+  %add7 = add <4 x i32> %add6, %vec9
+  %add8 = add <4 x i32> %add7, %vec10
+  %add9 = add <4 x i32> %add8, %vec11
+  %add10 = add <4 x i32> %add9, %vec12
+  %add11 = add <4 x i32> %add10, %vec13
+  %add12 = add <4 x i32> %add11, %vec14
+  ret <4 x i32> %add12
+}
+
+; ASM32-LABEL:    vec_callee:
+
+; ASM32:          # %bb.0: # %entry
+; ASM32-DAG:      vadduwm 2, 2, 3
+; ASM32-DAG:      addi 3, 1, 224
+; ASM32-DAG:      lxvw4x {{[0-9]+}}, 0, 3
+; ASM32-DAG:      addi 3, 1, 240
+; ASM32-DAG:      vadduwm 2, 2, 4
+; ASM32-DAG:      lxvw4x {{[0-9]+}}, 0, 3
+; ASM32-DAG:      vadduwm 2, 2, 5
+; ASM32-DAG:      vadduwm 2, 2, 6
+; ASM32-DAG:      vadduwm 2, 2, 7
+; ASM32-DAG:      vadduwm 2, 2, 8
+; ASM32-DAG:      vadduwm 2, 2, 9
+; ASM32-DAG:      vadduwm 2, 2, 10
+; ASM32-DAG:      vadduwm 2, 2, 11
+; ASM32-DAG:      vadduwm 2, 2, 12
+; ASM32-DAG:      vadduwm 2, 2, 13
+; ASM32-DAG:      vadduwm 2, 2, {{[0-9]+}}
+; ASM32-DAG:      vadduwm 2, 2, {{[0-9]+}}
+; ASM32:          blr
+
+; ASM64-LABEL:   vec_callee:
+
+; ASM64:         # %bb.0: # %entry
+; ASM64-NEXT:    vadduwm 2, 2, 3
+; ASM64-NEXT:    addi 3, 1, 240
+; ASM64-NEXT:    lxvw4x {{[0-9]+}}, 0, 3
+; ASM64-NEXT:    addi 3, 1, 256
+; ASM64-NEXT:    vadduwm 2, 2, 4
+; ASM64-NEXT:    lxvw4x {{[0-9]+}}, 0, 3
+; ASM64-NEXT:    vadduwm 2, 2, 5
+; ASM64-NEXT:    vadduwm 2, 2, 6
+; ASM64-NEXT:    vadduwm 2, 2, 7
+; ASM64-NEXT:    vadduwm 2, 2, 8
+; ASM64-NEXT:    vadduwm 2, 2, 9
+; ASM64-NEXT:    vadduwm 2, 2, 10
+; ASM64-NEXT:    vadduwm 2, 2, 11
+; ASM64-NEXT:    vadduwm 2, 2, 12
+; ASM64-NEXT:    vadduwm 2, 2, 13
+; ASM64-NEXT:    vadduwm 2, 2, {{[0-9]+}}
+; ASM64-NEXT:    vadduwm 2, 2, {{[0-9]+}}
+; ASM64-NEXT:    blr
+
+define dso_local i32 @vec_caller() {
+entry:
+  %call = call <4 x i32> @vec_callee(<4 x i32> <i32 1, i32 2, i32 3, i32 4>, <4 x i32> <i32 5, i32 6, i32 7, i32 8>, <4 x i32> <i32 9, i32 10, i32 11, i32 12>, <4 x i32> <i32 13, i32 14, i32 15, i32 16>, <4 x i32> <i32 17, i32 18, i32 19, i32 20>, <4 x i32> <i32 21, i32 22, i32 23, i32 24>, <4 x i32> <i32 25, i32 26, i32 27, i32 28>, <4 x i32> <i32 29, i32 30, i32 31, i32 32>, <4 x i32> <i32 33, i32 34, i32 35, i32 36>, <4 x i32> <i32 37, i32 38, i32 39, i32 40>, <4 x i32> <i32 41, i32 42, i32 43, i32 44>, <4 x i32> <i32 45, i32 46, i32 47, i32 48>, <4 x i32> <i32 49, i32 50, i32 51, i32 52>, <4 x i32> <i32 53, i32 54, i32 55, i32 56>)
+  ret i32 0
+}
+
+; ASM32-LABEL:   .vec_caller:
+; ASM32-DAG:     # %bb.0:                                # %entry
+; ASM32-DAG:     mflr 0
+; ASM32-DAG:     stw 0, 8(1)
+; ASM32-DAG:     stwu 1, -256(1)
+; ASM32-DAG:     lwz 3, L..C0(2)
+; ASM32-DAG:     lxvw4x 34, 0, 3
+; ASM32-DAG:     lwz 4, L..C1(2)
+; ASM32-DAG:     lxvw4x 35, 0, 4
+; ASM32-DAG:     lwz 5, L..C2(2)
+; ASM32-DAG:     lxvw4x 36, 0, 5
+; ASM32-DAG:     lwz 6, L..C3(2)
+; ASM32-DAG:     lxvw4x 37, 0, 6
+; ASM32-DAG:     lwz 7, L..C4(2)
+; ASM32-DAG:     lxvw4x 38, 0, 7
+; ASM32-DAG:     lwz 8, L..C5(2)
+; ASM32-DAG:     lxvw4x 39, 0, 8
+; ASM32-DAG:     lwz 3, L..C6(2)
+; ASM32-DAG:     lxvw4x 40, 0, 3
+; ASM32-DAG:     lwz 4, L..C7(2)
+; ASM32-DAG:     lxvw4x 41, 0, 4
+; ASM32-DAG:     lwz 5, L..C8(2)
+; ASM32-DAG:     lxvw4x 42, 0, 5
+; ASM32-DAG:     lwz 6, L..C9(2)
+; ASM32-DAG:     lxvw4x 43, 0, 6
+; ASM32-DAG:     lwz 7, L..C10(2)
+; ASM32-DAG:     lxvw4x 44, 0, 7
+; ASM32-DAG:     lwz 8, L..C11(2)
+; ASM32-DAG:     lxvw4x 45, 0, 8
+; ASM32-DAG:     lwz 3, L..C12(2)
+; ASM32-DAG:     lxvw4x 0, 0, 3
+; ASM32-DAG:     lwz 4, L..C13(2)
+; ASM32-DAG:     lxvw4x 1, 0, 4
+; ASM32-DAG:     li 3, 240
+; ASM32-DAG:     li 4, 224
+; ASM32-DAG:     stxvw4x 0, 1, 3
+; ASM32-DAG:     stxvw4x 1, 1, 4
+; ASM32-DAG:     bl .vec_callee
+; ASM32-DAG:     li 3, 0
+; ASM32-DAG:     addi 1, 1, 256
+; ASM32-DAG:     lwz 0, 8(1)
+; ASM32-DAG:     mtlr 0
+; ASM32-DAG:     blr
+
+; ASM64-LABEL:   .vec_caller:
+
+; ASM64:         # %bb.0:                                # %entry
+; ASM64-DAG:     mflr 0
+; ASM64-DAG:     std 0, 16(1)
+; ASM64-DAG:     stdu 1, -272(1)
+; ASM64-DAG:     ld 3, L..C0(2)
+; ASM64-DAG:     lxvw4x 34, 0, 3
+; ASM64-DAG:     ld 4, L..C1(2)
+; ASM64-DAG:     lxvw4x 35, 0, 4
+; ASM64-DAG:     ld 5, L..C2(2)
+; ASM64-DAG:     lxvw4x 36, 0, 5
+; ASM64-DAG:     ld 6, L..C3(2)
+; ASM64-DAG:     lxvw4x 37, 0, 6
+; ASM64-DAG:     ld 7, L..C4(2)
+; ASM64-DAG:     lxvw4x 38, 0, 7
+; ASM64-DAG:     ld 8, L..C5(2)
+; ASM64-DAG:     lxvw4x 39, 0, 8
+; ASM64-DAG:     ld 3, L..C6(2)
+; ASM64-DAG:     lxvw4x 40, 0, 3
+; ASM64-DAG:     ld 4, L..C7(2)
+; ASM64-DAG:     lxvw4x 41, 0, 4
+; ASM64-DAG:     ld 5, L..C8(2)
+; ASM64-DAG:     lxvw4x 42, 0, 5
+; ASM64-DAG:     ld 6, L..C9(2)
+; ASM64-DAG:     lxvw4x 43, 0, 6
+; ASM64-DAG:     ld 7, L..C10(2)
+; ASM64-DAG:     lxvw4x 44, 0, 7
+; ASM64-DAG:     ld 8, L..C11(2)
+; ASM64-DAG:     lxvw4x 45, 0, 8
+; ASM64-DAG:     ld 3, L..C12(2)
+; ASM64-DAG:     lxvw4x 0, 0, 3
+; ASM64-DAG:     ld 4, L..C13(2)
+; ASM64-DAG:     lxvw4x 1, 0, 4
+; ASM64-DAG:     li 3, 256
+; ASM64-DAG:     li 4, 240
+; ASM64-DAG:     stxvw4x 0, 1, 3
+; ASM64-DAG:     stxvw4x 1, 1, 4
+; ASM64-DAG:     bl .vec_callee
+; ASM64-DAG:     li 3, 0
+; ASM64-DAG:     addi 1, 1, 272
+; ASM64-DAG:     ld 0, 16(1)
+; ASM64-DAG:     mtlr 0
+; ASM64:         blr

llvm/test/CodeGen/PowerPC/aix-vector-return.ll

-; RUN: not --crash llc --verify-machineinstrs -mtriple powerpc-ibm-aix-xcoff \
-; RUN:   -mattr=+altivec 2>&1 < %s | FileCheck %s
-
-; RUN: not --crash llc --verify-machineinstrs -mtriple powerpc64-ibm-aix-xcoff \
-; RUN:   -mattr=+altivec 2>&1 < %s | FileCheck %s
-
-; CHECK: LLVM ERROR: Returning vector types not yet supported on AIX.
-
-define dso_local <4 x i32> @test() local_unnamed_addr #0 {
-  entry:
-    ret <4 x i32> zeroinitializer
-}