[SVE][CodeGen] Fix up warnings in sve-split-insert/extract tests

[david-arm]

Summary

I have fixed up some more ElementCount/TypeSize related warnings in
the following tests:

CodeGen/AArch64/sve-split-extract-elt.ll
CodeGen/AArch64/sve-split-insert-elt.ll

In SelectionDAG::CreateStackTemporary we were relying upon the implicit
cast from TypeSize -> uint64_t when calling MachineFrameInfo::CreateStackObject.
I've fixed this by passing in the known minimum size instead, which I
believe is fine because the associated stack id indicates whether this
is a scalable object or not.

I've also fixed up a case in TargetLowering::SimplifyDemandedBits when
extracting a vector element from a scalable vector. The result is a scalar,
hence it wasn't caught at the start of the function. If the vector is
scalable we just bail out for now.

[kmclaughlin]

LGTM

[efriedma]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

2041

Please bail out here for scalable vectors even if KnownIdx is in range. The rest of the demanded bits code code doesn't expect scalable vectors at the moment.

[david-arm]

• Changed the SimplifyDemandedBits code to simply bail out if it's a scalable vector we're extracting from.

[efriedma]

LGTM with one minor comment

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

2032

getFixedValue().

[fhahn]

llvm/include/llvm/Support/TypeSize.h

119 ↗

(On Diff #289897)

Does this comment intentionally not use ///? As is the documentation is missing in the rendered docs (https://llvm.org/docs/doxygen/classllvm_1_1LinearPolySize.html#a46d9c84b6f3a39f74ab8d5906c4fcf61)

[david-arm]

llvm/include/llvm/Support/TypeSize.h

119 ↗

(On Diff #289897)

No it's not intentional. I just forget to use the doxygen format sometimes. I can fix this.

[fhahn]

llvm/include/llvm/Support/TypeSize.h

119 ↗

(On Diff #289897)

that would be great, thanks!

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp

 }
 
 SDValue SelectionDAG::CreateStackTemporary(TypeSize Bytes, Align Alignment) {
   MachineFrameInfo &MFI = MF->getFrameInfo();
   const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
   int StackID = 0;
   if (Bytes.isScalable())
     StackID = TFI->getStackIDForScalableVectors();
-  int FrameIdx = MFI.CreateStackObject(Bytes, Alignment,
+  // The stack id gives an indication of whether the object is scalable or
+  // not, so it's safe to pass in the minimum size here.
+  int FrameIdx = MFI.CreateStackObject(Bytes.getKnownMinSize(), Alignment,
                                        false, nullptr, StackID);
   return getFrameIndex(FrameIdx, TLI->getFrameIndexTy(getDataLayout()));
 }
 
 SDValue SelectionDAG::CreateStackTemporary(EVT VT, unsigned minAlign) {
   Type *Ty = VT.getTypeForEVT(*getContext());
   Align StackAlign =
       std::max(getDataLayout().getPrefTypeAlign(Ty), Align(minAlign));

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

case ISD::AssertZext: {
     assert(!Known.hasConflict() && "Bits known to be one AND zero?");
 
     Known.Zero |= ~InMask;
     break;
   }
   case ISD::EXTRACT_VECTOR_ELT: {
     SDValue Src = Op.getOperand(0);
     SDValue Idx = Op.getOperand(1);
-    unsigned NumSrcElts = Src.getValueType().getVectorNumElements();
+    ElementCount SrcEltCnt = Src.getValueType().getVectorElementCount();
     unsigned EltBitWidth = Src.getScalarValueSizeInBits();
 
+    if (SrcEltCnt.isScalable())
+      return false;
+
     // Demand the bits from every vector element without a constant index.
+    unsigned NumSrcElts = SrcEltCnt.getKnownMinValue();
     APInt DemandedSrcElts = APInt::getAllOnesValue(NumSrcElts);
     if (auto *CIdx = dyn_cast<ConstantSDNode>(Idx))
       if (CIdx->getAPIntValue().ult(NumSrcElts))
         DemandedSrcElts = APInt::getOneBitSet(NumSrcElts, CIdx->getZExtValue());
 
     // If BitWidth > EltBitWidth the value is anyext:ed. So we do not know
     // anything about the extended bits.
     APInt DemandedSrcBits = DemandedBits;
     if (BitWidth > EltBitWidth)
       DemandedSrcBits = DemandedSrcBits.trunc(EltBitWidth);
 
     if (SimplifyDemandedBits(Src, DemandedSrcBits, DemandedSrcElts, Known2, TLO,
                              Depth + 1))
       return true;
 
     // Attempt to avoid multi-use ops if we don't need anything from them.
     if (!DemandedSrcBits.isAllOnesValue() ||

llvm/test/CodeGen/AArch64/sve-split-extract-elt.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
+; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
+
+; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
+; WARN-NOT: warning
 
 ; EXTRACT VECTOR ELT
 
 define i32 @promote_extract_2i32_idx(<vscale x 2 x i32> %a, i32 %idx) {
 ; CHECK-LABEL: promote_extract_2i32_idx:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    // kill: def $w0 killed $w0 def $x0
 ; CHECK-NEXT:    sxtw x8, w0

llvm/test/CodeGen/AArch64/sve-split-insert-elt.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
+; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s 2>%t | FileCheck %s
+; RUN: FileCheck --check-prefix=WARN --allow-empty %s <%t
+
+; If this check fails please read test/CodeGen/AArch64/README for instructions on how to resolve it.
+; WARN-NOT: warning
 
 ; INSERT VECTOR ELT
 
 define <vscale x 8 x i8> @promote_insert_8i8(<vscale x 8 x i8> %a, i8 %elt, i64 %idx) {
 ; CHECK-LABEL: promote_insert_8i8:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    mov z1.h, w1
 ; CHECK-NEXT:    index z2.h, #0, #1