[X86][GlobalISel] Legalize G_ICMP results to s8.

[craig.topper]

Summary

We need to produce a setcc instruction which has an 8-bit result.
This gets rid of a bunch of cases that were using the s1->s8/s16/s32/s64
handling in selectZExt.

I'm not very familiar with GlobalISel yet so I'm not yet sure
the best way to do things. I'd especially like feedback on the
best way to handle the currently split 32-bit and 64-bit mode
handling.

[arsenm]

LGTM. Not sure I understand the question for 32 vs. 64 mode since it doesn't seem relevant for compares

llvm/lib/Target/X86/X86LegalizerInfo.cpp

172

You'll have to do something explicitly to handle non-0 address space pointers eventually, but this is a good enough first step

[craig.topper]

In D85814#2212932, @arsenm wrote:

LGTM. Not sure I understand the question for 32 vs. 64 mode since it doesn't seem relevant for compares

I have two different getActionDefinitionsBuilder calls with 2 different type lists for G_ICMP right now. One called when !is64BitMode() and one called when is64BitMode(). I feel like I should move up to the constructor so they are closer together instead of being in separate setLegalizerInfo32bit and setLegalizerInfo64Bit functions. Then I'm wondering if there's a good way to use one getActionDefinitionsBuilder and conditionally control the type lists. And not just for G_ICMP. We're missing clampScalar and or other type legalization controls on a lot of operations right now.

[arsenm]

In D85814#2213559, @craig.topper wrote:

In D85814#2212932, @arsenm wrote:

LGTM. Not sure I understand the question for 32 vs. 64 mode since it doesn't seem relevant for compares

I have two different getActionDefinitionsBuilder calls with 2 different type lists for G_ICMP right now. One called when !is64BitMode() and one called when is64BitMode(). I feel like I should move up to the constructor so they are closer together instead of being in separate setLegalizerInfo32bit and setLegalizerInfo64Bit functions. Then I'm wondering if there's a good way to use one getActionDefinitionsBuilder and conditionally control the type lists. And not just for G_ICMP. We're missing clampScalar and or other type legalization controls on a lot of operations right now.

I didn't understand why the x86 legalizer rules are structured the way they are last time I looked at them. I think they're overly split up. I also think these were a bit overly aggressive in setting rules before most of the legalizer actions were implemented, and they're using the legacy rule tables. It might be worth just starting over on them (although I'm not sure what the tradeoffs are between the old table rules, and the new actionbuilder is. I only recently discovered the action builder is not merely syntactic sugar for the setAction style of rules)

llvm/lib/Target/X86/X86LegalizerInfo.cpp

 //===- X86LegalizerInfo.cpp --------------------------------------*- C++ -*-==//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 /// \file
getActionDefinitionsBuilder(
       .legalFor({s8, s16, s32})
       .clampScalar(0, s8, s32);
 
     getActionDefinitionsBuilder(
         {G_SHL, G_LSHR, G_ASHR})
       .legalFor({{s8, s8}, {s16, s8}, {s32, s8}})
       .clampScalar(0, s8, s32)
       .clampScalar(1, s8, s8);
+
+    // Comparison
+    getActionDefinitionsBuilder(G_ICMP)
+      .legalForCartesianProduct({s8}, {s8, s16, s32, p0})
+      .clampScalar(0, s8, s8);
   }
 
   // Control-flow
   setAction({G_BRCOND, s1}, Legal);
 
   // Constants
   for (auto Ty : {s8, s16, s32, p0})
     setAction({TargetOpcode::G_CONSTANT, Ty}, Legal);
 
   // Extensions
   for (auto Ty : {s8, s16, s32}) {
     setAction({G_ZEXT, Ty}, Legal);
     setAction({G_SEXT, Ty}, Legal);
     setAction({G_ANYEXT, Ty}, Legal);
   }
   setAction({G_ANYEXT, s128}, Legal);
   getActionDefinitionsBuilder(G_SEXT_INREG).lower();
 
-  // Comparison
-  setAction({G_ICMP, s1}, Legal);
-
-  for (auto Ty : {s8, s16, s32, p0})
-    setAction({G_ICMP, 1, Ty}, Legal);
-
   // Merge/Unmerge
   for (const auto &Ty : {s16, s32, s64}) {
     setAction({G_MERGE_VALUES, Ty}, Legal);
     setAction({G_UNMERGE_VALUES, 1, Ty}, Legal);
   }
   for (const auto &Ty : {s8, s16, s32}) {
     setAction({G_MERGE_VALUES, 1, Ty}, Legal);
     setAction({G_UNMERGE_VALUES, Ty}, Legal);
void X86LegalizerInfo::setLegalizerInfo64bit() {
   getActionDefinitionsBuilder(G_FPTOSI)
       .legalForCartesianProduct({s32, s64})
       .clampScalar(1, s32, s64)
       .widenScalarToNextPow2(0)
       .clampScalar(0, s32, s64)
       .widenScalarToNextPow2(1);
 
   // Comparison
-  setAction({G_ICMP, 1, s64}, Legal);
+  getActionDefinitionsBuilder(G_ICMP)
+    .legalForCartesianProduct({s8}, {s8, s16, s32, s64, p0})
+    .clampScalar(0, s8, s8);
 
   getActionDefinitionsBuilder(G_FCMP)
       .legalForCartesianProduct({s8}, {s32, s64})
       .clampScalar(0, s8, s8)
       .clampScalar(1, s32, s64)
       .widenScalarToNextPow2(1);
 
   // Divisions

llvm/test/CodeGen/X86/GlobalISel/cmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=x86_64-linux-gnu    -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=ALL
 
 define i32 @test_icmp_eq_i8(i8 %a, i8 %b) {
 ; ALL-LABEL: test_icmp_eq_i8:
 ; ALL:       # %bb.0:
+; ALL-NEXT:    xorl %eax, %eax
 ; ALL-NEXT:    cmpb %sil, %dil
 ; ALL-NEXT:    sete %al
 ; ALL-NEXT:    andl $1, %eax
 ; ALL-NEXT:    retq
   %r = icmp eq i8 %a, %b
   %res =  zext i1 %r to i32
   ret i32 %res
 }
 
 define i32 @test_icmp_eq_i16(i16 %a, i16 %b) {
 ; ALL-LABEL: test_icmp_eq_i16:
 ; ALL:       # %bb.0:
+; ALL-NEXT:    xorl %eax, %eax
 ; ALL-NEXT:    cmpw %si, %di
 ; ALL-NEXT:    sete %al
 ; ALL-NEXT:    andl $1, %eax
 ; ALL-NEXT:    retq
   %r = icmp eq i16 %a, %b
   %res =  zext i1 %r to i32
   ret i32 %res
 }
 
 define i32 @test_icmp_eq_i64(i64 %a, i64 %b) {
 ; ALL-LABEL: test_icmp_eq_i64:
 ; ALL:       # %bb.0:
+; ALL-NEXT:    xorl %eax, %eax
 ; ALL-NEXT:    cmpq %rsi, %rdi
 ; ALL-NEXT:    sete %al
 ; ALL-NEXT:    andl $1, %eax
 ; ALL-NEXT:    retq
   %r = icmp eq i64 %a, %b
   %res =  zext i1 %r to i32
   ret i32 %res
 }
 
 define i32 @test_icmp_eq_i32(i32 %a, i32 %b) {
 ; ALL-LABEL: test_icmp_eq_i32:
 ; ALL:       # %bb.0:
+; ALL-NEXT:    xorl %eax, %eax
 ; ALL-NEXT:    cmpl %esi, %edi
 ; ALL-NEXT:    sete %al
 ; ALL-NEXT:    andl $1, %eax
 ; ALL-NEXT:    retq
   %r = icmp eq i32 %a, %b
   %res =  zext i1 %r to i32
   ret i32 %res
 }
 
 define i32 @test_icmp_ne_i32(i32 %a, i32 %b) {
 ; ALL-LABEL: test_icmp_ne_i32:
 ; ALL:       # %bb.0:
+; ALL-NEXT:    xorl %eax, %eax
 ; ALL-NEXT:    cmpl %esi, %edi
 ; ALL-NEXT:    setne %al
 ; ALL-NEXT:    andl $1, %eax
 ; ALL-NEXT:    retq
   %r = icmp ne i32 %a, %b
   %res =  zext i1 %r to i32
   ret i32 %res
 }
 
 define i32 @test_icmp_ugt_i32(i32 %a, i32 %b) {
 ; ALL-LABEL: test_icmp_ugt_i32:
 ; ALL:       # %bb.0:
+; ALL-NEXT:    xorl %eax, %eax
 ; ALL-NEXT:    cmpl %esi, %edi
 ; ALL-NEXT:    seta %al
 ; ALL-NEXT:    andl $1, %eax
 ; ALL-NEXT:    retq
   %r = icmp ugt i32 %a, %b
   %res =  zext i1 %r to i32
   ret i32 %res
 }
 
 define i32 @test_icmp_uge_i32(i32 %a, i32 %b) {
 ; ALL-LABEL: test_icmp_uge_i32:
 ; ALL:       # %bb.0:
+; ALL-NEXT:    xorl %eax, %eax
 ; ALL-NEXT:    cmpl %esi, %edi
 ; ALL-NEXT:    setae %al
 ; ALL-NEXT:    andl $1, %eax
 ; ALL-NEXT:    retq
   %r = icmp uge i32 %a, %b
   %res =  zext i1 %r to i32
   ret i32 %res
 }
 
 define i32 @test_icmp_ult_i32(i32 %a, i32 %b) {
 ; ALL-LABEL: test_icmp_ult_i32:
 ; ALL:       # %bb.0:
+; ALL-NEXT:    xorl %eax, %eax
 ; ALL-NEXT:    cmpl %esi, %edi
 ; ALL-NEXT:    setb %al
 ; ALL-NEXT:    andl $1, %eax
 ; ALL-NEXT:    retq
   %r = icmp ult i32 %a, %b
   %res =  zext i1 %r to i32
   ret i32 %res
 }
 
 define i32 @test_icmp_ule_i32(i32 %a, i32 %b) {
 ; ALL-LABEL: test_icmp_ule_i32:
 ; ALL:       # %bb.0:
+; ALL-NEXT:    xorl %eax, %eax
 ; ALL-NEXT:    cmpl %esi, %edi
 ; ALL-NEXT:    setbe %al
 ; ALL-NEXT:    andl $1, %eax
 ; ALL-NEXT:    retq
   %r = icmp ule i32 %a, %b
   %res =  zext i1 %r to i32
   ret i32 %res
 }
 
 define i32 @test_icmp_sgt_i32(i32 %a, i32 %b) {
 ; ALL-LABEL: test_icmp_sgt_i32:
 ; ALL:       # %bb.0:
+; ALL-NEXT:    xorl %eax, %eax
 ; ALL-NEXT:    cmpl %esi, %edi
 ; ALL-NEXT:    setg %al
 ; ALL-NEXT:    andl $1, %eax
 ; ALL-NEXT:    retq
   %r = icmp sgt i32 %a, %b
   %res =  zext i1 %r to i32
   ret i32 %res
 }
 
 define i32 @test_icmp_sge_i32(i32 %a, i32 %b) {
 ; ALL-LABEL: test_icmp_sge_i32:
 ; ALL:       # %bb.0:
+; ALL-NEXT:    xorl %eax, %eax
 ; ALL-NEXT:    cmpl %esi, %edi
 ; ALL-NEXT:    setge %al
 ; ALL-NEXT:    andl $1, %eax
 ; ALL-NEXT:    retq
   %r = icmp sge i32 %a, %b
   %res =  zext i1 %r to i32
   ret i32 %res
 }
 
 define i32 @test_icmp_slt_i32(i32 %a, i32 %b) {
 ; ALL-LABEL: test_icmp_slt_i32:
 ; ALL:       # %bb.0:
+; ALL-NEXT:    xorl %eax, %eax
 ; ALL-NEXT:    cmpl %esi, %edi
 ; ALL-NEXT:    setl %al
 ; ALL-NEXT:    andl $1, %eax
 ; ALL-NEXT:    retq
   %r = icmp slt i32 %a, %b
   %res =  zext i1 %r to i32
   ret i32 %res
 }
 
 define i32 @test_icmp_sle_i32(i32 %a, i32 %b) {
 ; ALL-LABEL: test_icmp_sle_i32:
 ; ALL:       # %bb.0:
+; ALL-NEXT:    xorl %eax, %eax
 ; ALL-NEXT:    cmpl %esi, %edi
 ; ALL-NEXT:    setle %al
 ; ALL-NEXT:    andl $1, %eax
 ; ALL-NEXT:    retq
   %r = icmp sle i32 %a, %b
   %res =  zext i1 %r to i32
   ret i32 %res
 }
 

llvm/test/CodeGen/X86/GlobalISel/legalize-cmp.mir

registers:
   - { id: 3, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_cmp_i8
     ; CHECK: [[COPY:%[0-9]+]]:_(s8) = COPY $dil
     ; CHECK: [[COPY1:%[0-9]+]]:_(s8) = COPY $sil
-    ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY]](s8), [[COPY1]]
-    ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
-    ; CHECK: $eax = COPY [[ZEXT]](s32)
+    ; CHECK: [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(ult), [[COPY]](s8), [[COPY1]]
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
+    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
+    ; CHECK: $eax = COPY [[AND]](s32)
     ; CHECK: RET 0, implicit $eax
     %0(s8) = COPY $dil
     %1(s8) = COPY $sil
     %2(s1) = G_ICMP intpred(ult), %0(s8), %1
     %3(s32) = G_ZEXT %2(s1)
     $eax = COPY %3(s32)
     RET 0, implicit $eax
 
registers:
   - { id: 3, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_cmp_i16
     ; CHECK: [[COPY:%[0-9]+]]:_(s16) = COPY $di
     ; CHECK: [[COPY1:%[0-9]+]]:_(s16) = COPY $si
-    ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY]](s16), [[COPY1]]
-    ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
-    ; CHECK: $eax = COPY [[ZEXT]](s32)
+    ; CHECK: [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(ult), [[COPY]](s16), [[COPY1]]
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
+    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
+    ; CHECK: $eax = COPY [[AND]](s32)
     ; CHECK: RET 0, implicit $eax
     %0(s16) = COPY $di
     %1(s16) = COPY $si
     %2(s1) = G_ICMP intpred(ult), %0(s16), %1
     %3(s32) = G_ZEXT %2(s1)
     $eax = COPY %3(s32)
     RET 0, implicit $eax
 
registers:
   - { id: 3, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_cmp_i32
     ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $edi
     ; CHECK: [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
-    ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
-    ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
-    ; CHECK: $eax = COPY [[ZEXT]](s32)
+    ; CHECK: [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(ult), [[COPY]](s32), [[COPY1]]
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
+    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
+    ; CHECK: $eax = COPY [[AND]](s32)
     ; CHECK: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
     %2(s1) = G_ICMP intpred(ult), %0(s32), %1
     %3(s32) = G_ZEXT %2(s1)
     $eax = COPY %3(s32)
     RET 0, implicit $eax
 
registers:
   - { id: 3, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $rdi, $rsi
 
     ; CHECK-LABEL: name: test_cmp_i64
     ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $rdi
     ; CHECK: [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi
-    ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY]](s64), [[COPY1]]
-    ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
-    ; CHECK: $eax = COPY [[ZEXT]](s32)
+    ; CHECK: [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(ult), [[COPY]](s64), [[COPY1]]
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
+    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
+    ; CHECK: $eax = COPY [[AND]](s32)
     ; CHECK: RET 0, implicit $eax
     %0(s64) = COPY $rdi
     %1(s64) = COPY $rsi
     %2(s1) = G_ICMP intpred(ult), %0(s64), %1
     %3(s32) = G_ZEXT %2(s1)
     $eax = COPY %3(s32)
     RET 0, implicit $eax
 
registers:
   - { id: 3, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $rdi, $rsi
 
     ; CHECK-LABEL: name: test_cmp_p0
     ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $rdi
     ; CHECK: [[COPY1:%[0-9]+]]:_(p0) = COPY $rsi
-    ; CHECK: [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(ult), [[COPY]](p0), [[COPY1]]
-    ; CHECK: [[ZEXT:%[0-9]+]]:_(s32) = G_ZEXT [[ICMP]](s1)
-    ; CHECK: $eax = COPY [[ZEXT]](s32)
+    ; CHECK: [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(ult), [[COPY]](p0), [[COPY1]]
+    ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+    ; CHECK: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ICMP]](s8)
+    ; CHECK: [[AND:%[0-9]+]]:_(s32) = G_AND [[ANYEXT]], [[C]]
+    ; CHECK: $eax = COPY [[AND]](s32)
     ; CHECK: RET 0, implicit $eax
     %0(p0) = COPY $rdi
     %1(p0) = COPY $rsi
     %2(s1) = G_ICMP intpred(ult), %0(p0), %1
     %3(s32) = G_ZEXT %2(s1)
     $eax = COPY %3(s32)
     RET 0, implicit $eax
 
 ...

llvm/test/CodeGen/X86/GlobalISel/legalize-phi.mir

body:             |
   ; ALL-LABEL: name: test_i1
   ; ALL: bb.0.entry:
   ; ALL:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; ALL:   liveins: $edi, $edx, $esi
   ; ALL:   [[COPY:%[0-9]+]]:_(s32) = COPY $edi
   ; ALL:   [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
   ; ALL:   [[COPY2:%[0-9]+]]:_(s32) = COPY $edx
   ; ALL:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-  ; ALL:   [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
-  ; ALL:   [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
-  ; ALL:   G_BRCOND [[ICMP]](s1), %bb.2
+  ; ALL:   [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
+  ; ALL:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s8)
+  ; ALL:   [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
+  ; ALL:   G_BRCOND [[TRUNC]](s1), %bb.2
   ; ALL: bb.1.cond.false:
   ; ALL:   successors: %bb.2(0x80000000)
-  ; ALL:   [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s32)
+  ; ALL:   [[TRUNC2:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s32)
   ; ALL: bb.2.cond.end:
-  ; ALL:   [[PHI:%[0-9]+]]:_(s8) = G_PHI [[TRUNC1]](s8), %bb.1, [[TRUNC]](s8), %bb.0
+  ; ALL:   [[PHI:%[0-9]+]]:_(s8) = G_PHI [[TRUNC2]](s8), %bb.1, [[TRUNC1]](s8), %bb.0
   ; ALL:   [[COPY3:%[0-9]+]]:_(s8) = COPY [[PHI]](s8)
   ; ALL:   $al = COPY [[COPY3]](s8)
   ; ALL:   RET 0, implicit $al
   bb.1.entry:
     successors: %bb.3(0x40000000), %bb.2(0x40000000)
     liveins: $edi, $edx, $esi
 
     %0:_(s32) = COPY $edi
body:             |
   ; ALL:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; ALL:   liveins: $edi, $edx, $esi
   ; ALL:   [[COPY:%[0-9]+]]:_(s32) = COPY $edi
   ; ALL:   [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
   ; ALL:   [[TRUNC:%[0-9]+]]:_(s8) = G_TRUNC [[COPY1]](s32)
   ; ALL:   [[COPY2:%[0-9]+]]:_(s32) = COPY $edx
   ; ALL:   [[TRUNC1:%[0-9]+]]:_(s8) = G_TRUNC [[COPY2]](s32)
   ; ALL:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-  ; ALL:   [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
-  ; ALL:   G_BRCOND [[ICMP]](s1), %bb.2
+  ; ALL:   [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
+  ; ALL:   [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s8)
+  ; ALL:   G_BRCOND [[TRUNC2]](s1), %bb.2
   ; ALL: bb.1.cond.false:
   ; ALL:   successors: %bb.2(0x80000000)
   ; ALL: bb.2.cond.end:
   ; ALL:   [[PHI:%[0-9]+]]:_(s8) = G_PHI [[TRUNC1]](s8), %bb.1, [[TRUNC]](s8), %bb.0
   ; ALL:   $al = COPY [[PHI]](s8)
   ; ALL:   RET 0, implicit $al
   bb.1.entry:
     successors: %bb.3(0x40000000), %bb.2(0x40000000)
body:             |
   ; ALL:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; ALL:   liveins: $edi, $edx, $esi
   ; ALL:   [[COPY:%[0-9]+]]:_(s32) = COPY $edi
   ; ALL:   [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
   ; ALL:   [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY1]](s32)
   ; ALL:   [[COPY2:%[0-9]+]]:_(s32) = COPY $edx
   ; ALL:   [[TRUNC1:%[0-9]+]]:_(s16) = G_TRUNC [[COPY2]](s32)
   ; ALL:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-  ; ALL:   [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
-  ; ALL:   G_BRCOND [[ICMP]](s1), %bb.2
+  ; ALL:   [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
+  ; ALL:   [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s8)
+  ; ALL:   G_BRCOND [[TRUNC2]](s1), %bb.2
   ; ALL: bb.1.cond.false:
   ; ALL:   successors: %bb.2(0x80000000)
   ; ALL: bb.2.cond.end:
   ; ALL:   [[PHI:%[0-9]+]]:_(s16) = G_PHI [[TRUNC1]](s16), %bb.1, [[TRUNC]](s16), %bb.0
   ; ALL:   $ax = COPY [[PHI]](s16)
   ; ALL:   RET 0, implicit $ax
   bb.1.entry:
     successors: %bb.3(0x40000000), %bb.2(0x40000000)
body:             |
   ; ALL-LABEL: name: test_i32
   ; ALL: bb.0.entry:
   ; ALL:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; ALL:   liveins: $edi, $edx, $esi
   ; ALL:   [[COPY:%[0-9]+]]:_(s32) = COPY $edi
   ; ALL:   [[COPY1:%[0-9]+]]:_(s32) = COPY $esi
   ; ALL:   [[COPY2:%[0-9]+]]:_(s32) = COPY $edx
   ; ALL:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-  ; ALL:   [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
-  ; ALL:   G_BRCOND [[ICMP]](s1), %bb.1
+  ; ALL:   [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
+  ; ALL:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s8)
+  ; ALL:   G_BRCOND [[TRUNC]](s1), %bb.1
   ; ALL:   G_BR %bb.2
   ; ALL: bb.1.cond.true:
   ; ALL:   successors: %bb.3(0x80000000)
   ; ALL:   G_BR %bb.3
   ; ALL: bb.2.cond.false:
   ; ALL:   successors: %bb.3(0x80000000)
   ; ALL: bb.3.cond.end:
   ; ALL:   [[PHI:%[0-9]+]]:_(s32) = G_PHI [[COPY1]](s32), %bb.1, [[COPY2]](s32), %bb.2
body:             |
   ; ALL-LABEL: name: test_i64
   ; ALL: bb.0.entry:
   ; ALL:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; ALL:   liveins: $edi, $rdx, $rsi
   ; ALL:   [[COPY:%[0-9]+]]:_(s32) = COPY $edi
   ; ALL:   [[COPY1:%[0-9]+]]:_(s64) = COPY $rsi
   ; ALL:   [[COPY2:%[0-9]+]]:_(s64) = COPY $rdx
   ; ALL:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-  ; ALL:   [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
-  ; ALL:   G_BRCOND [[ICMP]](s1), %bb.1
+  ; ALL:   [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
+  ; ALL:   [[TRUNC:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s8)
+  ; ALL:   G_BRCOND [[TRUNC]](s1), %bb.1
   ; ALL:   G_BR %bb.2
   ; ALL: bb.1.cond.true:
   ; ALL:   successors: %bb.3(0x80000000)
   ; ALL:   G_BR %bb.3
   ; ALL: bb.2.cond.false:
   ; ALL:   successors: %bb.3(0x80000000)
   ; ALL: bb.3.cond.end:
   ; ALL:   [[PHI:%[0-9]+]]:_(s64) = G_PHI [[COPY1]](s64), %bb.1, [[COPY2]](s64), %bb.2
body:             |
   ; ALL:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; ALL:   liveins: $edi, $xmm0, $xmm1
   ; ALL:   [[COPY:%[0-9]+]]:_(s32) = COPY $edi
   ; ALL:   [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm0
   ; ALL:   [[TRUNC:%[0-9]+]]:_(s32) = G_TRUNC [[COPY1]](s128)
   ; ALL:   [[COPY2:%[0-9]+]]:_(s128) = COPY $xmm1
   ; ALL:   [[TRUNC1:%[0-9]+]]:_(s32) = G_TRUNC [[COPY2]](s128)
   ; ALL:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-  ; ALL:   [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
-  ; ALL:   G_BRCOND [[ICMP]](s1), %bb.2
+  ; ALL:   [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
+  ; ALL:   [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s8)
+  ; ALL:   G_BRCOND [[TRUNC2]](s1), %bb.2
   ; ALL: bb.1.cond.false:
   ; ALL:   successors: %bb.2(0x80000000)
   ; ALL: bb.2.cond.end:
   ; ALL:   [[PHI:%[0-9]+]]:_(s32) = G_PHI [[TRUNC1]](s32), %bb.1, [[TRUNC]](s32), %bb.0
   ; ALL:   [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[PHI]](s32)
   ; ALL:   $xmm0 = COPY [[ANYEXT]](s128)
   ; ALL:   RET 0, implicit $xmm0
   bb.1.entry:
body:             |
   ; ALL:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; ALL:   liveins: $edi, $xmm0, $xmm1
   ; ALL:   [[COPY:%[0-9]+]]:_(s32) = COPY $edi
   ; ALL:   [[COPY1:%[0-9]+]]:_(s128) = COPY $xmm0
   ; ALL:   [[TRUNC:%[0-9]+]]:_(s64) = G_TRUNC [[COPY1]](s128)
   ; ALL:   [[COPY2:%[0-9]+]]:_(s128) = COPY $xmm1
   ; ALL:   [[TRUNC1:%[0-9]+]]:_(s64) = G_TRUNC [[COPY2]](s128)
   ; ALL:   [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 0
-  ; ALL:   [[ICMP:%[0-9]+]]:_(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
-  ; ALL:   G_BRCOND [[ICMP]](s1), %bb.2
+  ; ALL:   [[ICMP:%[0-9]+]]:_(s8) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
+  ; ALL:   [[TRUNC2:%[0-9]+]]:_(s1) = G_TRUNC [[ICMP]](s8)
+  ; ALL:   G_BRCOND [[TRUNC2]](s1), %bb.2
   ; ALL: bb.1.cond.false:
   ; ALL:   successors: %bb.2(0x80000000)
   ; ALL: bb.2.cond.end:
   ; ALL:   [[PHI:%[0-9]+]]:_(s64) = G_PHI [[TRUNC1]](s64), %bb.1, [[TRUNC]](s64), %bb.0
   ; ALL:   [[ANYEXT:%[0-9]+]]:_(s128) = G_ANYEXT [[PHI]](s64)
   ; ALL:   $xmm0 = COPY [[ANYEXT]](s128)
   ; ALL:   RET 0, implicit $xmm0
   bb.1.entry:

llvm/test/CodeGen/X86/GlobalISel/regbankselect-X86_64.mir

registers:
   - { id: 2, class: _ }
   - { id: 3, class: _ }
   - { id: 4, class: _ }
 body:             |
   bb.0 (%ir-block.0):
     ; FAST-LABEL: name: test_gep
     ; FAST: [[DEF:%[0-9]+]]:gpr(p0) = IMPLICIT_DEF
     ; FAST: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 20
-    ; FAST: [[GEP:%[0-9]+]]:gpr(p0) = G_PTR_ADD [[DEF]], [[C]](s32)
+    ; FAST: [[PTR_ADD:%[0-9]+]]:gpr(p0) = G_PTR_ADD [[DEF]], [[C]](s32)
     ; FAST: [[C1:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 20
-    ; FAST: [[GEP1:%[0-9]+]]:gpr(p0) = G_PTR_ADD [[DEF]], [[C1]](s64)
+    ; FAST: [[PTR_ADD1:%[0-9]+]]:gpr(p0) = G_PTR_ADD [[DEF]], [[C1]](s64)
     ; FAST: RET 0
     ; GREEDY-LABEL: name: test_gep
     ; GREEDY: [[DEF:%[0-9]+]]:gpr(p0) = IMPLICIT_DEF
     ; GREEDY: [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 20
-    ; GREEDY: [[GEP:%[0-9]+]]:gpr(p0) = G_PTR_ADD [[DEF]], [[C]](s32)
+    ; GREEDY: [[PTR_ADD:%[0-9]+]]:gpr(p0) = G_PTR_ADD [[DEF]], [[C]](s32)
     ; GREEDY: [[C1:%[0-9]+]]:gpr(s64) = G_CONSTANT i64 20
-    ; GREEDY: [[GEP1:%[0-9]+]]:gpr(p0) = G_PTR_ADD [[DEF]], [[C1]](s64)
+    ; GREEDY: [[PTR_ADD1:%[0-9]+]]:gpr(p0) = G_PTR_ADD [[DEF]], [[C1]](s64)
     ; GREEDY: RET 0
     %0(p0) = IMPLICIT_DEF
     %1(s32) = G_CONSTANT i32 20
     %2(p0) = G_PTR_ADD %0, %1(s32)
     %3(s64) = G_CONSTANT i64 20
     %4(p0) = G_PTR_ADD %0, %3(s64)
     RET 0
 
body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; FAST-LABEL: name: test_icmp_eq_i8
     ; FAST: [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi
     ; FAST: [[TRUNC:%[0-9]+]]:gpr(s8) = G_TRUNC [[COPY]](s32)
     ; FAST: [[COPY1:%[0-9]+]]:gpr(s32) = COPY $esi
     ; FAST: [[TRUNC1:%[0-9]+]]:gpr(s8) = G_TRUNC [[COPY1]](s32)
-    ; FAST: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(eq), [[TRUNC]](s8), [[TRUNC1]]
-    ; FAST: [[ANYEXT:%[0-9]+]]:gpr(s8) = G_ANYEXT [[ICMP]](s1)
-    ; FAST: $al = COPY [[ANYEXT]](s8)
+    ; FAST: [[ICMP:%[0-9]+]]:gpr(s8) = G_ICMP intpred(eq), [[TRUNC]](s8), [[TRUNC1]]
+    ; FAST: [[COPY2:%[0-9]+]]:gpr(s8) = COPY [[ICMP]](s8)
+    ; FAST: $al = COPY [[COPY2]](s8)
     ; FAST: RET 0, implicit $al
     ; GREEDY-LABEL: name: test_icmp_eq_i8
     ; GREEDY: [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi
     ; GREEDY: [[TRUNC:%[0-9]+]]:gpr(s8) = G_TRUNC [[COPY]](s32)
     ; GREEDY: [[COPY1:%[0-9]+]]:gpr(s32) = COPY $esi
     ; GREEDY: [[TRUNC1:%[0-9]+]]:gpr(s8) = G_TRUNC [[COPY1]](s32)
-    ; GREEDY: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(eq), [[TRUNC]](s8), [[TRUNC1]]
-    ; GREEDY: [[ANYEXT:%[0-9]+]]:gpr(s8) = G_ANYEXT [[ICMP]](s1)
-    ; GREEDY: $al = COPY [[ANYEXT]](s8)
+    ; GREEDY: [[ICMP:%[0-9]+]]:gpr(s8) = G_ICMP intpred(eq), [[TRUNC]](s8), [[TRUNC1]]
+    ; GREEDY: [[COPY2:%[0-9]+]]:gpr(s8) = COPY [[ICMP]](s8)
+    ; GREEDY: $al = COPY [[COPY2]](s8)
     ; GREEDY: RET 0, implicit $al
     %2:_(s32) = COPY $edi
     %0:_(s8) = G_TRUNC %2(s32)
     %3:_(s32) = COPY $esi
     %1:_(s8) = G_TRUNC %3(s32)
-    %4:_(s1) = G_ICMP intpred(eq), %0(s8), %1
-    %5:_(s8) = G_ANYEXT %4(s1)
+    %6:_(s8) = G_ICMP intpred(eq), %0(s8), %1
+    %5:_(s8) = COPY %6(s8)
     $al = COPY %5(s8)
     RET 0, implicit $al
 
 ...
 ---
 name:            test_icmp_eq_i16
 alignment:       16
 legalized:       true
 regBankSelected: false
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; FAST-LABEL: name: test_icmp_eq_i16
     ; FAST: [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi
     ; FAST: [[TRUNC:%[0-9]+]]:gpr(s16) = G_TRUNC [[COPY]](s32)
     ; FAST: [[COPY1:%[0-9]+]]:gpr(s32) = COPY $esi
     ; FAST: [[TRUNC1:%[0-9]+]]:gpr(s16) = G_TRUNC [[COPY1]](s32)
-    ; FAST: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(eq), [[TRUNC]](s16), [[TRUNC1]]
-    ; FAST: [[ANYEXT:%[0-9]+]]:gpr(s8) = G_ANYEXT [[ICMP]](s1)
-    ; FAST: $al = COPY [[ANYEXT]](s8)
+    ; FAST: [[ICMP:%[0-9]+]]:gpr(s8) = G_ICMP intpred(eq), [[TRUNC]](s16), [[TRUNC1]]
+    ; FAST: [[COPY2:%[0-9]+]]:gpr(s8) = COPY [[ICMP]](s8)
+    ; FAST: $al = COPY [[COPY2]](s8)
     ; FAST: RET 0, implicit $al
     ; GREEDY-LABEL: name: test_icmp_eq_i16
     ; GREEDY: [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi
     ; GREEDY: [[TRUNC:%[0-9]+]]:gpr(s16) = G_TRUNC [[COPY]](s32)
     ; GREEDY: [[COPY1:%[0-9]+]]:gpr(s32) = COPY $esi
     ; GREEDY: [[TRUNC1:%[0-9]+]]:gpr(s16) = G_TRUNC [[COPY1]](s32)
-    ; GREEDY: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(eq), [[TRUNC]](s16), [[TRUNC1]]
-    ; GREEDY: [[ANYEXT:%[0-9]+]]:gpr(s8) = G_ANYEXT [[ICMP]](s1)
-    ; GREEDY: $al = COPY [[ANYEXT]](s8)
+    ; GREEDY: [[ICMP:%[0-9]+]]:gpr(s8) = G_ICMP intpred(eq), [[TRUNC]](s16), [[TRUNC1]]
+    ; GREEDY: [[COPY2:%[0-9]+]]:gpr(s8) = COPY [[ICMP]](s8)
+    ; GREEDY: $al = COPY [[COPY2]](s8)
     ; GREEDY: RET 0, implicit $al
     %2:_(s32) = COPY $edi
     %0:_(s16) = G_TRUNC %2(s32)
     %3:_(s32) = COPY $esi
     %1:_(s16) = G_TRUNC %3(s32)
-    %4:_(s1) = G_ICMP intpred(eq), %0(s16), %1
-    %5:_(s8) = G_ANYEXT %4(s1)
+    %6:_(s8) = G_ICMP intpred(eq), %0(s16), %1
+    %5:_(s8) = COPY %6(s8)
     $al = COPY %5(s8)
     RET 0, implicit $al
 
 ...
 ---
 name:            test_icmp_eq_i32
 alignment:       16
 legalized:       true
 regBankSelected: false
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; FAST-LABEL: name: test_icmp_eq_i32
     ; FAST: [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi
     ; FAST: [[COPY1:%[0-9]+]]:gpr(s32) = COPY $esi
-    ; FAST: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
-    ; FAST: [[ANYEXT:%[0-9]+]]:gpr(s8) = G_ANYEXT [[ICMP]](s1)
-    ; FAST: $al = COPY [[ANYEXT]](s8)
+    ; FAST: [[ICMP:%[0-9]+]]:gpr(s8) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
+    ; FAST: [[COPY2:%[0-9]+]]:gpr(s8) = COPY [[ICMP]](s8)
+    ; FAST: $al = COPY [[COPY2]](s8)
     ; FAST: RET 0, implicit $al
     ; GREEDY-LABEL: name: test_icmp_eq_i32
     ; GREEDY: [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi
     ; GREEDY: [[COPY1:%[0-9]+]]:gpr(s32) = COPY $esi
-    ; GREEDY: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
-    ; GREEDY: [[ANYEXT:%[0-9]+]]:gpr(s8) = G_ANYEXT [[ICMP]](s1)
-    ; GREEDY: $al = COPY [[ANYEXT]](s8)
+    ; GREEDY: [[ICMP:%[0-9]+]]:gpr(s8) = G_ICMP intpred(eq), [[COPY]](s32), [[COPY1]]
+    ; GREEDY: [[COPY2:%[0-9]+]]:gpr(s8) = COPY [[ICMP]](s8)
+    ; GREEDY: $al = COPY [[COPY2]](s8)
     ; GREEDY: RET 0, implicit $al
     %0:_(s32) = COPY $edi
     %1:_(s32) = COPY $esi
-    %2:_(s1) = G_ICMP intpred(eq), %0(s32), %1
-    %3:_(s8) = G_ANYEXT %2(s1)
+    %4:_(s8) = G_ICMP intpred(eq), %0(s32), %1
+    %3:_(s8) = COPY %4(s8)
     $al = COPY %3(s8)
     RET 0, implicit $al
 
 ...
 ---
 name:            test_icmp_eq_i64
 alignment:       16
 legalized:       true
 regBankSelected: false
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
   - { id: 2, class: _ }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $rdi, $rsi
 
     ; FAST-LABEL: name: test_icmp_eq_i64
     ; FAST: [[COPY:%[0-9]+]]:gpr(s64) = COPY $rdi
     ; FAST: [[COPY1:%[0-9]+]]:gpr(s64) = COPY $rsi
-    ; FAST: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(eq), [[COPY]](s64), [[COPY1]]
-    ; FAST: [[ANYEXT:%[0-9]+]]:gpr(s8) = G_ANYEXT [[ICMP]](s1)
-    ; FAST: $al = COPY [[ANYEXT]](s8)
+    ; FAST: [[ICMP:%[0-9]+]]:gpr(s8) = G_ICMP intpred(eq), [[COPY]](s64), [[COPY1]]
+    ; FAST: [[COPY2:%[0-9]+]]:gpr(s8) = COPY [[ICMP]](s8)
+    ; FAST: $al = COPY [[COPY2]](s8)
     ; FAST: RET 0, implicit $al
     ; GREEDY-LABEL: name: test_icmp_eq_i64
     ; GREEDY: [[COPY:%[0-9]+]]:gpr(s64) = COPY $rdi
     ; GREEDY: [[COPY1:%[0-9]+]]:gpr(s64) = COPY $rsi
-    ; GREEDY: [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(eq), [[COPY]](s64), [[COPY1]]
-    ; GREEDY: [[ANYEXT:%[0-9]+]]:gpr(s8) = G_ANYEXT [[ICMP]](s1)
-    ; GREEDY: $al = COPY [[ANYEXT]](s8)
+    ; GREEDY: [[ICMP:%[0-9]+]]:gpr(s8) = G_ICMP intpred(eq), [[COPY]](s64), [[COPY1]]
+    ; GREEDY: [[COPY2:%[0-9]+]]:gpr(s8) = COPY [[ICMP]](s8)
+    ; GREEDY: $al = COPY [[COPY2]](s8)
     ; GREEDY: RET 0, implicit $al
     %0:_(s64) = COPY $rdi
     %1:_(s64) = COPY $rsi
-    %2:_(s1) = G_ICMP intpred(eq), %0(s64), %1
-    %3:_(s8) = G_ANYEXT %2(s1)
+    %4:_(s8) = G_ICMP intpred(eq), %0(s64), %1
+    %3:_(s8) = COPY %4(s8)
     $al = COPY %3(s8)
     RET 0, implicit $al
 
 ...
 ---
 name:            test_xor_i8
 alignment:       16
 legalized:       true

 tracksRegLiveness: true
 registers:
   - { id: 0, class: _, preferred-register: '' }
   - { id: 1, class: _, preferred-register: '' }
   - { id: 2, class: _, preferred-register: '' }
   - { id: 3, class: _, preferred-register: '' }
   - { id: 4, class: _, preferred-register: '' }
   - { id: 5, class: _, preferred-register: '' }
+  - { id: 6, class: _, preferred-register: '' }
 body:             |
   ; FAST-LABEL: name: test_i32
   ; FAST: bb.0.entry:
   ; FAST:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; FAST:   liveins: $edi, $edx, $esi
   ; FAST:   [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi
   ; FAST:   [[COPY1:%[0-9]+]]:gpr(s32) = COPY $esi
   ; FAST:   [[COPY2:%[0-9]+]]:gpr(s32) = COPY $edx
   ; FAST:   [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
-  ; FAST:   [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
-  ; FAST:   G_BRCOND [[ICMP]](s1), %bb.1
+  ; FAST:   [[ICMP:%[0-9]+]]:gpr(s8) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
+  ; FAST:   [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[ICMP]](s8)
+  ; FAST:   G_BRCOND [[TRUNC]](s1), %bb.1
   ; FAST:   G_BR %bb.2
   ; FAST: bb.1.cond.true:
   ; FAST:   successors: %bb.3(0x80000000)
   ; FAST:   G_BR %bb.3
   ; FAST: bb.2.cond.false:
   ; FAST:   successors: %bb.3(0x80000000)
   ; FAST: bb.3.cond.end:
   ; FAST:   [[PHI:%[0-9]+]]:gpr(s32) = G_PHI [[COPY1]](s32), %bb.1, [[COPY2]](s32), %bb.2
   ; FAST:   $eax = COPY [[PHI]](s32)
   ; FAST:   RET 0, implicit $eax
   ; GREEDY-LABEL: name: test_i32
   ; GREEDY: bb.0.entry:
   ; GREEDY:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; GREEDY:   liveins: $edi, $edx, $esi
   ; GREEDY:   [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi
   ; GREEDY:   [[COPY1:%[0-9]+]]:gpr(s32) = COPY $esi
   ; GREEDY:   [[COPY2:%[0-9]+]]:gpr(s32) = COPY $edx
   ; GREEDY:   [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
-  ; GREEDY:   [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
-  ; GREEDY:   G_BRCOND [[ICMP]](s1), %bb.1
+  ; GREEDY:   [[ICMP:%[0-9]+]]:gpr(s8) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
+  ; GREEDY:   [[TRUNC:%[0-9]+]]:gpr(s1) = G_TRUNC [[ICMP]](s8)
+  ; GREEDY:   G_BRCOND [[TRUNC]](s1), %bb.1
   ; GREEDY:   G_BR %bb.2
   ; GREEDY: bb.1.cond.true:
   ; GREEDY:   successors: %bb.3(0x80000000)
   ; GREEDY:   G_BR %bb.3
   ; GREEDY: bb.2.cond.false:
   ; GREEDY:   successors: %bb.3(0x80000000)
   ; GREEDY: bb.3.cond.end:
   ; GREEDY:   [[PHI:%[0-9]+]]:gpr(s32) = G_PHI [[COPY1]](s32), %bb.1, [[COPY2]](s32), %bb.2
   ; GREEDY:   $eax = COPY [[PHI]](s32)
   ; GREEDY:   RET 0, implicit $eax
   bb.0.entry:
     successors: %bb.1(0x40000000), %bb.2(0x40000000)
     liveins: $edi, $edx, $esi
 
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
     %2(s32) = COPY $edx
     %3(s32) = G_CONSTANT i32 0
-    %4(s1) = G_ICMP intpred(sgt), %0(s32), %3
+    %6(s8) = G_ICMP intpred(sgt), %0(s32), %3
+    %4(s1) = G_TRUNC %6(s8)
     G_BRCOND %4(s1), %bb.1
     G_BR %bb.2
 
   bb.1.cond.true:
     successors: %bb.3(0x80000000)
 
     G_BR %bb.3
 
body:             |
   ; FAST:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; FAST:   liveins: $edi, $xmm0, $xmm1
   ; FAST:   [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi
   ; FAST:   [[COPY1:%[0-9]+]]:vecr(s128) = COPY $xmm0
   ; FAST:   [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY1]](s128)
   ; FAST:   [[COPY2:%[0-9]+]]:vecr(s128) = COPY $xmm1
   ; FAST:   [[TRUNC1:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY2]](s128)
   ; FAST:   [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
-  ; FAST:   [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
-  ; FAST:   G_BRCOND [[ICMP]](s1), %bb.2
+  ; FAST:   [[ICMP:%[0-9]+]]:gpr(s8) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
+  ; FAST:   [[TRUNC2:%[0-9]+]]:gpr(s1) = G_TRUNC [[ICMP]](s8)
+  ; FAST:   G_BRCOND [[TRUNC2]](s1), %bb.2
   ; FAST: bb.1.cond.false:
   ; FAST:   successors: %bb.2(0x80000000)
   ; FAST: bb.2.cond.end:
   ; FAST:   [[PHI:%[0-9]+]]:vecr(s32) = G_PHI [[TRUNC1]](s32), %bb.1, [[TRUNC]](s32), %bb.0
   ; FAST:   [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[PHI]](s32)
   ; FAST:   $xmm0 = COPY [[ANYEXT]](s128)
   ; FAST:   RET 0, implicit $xmm0
   ; GREEDY-LABEL: name: test_float
   ; GREEDY: bb.0.entry:
   ; GREEDY:   successors: %bb.2(0x40000000), %bb.1(0x40000000)
   ; GREEDY:   liveins: $edi, $xmm0, $xmm1
   ; GREEDY:   [[COPY:%[0-9]+]]:gpr(s32) = COPY $edi
   ; GREEDY:   [[COPY1:%[0-9]+]]:vecr(s128) = COPY $xmm0
   ; GREEDY:   [[TRUNC:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY1]](s128)
   ; GREEDY:   [[COPY2:%[0-9]+]]:vecr(s128) = COPY $xmm1
   ; GREEDY:   [[TRUNC1:%[0-9]+]]:vecr(s32) = G_TRUNC [[COPY2]](s128)
   ; GREEDY:   [[C:%[0-9]+]]:gpr(s32) = G_CONSTANT i32 0
-  ; GREEDY:   [[ICMP:%[0-9]+]]:gpr(s1) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
-  ; GREEDY:   G_BRCOND [[ICMP]](s1), %bb.2
+  ; GREEDY:   [[ICMP:%[0-9]+]]:gpr(s8) = G_ICMP intpred(sgt), [[COPY]](s32), [[C]]
+  ; GREEDY:   [[TRUNC2:%[0-9]+]]:gpr(s1) = G_TRUNC [[ICMP]](s8)
+  ; GREEDY:   G_BRCOND [[TRUNC2]](s1), %bb.2
   ; GREEDY: bb.1.cond.false:
   ; GREEDY:   successors: %bb.2(0x80000000)
   ; GREEDY: bb.2.cond.end:
   ; GREEDY:   [[PHI:%[0-9]+]]:vecr(s32) = G_PHI [[TRUNC1]](s32), %bb.1, [[TRUNC]](s32), %bb.0
   ; GREEDY:   [[ANYEXT:%[0-9]+]]:vecr(s128) = G_ANYEXT [[PHI]](s32)
   ; GREEDY:   $xmm0 = COPY [[ANYEXT]](s128)
   ; GREEDY:   RET 0, implicit $xmm0
   bb.1.entry:
     successors: %bb.3(0x40000000), %bb.2(0x40000000)
     liveins: $edi, $xmm0, $xmm1
 
     %0:_(s32) = COPY $edi
     %3:_(s128) = COPY $xmm0
     %1:_(s32) = G_TRUNC %3(s128)
     %4:_(s128) = COPY $xmm1
     %2:_(s32) = G_TRUNC %4(s128)
     %5:_(s32) = G_CONSTANT i32 0
-    %6:_(s1) = G_ICMP intpred(sgt), %0(s32), %5
+    %9:_(s8) = G_ICMP intpred(sgt), %0(s32), %5
+    %6:_(s1) = G_TRUNC %9(s8)
     G_BRCOND %6(s1), %bb.3
 
   bb.2.cond.false:
     successors: %bb.3(0x80000000)
 
 
   bb.3.cond.end:
     %7:_(s32) = G_PHI %2(s32), %bb.2, %1(s32), %bb.1

llvm/test/CodeGen/X86/GlobalISel/select-cmp.mir

 ---
 name:            test_icmp_eq_i8
 alignment:       16
 legalized:       true
 regBankSelected: true
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
+  - { id: 2, class: _ }
   - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_eq_i8
     ; CHECK: [[COPY:%[0-9]+]]:gr8 = COPY $dil
     ; CHECK: [[COPY1:%[0-9]+]]:gr8 = COPY $sil
     ; CHECK: CMP8rr [[COPY]], [[COPY1]], implicit-def $eflags
     ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
-    ; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
-    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
-    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
+    ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[MOVZX32rr8_]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s8) = COPY $dil
     %1(s8) = COPY $sil
-    %2(s1) = G_ICMP intpred(eq), %0(s8), %1
-    %3(s32) = G_ZEXT %2(s1)
+    %4(s8) = G_ICMP intpred(eq), %0(s8), %1
+    %5(s32) = G_CONSTANT i32 1
+    %6(s32) = G_ANYEXT %4(s8)
+    %3(s32) = G_AND %6, %5
     $eax = COPY %3(s32)
     RET 0, implicit $eax
 
 ...
 ---
 name:            test_icmp_eq_i16
 alignment:       16
 legalized:       true
 regBankSelected: true
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
+  - { id: 2, class: _ }
   - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_eq_i16
     ; CHECK: [[COPY:%[0-9]+]]:gr16 = COPY $di
     ; CHECK: [[COPY1:%[0-9]+]]:gr16 = COPY $si
     ; CHECK: CMP16rr [[COPY]], [[COPY1]], implicit-def $eflags
     ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
-    ; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
-    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
-    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
+    ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[MOVZX32rr8_]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s16) = COPY $di
     %1(s16) = COPY $si
-    %2(s1) = G_ICMP intpred(eq), %0(s16), %1
-    %3(s32) = G_ZEXT %2(s1)
+    %4(s8) = G_ICMP intpred(eq), %0(s16), %1
+    %5(s32) = G_CONSTANT i32 1
+    %6(s32) = G_ANYEXT %4(s8)
+    %3(s32) = G_AND %6, %5
     $eax = COPY %3(s32)
     RET 0, implicit $eax
 
 ...
 ---
 name:            test_icmp_eq_i64
 alignment:       16
 legalized:       true
 regBankSelected: true
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
+  - { id: 2, class: _ }
   - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $rdi, $rsi
 
     ; CHECK-LABEL: name: test_icmp_eq_i64
     ; CHECK: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
     ; CHECK: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
     ; CHECK: CMP64rr [[COPY]], [[COPY1]], implicit-def $eflags
     ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
-    ; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
-    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
-    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
+    ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[MOVZX32rr8_]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s64) = COPY $rdi
     %1(s64) = COPY $rsi
-    %2(s1) = G_ICMP intpred(eq), %0(s64), %1
-    %3(s32) = G_ZEXT %2(s1)
+    %4(s8) = G_ICMP intpred(eq), %0(s64), %1
+    %5(s32) = G_CONSTANT i32 1
+    %6(s32) = G_ANYEXT %4(s8)
+    %3(s32) = G_AND %6, %5
     $eax = COPY %3(s32)
     RET 0, implicit $eax
 
 ...
 ---
 name:            test_icmp_eq_i32
 alignment:       16
 legalized:       true
 regBankSelected: true
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
+  - { id: 2, class: _ }
   - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_eq_i32
     ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
     ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
     ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 4, implicit $eflags
-    ; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
-    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
-    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
+    ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[MOVZX32rr8_]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
-    %2(s1) = G_ICMP intpred(eq), %0(s32), %1
-    %3(s32) = G_ZEXT %2(s1)
+    %4(s8) = G_ICMP intpred(eq), %0(s32), %1
+    %5(s32) = G_CONSTANT i32 1
+    %6(s32) = G_ANYEXT %4(s8)
+    %3(s32) = G_AND %6, %5
     $eax = COPY %3(s32)
     RET 0, implicit $eax
 
 ...
 ---
 name:            test_icmp_ne_i32
 alignment:       16
 legalized:       true
 regBankSelected: true
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
+  - { id: 2, class: _ }
   - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_ne_i32
     ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
     ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
     ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 5, implicit $eflags
-    ; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
-    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
-    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
+    ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[MOVZX32rr8_]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
-    %2(s1) = G_ICMP intpred(ne), %0(s32), %1
-    %3(s32) = G_ZEXT %2(s1)
+    %4(s8) = G_ICMP intpred(ne), %0(s32), %1
+    %5(s32) = G_CONSTANT i32 1
+    %6(s32) = G_ANYEXT %4(s8)
+    %3(s32) = G_AND %6, %5
     $eax = COPY %3(s32)
     RET 0, implicit $eax
 
 ...
 ---
 name:            test_icmp_ugt_i32
 alignment:       16
 legalized:       true
 regBankSelected: true
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
+  - { id: 2, class: _ }
   - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_ugt_i32
     ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
     ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
     ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 7, implicit $eflags
-    ; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
-    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
-    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
+    ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[MOVZX32rr8_]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
-    %2(s1) = G_ICMP intpred(ugt), %0(s32), %1
-    %3(s32) = G_ZEXT %2(s1)
+    %4(s8) = G_ICMP intpred(ugt), %0(s32), %1
+    %5(s32) = G_CONSTANT i32 1
+    %6(s32) = G_ANYEXT %4(s8)
+    %3(s32) = G_AND %6, %5
     $eax = COPY %3(s32)
     RET 0, implicit $eax
 
 ...
 ---
 name:            test_icmp_uge_i32
 alignment:       16
 legalized:       true
 regBankSelected: true
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
+  - { id: 2, class: _ }
   - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_uge_i32
     ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
     ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
     ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 3, implicit $eflags
-    ; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
-    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
-    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
+    ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[MOVZX32rr8_]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
-    %2(s1) = G_ICMP intpred(uge), %0(s32), %1
-    %3(s32) = G_ZEXT %2(s1)
+    %4(s8) = G_ICMP intpred(uge), %0(s32), %1
+    %5(s32) = G_CONSTANT i32 1
+    %6(s32) = G_ANYEXT %4(s8)
+    %3(s32) = G_AND %6, %5
     $eax = COPY %3(s32)
     RET 0, implicit $eax
 
 ...
 ---
 name:            test_icmp_ult_i32
 alignment:       16
 legalized:       true
 regBankSelected: true
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
+  - { id: 2, class: _ }
   - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_ult_i32
     ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
     ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
     ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 2, implicit $eflags
-    ; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
-    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
-    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
+    ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[MOVZX32rr8_]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
-    %2(s1) = G_ICMP intpred(ult), %0(s32), %1
-    %3(s32) = G_ZEXT %2(s1)
+    %4(s8) = G_ICMP intpred(ult), %0(s32), %1
+    %5(s32) = G_CONSTANT i32 1
+    %6(s32) = G_ANYEXT %4(s8)
+    %3(s32) = G_AND %6, %5
     $eax = COPY %3(s32)
     RET 0, implicit $eax
 
 ...
 ---
 name:            test_icmp_ule_i32
 alignment:       16
 legalized:       true
 regBankSelected: true
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
+  - { id: 2, class: _ }
   - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_ule_i32
     ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
     ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
     ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 6, implicit $eflags
-    ; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
-    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
-    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
+    ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[MOVZX32rr8_]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
-    %2(s1) = G_ICMP intpred(ule), %0(s32), %1
-    %3(s32) = G_ZEXT %2(s1)
+    %4(s8) = G_ICMP intpred(ule), %0(s32), %1
+    %5(s32) = G_CONSTANT i32 1
+    %6(s32) = G_ANYEXT %4(s8)
+    %3(s32) = G_AND %6, %5
     $eax = COPY %3(s32)
     RET 0, implicit $eax
 
 ...
 ---
 name:            test_icmp_sgt_i32
 alignment:       16
 legalized:       true
 regBankSelected: true
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
+  - { id: 2, class: _ }
   - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_sgt_i32
     ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
     ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
     ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 15, implicit $eflags
-    ; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
-    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
-    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
+    ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[MOVZX32rr8_]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
-    %2(s1) = G_ICMP intpred(sgt), %0(s32), %1
-    %3(s32) = G_ZEXT %2(s1)
+    %4(s8) = G_ICMP intpred(sgt), %0(s32), %1
+    %5(s32) = G_CONSTANT i32 1
+    %6(s32) = G_ANYEXT %4(s8)
+    %3(s32) = G_AND %6, %5
     $eax = COPY %3(s32)
     RET 0, implicit $eax
 
 ...
 ---
 name:            test_icmp_sge_i32
 alignment:       16
 legalized:       true
 regBankSelected: true
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
+  - { id: 2, class: _ }
   - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_sge_i32
     ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
     ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
     ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 13, implicit $eflags
-    ; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
-    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
-    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
+    ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[MOVZX32rr8_]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
-    %2(s1) = G_ICMP intpred(sge), %0(s32), %1
-    %3(s32) = G_ZEXT %2(s1)
+    %4(s8) = G_ICMP intpred(sge), %0(s32), %1
+    %5(s32) = G_CONSTANT i32 1
+    %6(s32) = G_ANYEXT %4(s8)
+    %3(s32) = G_AND %6, %5
     $eax = COPY %3(s32)
     RET 0, implicit $eax
 
 ...
 ---
 name:            test_icmp_slt_i32
 alignment:       16
 legalized:       true
 regBankSelected: true
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
+  - { id: 2, class: _ }
   - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_slt_i32
     ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
     ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
     ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 12, implicit $eflags
-    ; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
-    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
-    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
+    ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[MOVZX32rr8_]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
-    %2(s1) = G_ICMP intpred(slt), %0(s32), %1
-    %3(s32) = G_ZEXT %2(s1)
+    %4(s8) = G_ICMP intpred(slt), %0(s32), %1
+    %5(s32) = G_CONSTANT i32 1
+    %6(s32) = G_ANYEXT %4(s8)
+    %3(s32) = G_AND %6, %5
     $eax = COPY %3(s32)
     RET 0, implicit $eax
 
 ...
 ---
 name:            test_icmp_sle_i32
 alignment:       16
 legalized:       true
 regBankSelected: true
 registers:
   - { id: 0, class: gpr }
   - { id: 1, class: gpr }
-  - { id: 2, class: gpr }
+  - { id: 2, class: _ }
   - { id: 3, class: gpr }
+  - { id: 4, class: gpr }
+  - { id: 5, class: gpr }
+  - { id: 6, class: gpr }
 body:             |
   bb.1 (%ir-block.0):
     liveins: $edi, $esi
 
     ; CHECK-LABEL: name: test_icmp_sle_i32
     ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi
     ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
     ; CHECK: CMP32rr [[COPY]], [[COPY1]], implicit-def $eflags
     ; CHECK: [[SETCCr:%[0-9]+]]:gr8 = SETCCr 14, implicit $eflags
-    ; CHECK: [[DEF:%[0-9]+]]:gr32 = IMPLICIT_DEF
-    ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:gr32 = INSERT_SUBREG [[DEF]], [[SETCCr]], %subreg.sub_8bit
-    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[INSERT_SUBREG]], 1, implicit-def $eflags
+    ; CHECK: [[MOVZX32rr8_:%[0-9]+]]:gr32 = MOVZX32rr8 [[SETCCr]]
+    ; CHECK: [[AND32ri8_:%[0-9]+]]:gr32 = AND32ri8 [[MOVZX32rr8_]], 1, implicit-def $eflags
     ; CHECK: $eax = COPY [[AND32ri8_]]
     ; CHECK: RET 0, implicit $eax
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
-    %2(s1) = G_ICMP intpred(sle), %0(s32), %1
-    %3(s32) = G_ZEXT %2(s1)
+    %4(s8) = G_ICMP intpred(sle), %0(s32), %1
+    %5(s32) = G_CONSTANT i32 1
+    %6(s32) = G_ANYEXT %4(s8)
+    %3(s32) = G_AND %6, %5
     $eax = COPY %3(s32)
     RET 0, implicit $eax
 
 ...

llvm/test/CodeGen/X86/GlobalISel/select-phi.mir

bb.1.entry:
     liveins: $edi, $edx, $esi
 
     %0:gpr(s32) = COPY $edi
     %3:gpr(s32) = COPY $esi
     %1:gpr(s8) = G_TRUNC %3(s32)
     %4:gpr(s32) = COPY $edx
     %2:gpr(s8) = G_TRUNC %4(s32)
     %5:gpr(s32) = G_CONSTANT i32 0
-    %6:gpr(s1) = G_ICMP intpred(sgt), %0(s32), %5
+    %8:gpr(s8) = G_ICMP intpred(sgt), %0(s32), %5
+    %6:gpr(s1) = G_TRUNC %8(s8)
     G_BRCOND %6(s1), %bb.3
 
   bb.2.cond.false:
     successors: %bb.3(0x80000000)
 
 
   bb.3.cond.end:
     %7:gpr(s8) = G_PHI %2(s8), %bb.2, %1(s8), %bb.1
bb.1.entry:
     liveins: $edi, $edx, $esi
 
     %0:gpr(s32) = COPY $edi
     %3:gpr(s32) = COPY $esi
     %1:gpr(s16) = G_TRUNC %3(s32)
     %4:gpr(s32) = COPY $edx
     %2:gpr(s16) = G_TRUNC %4(s32)
     %5:gpr(s32) = G_CONSTANT i32 0
-    %6:gpr(s1) = G_ICMP intpred(sgt), %0(s32), %5
+    %8:gpr(s8) = G_ICMP intpred(sgt), %0(s32), %5
+    %6:gpr(s1) = G_TRUNC %8(s8)
     G_BRCOND %6(s1), %bb.3
 
   bb.2.cond.false:
     successors: %bb.3(0x80000000)
 
 
   bb.3.cond.end:
     %7:gpr(s16) = G_PHI %2(s16), %bb.2, %1(s16), %bb.1

 tracksRegLiveness: true
 registers:
   - { id: 0, class: gpr, preferred-register: '' }
   - { id: 1, class: gpr, preferred-register: '' }
   - { id: 2, class: gpr, preferred-register: '' }
   - { id: 3, class: gpr, preferred-register: '' }
   - { id: 4, class: gpr, preferred-register: '' }
   - { id: 5, class: gpr, preferred-register: '' }
+  - { id: 6, class: gpr, preferred-register: '' }
 body:             |
   ; ALL-LABEL: name: test_i32
   ; ALL: bb.0.entry:
   ; ALL:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; ALL:   liveins: $edi, $edx, $esi
   ; ALL:   [[COPY:%[0-9]+]]:gr32 = COPY $edi
   ; ALL:   [[COPY1:%[0-9]+]]:gr32 = COPY $esi
   ; ALL:   [[COPY2:%[0-9]+]]:gr32 = COPY $edx
body:             |
   bb.1.entry:
     successors: %bb.2(0x40000000), %bb.3(0x40000000)
     liveins: $edi, $edx, $esi
 
     %0(s32) = COPY $edi
     %1(s32) = COPY $esi
     %2(s32) = COPY $edx
     %3(s32) = G_CONSTANT i32 0
-    %4(s1) = G_ICMP intpred(sgt), %0(s32), %3
+    %6(s8) = G_ICMP intpred(sgt), %0(s32), %3
+    %4:gpr(s1) = G_TRUNC %6(s8)
     G_BRCOND %4(s1), %bb.2
     G_BR %bb.3
 
   bb.2.cond.true:
     successors: %bb.4(0x80000000)
 
     G_BR %bb.4
 

 tracksRegLiveness: true
 registers:
   - { id: 0, class: gpr, preferred-register: '' }
   - { id: 1, class: gpr, preferred-register: '' }
   - { id: 2, class: gpr, preferred-register: '' }
   - { id: 3, class: gpr, preferred-register: '' }
   - { id: 4, class: gpr, preferred-register: '' }
   - { id: 5, class: gpr, preferred-register: '' }
+  - { id: 6, class: gpr, preferred-register: '' }
 body:             |
   ; ALL-LABEL: name: test_i64
   ; ALL: bb.0.entry:
   ; ALL:   successors: %bb.1(0x40000000), %bb.2(0x40000000)
   ; ALL:   liveins: $edi, $rdx, $rsi
   ; ALL:   [[COPY:%[0-9]+]]:gr32 = COPY $edi
   ; ALL:   [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
   ; ALL:   [[COPY2:%[0-9]+]]:gr64 = COPY $rdx
body:             |
   bb.1.entry:
     successors: %bb.2(0x40000000), %bb.3(0x40000000)
     liveins: $edi, $rdx, $rsi
 
     %0(s32) = COPY $edi
     %1(s64) = COPY $rsi
     %2(s64) = COPY $rdx
     %3(s32) = G_CONSTANT i32 0
-    %4(s1) = G_ICMP intpred(sgt), %0(s32), %3
+    %6(s8) = G_ICMP intpred(sgt), %0(s32), %3
+    %4:gpr(s1) = G_TRUNC %6(s8)
     G_BRCOND %4(s1), %bb.2
     G_BR %bb.3
 
   bb.2.cond.true:
     successors: %bb.4(0x80000000)
 
     G_BR %bb.4
 
bb.1.entry:
     liveins: $edi, $xmm0, $xmm1
 
     %0:gpr(s32) = COPY $edi
     %3:vecr(s128) = COPY $xmm0
     %1:vecr(s32) = G_TRUNC %3(s128)
     %4:vecr(s128) = COPY $xmm1
     %2:vecr(s32) = G_TRUNC %4(s128)
     %5:gpr(s32) = G_CONSTANT i32 0
-    %6:gpr(s1) = G_ICMP intpred(sgt), %0(s32), %5
+    %9:gpr(s8) = G_ICMP intpred(sgt), %0(s32), %5
+    %6:gpr(s1) = G_TRUNC %9(s8)
     G_BRCOND %6(s1), %bb.3
 
   bb.2.cond.false:
     successors: %bb.3(0x80000000)
 
   bb.3.cond.end:
     %7:vecr(s32) = G_PHI %2(s32), %bb.2, %1(s32), %bb.1
     %8:vecr(s128) = G_ANYEXT %7(s32)
bb.1.entry:
     liveins: $edi, $xmm0, $xmm1
 
     %0:gpr(s32) = COPY $edi
     %3:vecr(s128) = COPY $xmm0
     %1:vecr(s64) = G_TRUNC %3(s128)
     %4:vecr(s128) = COPY $xmm1
     %2:vecr(s64) = G_TRUNC %4(s128)
     %5:gpr(s32) = G_CONSTANT i32 0
-    %6:gpr(s1) = G_ICMP intpred(sgt), %0(s32), %5
+    %9:gpr(s8) = G_ICMP intpred(sgt), %0(s32), %5
+    %6:gpr(s1) = G_TRUNC %9(s8)
     G_BRCOND %6(s1), %bb.3
 
   bb.2.cond.false:
     successors: %bb.3(0x80000000)
 
   bb.3.cond.end:
     %7:vecr(s64) = G_PHI %2(s64), %bb.2, %1(s64), %bb.1
     %8:vecr(s128) = G_ANYEXT %7(s64)
     $xmm0 = COPY %8(s128)
     RET 0, implicit $xmm0
 
 ...