[SVE] No need to AND(X, 0x1) when truncating a scalable mask

[cameron.mcinally]

Summary

We're using CMPNE(X, 0) to truncate promoted fixed width masks to scalable masks. My confidence is moderate on this, but I think the preceding AND(X, 0x1) is unnecessary. I wouldn't expect a false element with tops bits set.

Did I miss something??

[efriedma]

The semantics of TRUNCATE is that it throws away the high bits. For most types, this happens implicitly, but we have to be a little more explicit here. We can't assume a the operand to a random TRUNCATE to i1 is produced by a compare operation.

If it turns out the operand to the AND is actually an all-ones/all-zeros value, we can optimize out the AND, sure.

[cameron.mcinally]

Ah, okay. So it's not safe to assume that the truncate to i1 is a mask. Makes sense.

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

static bool isVShiftRImm(SDValue Op, EVT VT, bool isNarrow, int64_t &Cnt) {
   return (Cnt >= 1 && Cnt <= (isNarrow ? ElementBits / 2 : ElementBits));
 }
 
 SDValue AArch64TargetLowering::LowerTRUNCATE(SDValue Op,
                                              SelectionDAG &DAG) const {
   EVT VT = Op.getValueType();
 
   if (VT.getScalarType() == MVT::i1) {
-    // Lower i1 truncate to `(x & 1) != 0`.
+    // Lower i1 truncate to `x != 0`.
     SDLoc dl(Op);
     EVT OpVT = Op.getOperand(0).getValueType();
     SDValue Zero = DAG.getConstant(0, dl, OpVT);
-    SDValue One = DAG.getConstant(1, dl, OpVT);
-    SDValue And = DAG.getNode(ISD::AND, dl, OpVT, Op.getOperand(0), One);
-    return DAG.getSetCC(dl, VT, And, Zero, ISD::SETNE);
+    return DAG.getSetCC(dl, VT, Op.getOperand(0), Zero, ISD::SETNE);
   }
 
   if (!VT.isVector() || VT.isScalableVector())
     return SDValue();
 
   if (useSVEForFixedLengthVectorVT(Op.getOperand(0).getValueType()))
     return LowerFixedLengthVectorTruncateToSVE(Op, DAG);
 

llvm/test/CodeGen/AArch64/sve-trunc.ll

 }
 
 ; Truncating to i1 requires convert it to a cmp
 
 define <vscale x 2 x i1> @trunc_i64toi1(<vscale x 2 x i64> %in) {
 ; CHECK-LABEL: trunc_i64toi1:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.d
-; CHECK-NEXT:    and z0.d, z0.d, #0x1
 ; CHECK-NEXT:    cmpne p0.d, p0/z, z0.d, #0
 ; CHECK-NEXT:    ret
 entry:
   %out = trunc <vscale x 2 x i64> %in to <vscale x 2 x i1>
   ret <vscale x 2 x i1> %out
 }
 
 define <vscale x 4 x i1> @trunc_i64toi1_split(<vscale x 4 x i64> %in) {
 ; CHECK-LABEL: trunc_i64toi1_split:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.d
-; CHECK-NEXT:    and z1.d, z1.d, #0x1
-; CHECK-NEXT:    and z0.d, z0.d, #0x1
 ; CHECK-NEXT:    cmpne p1.d, p0/z, z1.d, #0
 ; CHECK-NEXT:    cmpne p0.d, p0/z, z0.d, #0
 ; CHECK-NEXT:    uzp1 p0.s, p0.s, p1.s
 ; CHECK-NEXT:    ret
 entry:
   %out = trunc <vscale x 4 x i64> %in to <vscale x 4 x i1>
   ret <vscale x 4 x i1> %out
 }
 
 define <vscale x 8 x i1> @trunc_i64toi1_split2(<vscale x 8 x i64> %in) {
 ; CHECK-LABEL: trunc_i64toi1_split2:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.d
-; CHECK-NEXT:    and z3.d, z3.d, #0x1
-; CHECK-NEXT:    and z2.d, z2.d, #0x1
-; CHECK-NEXT:    and z1.d, z1.d, #0x1
-; CHECK-NEXT:    and z0.d, z0.d, #0x1
 ; CHECK-NEXT:    cmpne p1.d, p0/z, z3.d, #0
 ; CHECK-NEXT:    cmpne p2.d, p0/z, z2.d, #0
-; CHECK-NEXT:    uzp1 p1.s, p2.s, p1.s
-; CHECK-NEXT:    cmpne p2.d, p0/z, z1.d, #0
+; CHECK-NEXT:    cmpne p3.d, p0/z, z1.d, #0
 ; CHECK-NEXT:    cmpne p0.d, p0/z, z0.d, #0
-; CHECK-NEXT:    uzp1 p0.s, p0.s, p2.s
+; CHECK-NEXT:    uzp1 p1.s, p2.s, p1.s
+; CHECK-NEXT:    uzp1 p0.s, p0.s, p3.s
 ; CHECK-NEXT:    uzp1 p0.h, p0.h, p1.h
 ; CHECK-NEXT:    ret
 entry:
   %out = trunc <vscale x 8 x i64> %in to <vscale x 8 x i1>
   ret <vscale x 8 x i1> %out
 }
 
 define <vscale x 16 x i1> @trunc_i64toi1_split3(<vscale x 16 x i64> %in) {
 ; CHECK-LABEL: trunc_i64toi1_split3:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    str x29, [sp, #-16]! // 8-byte Folded Spill
 ; CHECK-NEXT:    addvl sp, sp, #-1
 ; CHECK-NEXT:    str p4, [sp, #7, mul vl] // 2-byte Folded Spill
 ; CHECK-NEXT:    .cfi_escape 0x0f, 0x0c, 0x8f, 0x00, 0x11, 0x10, 0x22, 0x11, 0x08, 0x92, 0x2e, 0x00, 0x1e, 0x22 // sp + 16 + 8 * VG
 ; CHECK-NEXT:    .cfi_offset w29, -16
 ; CHECK-NEXT:    ptrue p0.d
-; CHECK-NEXT:    and z7.d, z7.d, #0x1
-; CHECK-NEXT:    and z6.d, z6.d, #0x1
-; CHECK-NEXT:    and z5.d, z5.d, #0x1
-; CHECK-NEXT:    and z4.d, z4.d, #0x1
-; CHECK-NEXT:    and z3.d, z3.d, #0x1
-; CHECK-NEXT:    and z2.d, z2.d, #0x1
 ; CHECK-NEXT:    cmpne p1.d, p0/z, z7.d, #0
 ; CHECK-NEXT:    cmpne p2.d, p0/z, z6.d, #0
 ; CHECK-NEXT:    cmpne p3.d, p0/z, z5.d, #0
 ; CHECK-NEXT:    cmpne p4.d, p0/z, z4.d, #0
-; CHECK-NEXT:    and z1.d, z1.d, #0x1
-; CHECK-NEXT:    and z0.d, z0.d, #0x1
 ; CHECK-NEXT:    uzp1 p1.s, p2.s, p1.s
 ; CHECK-NEXT:    cmpne p2.d, p0/z, z3.d, #0
 ; CHECK-NEXT:    uzp1 p3.s, p4.s, p3.s
 ; CHECK-NEXT:    cmpne p4.d, p0/z, z2.d, #0
 ; CHECK-NEXT:    uzp1 p2.s, p4.s, p2.s
 ; CHECK-NEXT:    cmpne p4.d, p0/z, z1.d, #0
 ; CHECK-NEXT:    cmpne p0.d, p0/z, z0.d, #0
 ; CHECK-NEXT:    uzp1 p0.s, p0.s, p4.s
entry:
   ret <vscale x 16 x i1> %out
 }
 
 
 define <vscale x 4 x i1> @trunc_i32toi1(<vscale x 4 x i32> %in) {
 ; CHECK-LABEL: trunc_i32toi1:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.s
-; CHECK-NEXT:    and z0.s, z0.s, #0x1
 ; CHECK-NEXT:    cmpne p0.s, p0/z, z0.s, #0
 ; CHECK-NEXT:    ret
 entry:
   %out = trunc <vscale x 4 x i32> %in to <vscale x 4 x i1>
   ret <vscale x 4 x i1> %out
 }
 
 define <vscale x 8 x i1> @trunc_i16toi1(<vscale x 8 x i16> %in) {
 ; CHECK-LABEL: trunc_i16toi1:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.h
-; CHECK-NEXT:    and z0.h, z0.h, #0x1
 ; CHECK-NEXT:    cmpne p0.h, p0/z, z0.h, #0
 ; CHECK-NEXT:    ret
 entry:
   %out = trunc <vscale x 8 x i16> %in to <vscale x 8 x i1>
   ret <vscale x 8 x i1> %out
 }
 
 define <vscale x 16 x i1> @trunc_i8toi1(<vscale x 16 x i8> %in) {
 ; CHECK-LABEL: trunc_i8toi1:
 ; CHECK:       // %bb.0: // %entry
 ; CHECK-NEXT:    ptrue p0.b
-; CHECK-NEXT:    and z0.b, z0.b, #0x1
 ; CHECK-NEXT:    cmpne p0.b, p0/z, z0.b, #0
 ; CHECK-NEXT:    ret
 entry:
   %out = trunc <vscale x 16 x i8> %in to <vscale x 16 x i1>
   ret <vscale x 16 x i1> %out
 }