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Differential D85400

[RISCV] add the MC layer support of riscv vector Zvqmac extension
Needs ReviewPublic

Authored by StephenFan on Aug 5 2020, 11:53 PM.

Details

Reviewers
HsiangKai
rogfer01
evandro
fpallares
simoncook
rkruppe
Summary

change the VALUr_IV_V_X to VALUr_IV_X, change the 0b111111 to 0b111111

Diff Detail

Event Timeline

StephenFan created this revision.Aug 5 2020, 11:53 PM
Herald added a project: Restricted Project. · View Herald TranscriptAug 5 2020, 11:53 PM
Herald added subscribers: llvm-commits, luismarques, apazos and 23 others. · View Herald Transcript
StephenFan requested review of this revision.Aug 5 2020, 11:53 PM
Herald added a subscriber: MaskRay. · View Herald TranscriptAug 5 2020, 11:53 PM
Harbormaster completed remote builds in B67256: Diff 283496.Aug 6 2020, 12:07 AM
HsiangKai added a comment.Aug 17 2020, 8:10 PM

These instructions and encodings are already removed from vector specification. We could postpone the patch after these instructions are included in the vector specification.

llvm/lib/Target/RISCV/RISCVInstrInfoV.td
921

0b111111

922

VALUr_IV_X

StephenFan updated this revision to Diff 286781.Aug 20 2020, 4:47 AM
StephenFan edited the summary of this revision. (Show Details)
Harbormaster completed remote builds in B69014: Diff 286781.Aug 20 2020, 4:48 AM
StephenFan updated this revision to Diff 286783.Aug 20 2020, 4:52 AM
StephenFan marked an inline comment as done.
StephenFan edited the summary of this revision. (Show Details)

change the VALUr_IV_V_X to VALUr_IV_X, change the 0b111111 to 0b111111

StephenFan updated this revision to Diff 288208.Aug 26 2020, 11:28 PM
StephenFan marked an inline comment as done.

rebaes to the latest upstream master

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
8 lines
8 lines
2 lines
2 lines
2 lines
test/
MC/
RISCV/
rvv/
93 lines

Diff 286783

llvm/lib/Target/RISCV/RISCV.td

Show First 20 Lines • Show All 149 Lines • ▼ Show 20 Lines
def FeatureStdExtV def FeatureStdExtV
: SubtargetFeature<"experimental-v", "HasStdExtV", "true", : SubtargetFeature<"experimental-v", "HasStdExtV", "true",
"'V' (Vector Instructions)", "'V' (Vector Instructions)",
[FeatureStdExtF]>; [FeatureStdExtF]>;
def HasStdExtV : Predicate<"Subtarget->hasStdExtV()">, def HasStdExtV : Predicate<"Subtarget->hasStdExtV()">,
AssemblerPredicate<(all_of FeatureStdExtV), AssemblerPredicate<(all_of FeatureStdExtV),
"'V' (Vector Instructions)">; "'V' (Vector Instructions)">;
def FeatureExtZvqmac
: SubtargetFeature<"experimental-zvqmac", "HasStdExtZvqmac", "true",
"'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)",
[FeatureStdExtV]>;
def HasStdExtZvqmac : Predicate<"Subtarget->hasStdExtZvqmac()">,
AssemblerPredicate<(all_of FeatureExtZvqmac),
"'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)">;
def Feature64Bit def Feature64Bit
: SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">; : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
def IsRV64 : Predicate<"Subtarget->is64Bit()">, def IsRV64 : Predicate<"Subtarget->is64Bit()">,
AssemblerPredicate<(all_of Feature64Bit), AssemblerPredicate<(all_of Feature64Bit),
"RV64I Base Instruction Set">; "RV64I Base Instruction Set">;
def IsRV32 : Predicate<"!Subtarget->is64Bit()">, def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
AssemblerPredicate<(all_of (not Feature64Bit)), AssemblerPredicate<(all_of (not Feature64Bit)),
"RV32I Base Instruction Set">; "RV32I Base Instruction Set">;
▲ Show 20 Lines • Show All 86 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoV.td

Show First 20 Lines • Show All 907 Lines • ▼ Show 20 Lines def VMV#nf#R_V : RVInstV<0b100111, !add(nf, -1), OPIVI, (outs VRegOp:$vd),
(ins VRegOp:$vs2), "vmv" # nf # "r.v", (ins VRegOp:$vs2), "vmv" # nf # "r.v",
"$vd, $vs2"> { "$vd, $vs2"> {
let Uses = []; let Uses = [];
let vm = 1; let vm = 1;
} }
} }
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0 } // hasSideEffects = 0, mayLoad = 0, mayStore = 0
} // Predicates = [HasStdExtV] } // Predicates = [HasStdExtV]
// Vector Quad-Widening Integer Multiply-Add Instructions (Extension Zvqmac)
let Predicates = [HasStdExtZvqmac], Constraints = "@earlyclobber $vd", RVVConstraint = WidenV in {
defm VQMACCU_V : VALUr_IV_V_X<"vqmaccu", 0b111100>;
defm VQMACC_V : VALUr_IV_V_X<"vqmacc", 0b111101>;
defm VQMACCSU_V : VALUr_IV_V_X<"vqmaccsu", 0b111111>;
HsiangKaiUnsubmitted
Done
ReplyInline Actions

0b111111

HsiangKai: 0b111111
defm VQMACCUS_V : VALUr_IV_X<"vqmaccus", 0b111110>;
HsiangKaiUnsubmitted
Done
ReplyInline Actions

VALUr_IV_X

HsiangKai: VALUr_IV_X
} // Predicates = [HasStdExtZvqmac], Constraints = "@earlyclobber $vd", RVVConstraint = WidenV
No newline at end of file

llvm/lib/Target/RISCV/RISCVSchedRocket32.td

Show All 11 Lines
// Rocket machine model for scheduling and other instruction cost heuristics. // Rocket machine model for scheduling and other instruction cost heuristics.
def Rocket32Model : SchedMachineModel { def Rocket32Model : SchedMachineModel {
let MicroOpBufferSize = 0; // Explicitly set to zero since Rocket is in-order. let MicroOpBufferSize = 0; // Explicitly set to zero since Rocket is in-order.
let IssueWidth = 1; // 1 micro-ops are dispatched per cycle. let IssueWidth = 1; // 1 micro-ops are dispatched per cycle.
let LoadLatency = 3; let LoadLatency = 3;
let MispredictPenalty = 3; let MispredictPenalty = 3;
let CompleteModel = 1; let CompleteModel = 1;
let UnsupportedFeatures = [HasStdExtV]; let UnsupportedFeatures = [HasStdExtV, HasStdExtZvqmac];
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Define each kind of processor resource and number available. // Define each kind of processor resource and number available.
// Modeling each pipeline as a ProcResource using the BufferSize = 0 since // Modeling each pipeline as a ProcResource using the BufferSize = 0 since
// Rocket is in-order. // Rocket is in-order.
▲ Show 20 Lines • Show All 199 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVSchedRocket64.td

Show All 10 Lines
// This works with MachineScheduler. See MCSchedule.h for details. // This works with MachineScheduler. See MCSchedule.h for details.
// Rocket machine model for scheduling and other instruction cost heuristics. // Rocket machine model for scheduling and other instruction cost heuristics.
def Rocket64Model : SchedMachineModel { def Rocket64Model : SchedMachineModel {
let MicroOpBufferSize = 0; // Explicitly set to zero since Rocket is in-order. let MicroOpBufferSize = 0; // Explicitly set to zero since Rocket is in-order.
let IssueWidth = 1; // 1 micro-ops are dispatched per cycle. let IssueWidth = 1; // 1 micro-ops are dispatched per cycle.
let LoadLatency = 3; let LoadLatency = 3;
let MispredictPenalty = 3; let MispredictPenalty = 3;
let UnsupportedFeatures = [HasStdExtV]; let UnsupportedFeatures = [HasStdExtV, HasStdExtZvqmac];
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// Define each kind of processor resource and number available. // Define each kind of processor resource and number available.
// Modeling each pipeline as a ProcResource using the BufferSize = 0 since // Modeling each pipeline as a ProcResource using the BufferSize = 0 since
// Rocket is in-order. // Rocket is in-order.
▲ Show 20 Lines • Show All 201 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVSubtarget.h

Show First 20 Lines • Show All 45 Lines • ▼ Show 20 Linesclass RISCVSubtarget : public RISCVGenSubtargetInfo {
bool HasStdExtZbf = false; bool HasStdExtZbf = false;
bool HasStdExtZbm = false; bool HasStdExtZbm = false;
bool HasStdExtZbp = false; bool HasStdExtZbp = false;
bool HasStdExtZbr = false; bool HasStdExtZbr = false;
bool HasStdExtZbs = false; bool HasStdExtZbs = false;
bool HasStdExtZbt = false; bool HasStdExtZbt = false;
bool HasStdExtZbproposedc = false; bool HasStdExtZbproposedc = false;
bool HasStdExtV = false; bool HasStdExtV = false;
bool HasStdExtZvqmac = false;
bool HasRV64 = false; bool HasRV64 = false;
bool IsRV32E = false; bool IsRV32E = false;
bool EnableLinkerRelax = false; bool EnableLinkerRelax = false;
bool EnableRVCHintInstrs = true; bool EnableRVCHintInstrs = true;
bool EnableSaveRestore = false; bool EnableSaveRestore = false;
unsigned XLen = 32; unsigned XLen = 32;
MVT XLenVT = MVT::i32; MVT XLenVT = MVT::i32;
RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown; RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
▲ Show 20 Lines • Show All 45 Lines • ▼ Show 20 Linespublic:
bool hasStdExtZbf() const { return HasStdExtZbf; } bool hasStdExtZbf() const { return HasStdExtZbf; }
bool hasStdExtZbm() const { return HasStdExtZbm; } bool hasStdExtZbm() const { return HasStdExtZbm; }
bool hasStdExtZbp() const { return HasStdExtZbp; } bool hasStdExtZbp() const { return HasStdExtZbp; }
bool hasStdExtZbr() const { return HasStdExtZbr; } bool hasStdExtZbr() const { return HasStdExtZbr; }
bool hasStdExtZbs() const { return HasStdExtZbs; } bool hasStdExtZbs() const { return HasStdExtZbs; }
bool hasStdExtZbt() const { return HasStdExtZbt; } bool hasStdExtZbt() const { return HasStdExtZbt; }
bool hasStdExtZbproposedc() const { return HasStdExtZbproposedc; } bool hasStdExtZbproposedc() const { return HasStdExtZbproposedc; }
bool hasStdExtV() const { return HasStdExtV; } bool hasStdExtV() const { return HasStdExtV; }
bool hasStdExtZvqmac() const { return HasStdExtZvqmac; }
bool is64Bit() const { return HasRV64; } bool is64Bit() const { return HasRV64; }
bool isRV32E() const { return IsRV32E; } bool isRV32E() const { return IsRV32E; }
bool enableLinkerRelax() const { return EnableLinkerRelax; } bool enableLinkerRelax() const { return EnableLinkerRelax; }
bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; } bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; }
bool enableSaveRestore() const { return EnableSaveRestore; } bool enableSaveRestore() const { return EnableSaveRestore; }
MVT getXLenVT() const { return XLenVT; } MVT getXLenVT() const { return XLenVT; }
unsigned getXLen() const { return XLen; } unsigned getXLen() const { return XLen; }
RISCVABI::ABI getTargetABI() const { return TargetABI; } RISCVABI::ABI getTargetABI() const { return TargetABI; }
Show All 21 Lines

llvm/test/MC/RISCV/rvv/zvqmac.s

  • This file was added.
# RUN: llvm-mc -triple=riscv64 -show-encoding --mattr=+experimental-zvqmac %s \
# RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
# RUN: not llvm-mc -triple=riscv64 -show-encoding %s 2>&1 \
# RUN: | FileCheck %s --check-prefix=CHECK-ERROR
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zvqmac %s \
# RUN: | llvm-objdump -d --mattr=+experimental-zvqmac - \
# RUN: | FileCheck %s --check-prefix=CHECK-INST
# RUN: llvm-mc -triple=riscv64 -filetype=obj --mattr=+experimental-zvqmac %s \
# RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
vqmaccu.vv v8, v20, v4, v0.t
# CHECK-INST: vqmaccu.vv v8, v20, v4, v0.t
# CHECK-ENCODING: [0x57,0x04,0x4a,0xf0]
# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
# CHECK-UNKNOWN: 57 04 4a f0 <unknown>
vqmaccu.vv v8, v20, v4
# CHECK-INST: vqmaccu.vv v8, v20, v4
# CHECK-ENCODING: [0x57,0x04,0x4a,0xf2]
# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
# CHECK-UNKNOWN: 57 04 4a f2 <unknown>
vqmaccu.vx v8, a0, v4, v0.t
# CHECK-INST: vqmaccu.vx v8, a0, v4, v0.t
# CHECK-ENCODING: [0x57,0x44,0x45,0xf0]
# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
# CHECK-UNKNOWN: 57 44 45 f0 <unknown>
vqmaccu.vx v8, a0, v4
# CHECK-INST: vqmaccu.vx v8, a0, v4
# CHECK-ENCODING: [0x57,0x44,0x45,0xf2]
# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
# CHECK-UNKNOWN: 57 44 45 f2 <unknown>
vqmacc.vv v8, v20, v4, v0.t
# CHECK-INST: vqmacc.vv v8, v20, v4, v0.t
# CHECK-ENCODING: [0x57,0x04,0x4a,0xf4]
# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
# CHECK-UNKNOWN: 57 04 4a f4 <unknown>
vqmacc.vv v8, v20, v4
# CHECK-INST: vqmacc.vv v8, v20, v4
# CHECK-ENCODING: [0x57,0x04,0x4a,0xf6]
# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
# CHECK-UNKNOWN: 57 04 4a f6 <unknown>
vqmacc.vx v8, a0, v4, v0.t
# CHECK-INST: vqmacc.vx v8, a0, v4, v0.t
# CHECK-ENCODING: [0x57,0x44,0x45,0xf4]
# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
# CHECK-UNKNOWN: 57 44 45 f4 <unknown>
vqmacc.vx v8, a0, v4
# CHECK-INST: vqmacc.vx v8, a0, v4
# CHECK-ENCODING: [0x57,0x44,0x45,0xf6]
# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
# CHECK-UNKNOWN: 57 44 45 f6 <unknown>
vqmaccsu.vv v8, v20, v4, v0.t
# CHECK-INST: vqmaccsu.vv v8, v20, v4, v0.t
# CHECK-ENCODING: [0x57,0x04,0x4a,0xfc]
# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
# CHECK-UNKNOWN: 57 04 4a fc <unknown>
vqmaccsu.vv v8, v20, v4
# CHECK-INST: vqmaccsu.vv v8, v20, v4
# CHECK-ENCODING: [0x57,0x04,0x4a,0xfe]
# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
# CHECK-UNKNOWN: 57 04 4a fe <unknown>
vqmaccsu.vx v8, a0, v4, v0.t
# CHECK-INST: vqmaccsu.vx v8, a0, v4, v0.t
# CHECK-ENCODING: [0x57,0x44,0x45,0xfc]
# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
# CHECK-UNKNOWN: 57 44 45 fc <unknown>
vqmaccsu.vx v8, a0, v4
# CHECK-INST: vqmaccsu.vx v8, a0, v4
# CHECK-ENCODING: [0x57,0x44,0x45,0xfe]
# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
# CHECK-UNKNOWN: 57 44 45 fe <unknown>
vqmaccus.vx v8, a0, v4, v0.t
# CHECK-INST: vqmaccus.vx v8, a0, v4, v0.t
# CHECK-ENCODING: [0x57,0x44,0x45,0xf8]
# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
# CHECK-UNKNOWN: 57 44 45 f8 <unknown>
vqmaccus.vx v8, a0, v4
# CHECK-INST: vqmaccus.vx v8, a0, v4
# CHECK-ENCODING: [0x57,0x44,0x45,0xfa]
# CHECK-ERROR: 'Zvqmac' (Vector Quad-Widening Integer Multiply-Add Instructions)
# CHECK-UNKNOWN: 57 44 45 fa <unknown>