TableGen/GlobalISel: Allow inst matcher to check multiple opcodes

[arsenm]

Summary

This is to initially handleg immAllOnesV, which should match
G_BUILD_VECTOR or G_BUILD_VECTOR_TRUNC. In the future, it could be
used for other patterns cases that map to multiple G_* instructions,
such as G_ADD and G_PTR_ADD.

[foad]

llvm/utils/TableGen/GlobalISelEmitter.cpp

1674–1678

Typo "one several".

[arsenm]

Fix comment

[paquette]

Could we have more than 2 possible choices for opcodes? Would it make sense to make this take an arbitrary number of alternatives?

Maybe something like

/// - InsnID - Instruction ID
/// - NumChoices - Number of possible opcodes
/// - Opcode1, Opcode2, Opcode3, ... OpcodeNumChoices - Possible opcodes, ordered by preference
GIM_CheckOpcodeWithAlternatives

I can't think of anything off the top of my head, but it could be useful I suppose.

[arsenm]

In D85203#2200542, @paquette wrote:

Could we have more than 2 possible choices for opcodes? Would it make sense to make this take an arbitrary number of alternatives?

Maybe something like

/// - InsnID - Instruction ID
/// - NumChoices - Number of possible opcodes
/// - Opcode1, Opcode2, Opcode3, ... OpcodeNumChoices - Possible opcodes, ordered by preference
GIM_CheckOpcodeWithAlternatives

I can't think of anything off the top of my head, but it could be useful I suppose.

I considered doing it this way, but I couldn't come up with a case where we would need more than 2. I'd rather use the simpler thing unless there's a concrete need

[paquette]

In D85203#2200550, @arsenm wrote:

In D85203#2200542, @paquette wrote:

Could we have more than 2 possible choices for opcodes? Would it make sense to make this take an arbitrary number of alternatives?

Maybe something like

/// - InsnID - Instruction ID
/// - NumChoices - Number of possible opcodes
/// - Opcode1, Opcode2, Opcode3, ... OpcodeNumChoices - Possible opcodes, ordered by preference
GIM_CheckOpcodeWithAlternatives

I can't think of anything off the top of my head, but it could be useful I suppose.

I considered doing it this way, but I couldn't come up with a case where we would need more than 2. I'd rather use the simpler thing unless there's a concrete need

Ok, that seems reasonable to me.

Do you think you can change the name from GIM_CheckOpcode2 to something more descriptive?

[arsenm]

Rename

[paquette]

LGTM

[arsenm]

Fix breaking SwitchOpcode optimization

[arsenm]

116affb18dfc8c48ad0bd5134b42a51e34ad6fd8

llvm/include/llvm/CodeGen/GlobalISel/InstructionSelector.h

enum {
   /// Check the feature bits
   /// - Expected features
   GIM_CheckFeatures,
 
   /// Check the opcode on the specified instruction
   /// - InsnID - Instruction ID
   /// - Expected opcode
   GIM_CheckOpcode,
+
+  /// Check the opcode on the specified instruction, checking 2 acceptable
+  /// alternatives.
+  /// - InsnID - Instruction ID
+  /// - Expected opcode
+  /// - Alternative expected opcode
+  GIM_CheckOpcodeIsEither,
+
   /// Check the instruction has the right number of operands
   /// - InsnID - Instruction ID
   /// - Expected number of operands
   GIM_CheckNumOperands,
   /// Check an immediate predicate on the specified instruction
   /// - InsnID - Instruction ID
   /// - The predicate to test
   GIM_CheckI64ImmPredicate,

llvm/include/llvm/CodeGen/GlobalISel/InstructionSelectorImpl.h

case GIM_CheckFeatures: {
       if ((AvailableFeatures & ISelInfo.FeatureBitsets[ExpectedBitsetID]) !=
           ISelInfo.FeatureBitsets[ExpectedBitsetID]) {
         if (handleReject() == RejectAndGiveUp)
           return false;
       }
       break;
     }
 
-    case GIM_CheckOpcode: {
+    case GIM_CheckOpcode:
+    case GIM_CheckOpcodeIsEither: {
       int64_t InsnID = MatchTable[CurrentIdx++];
-      int64_t Expected = MatchTable[CurrentIdx++];
+      int64_t Expected0 = MatchTable[CurrentIdx++];
+      int64_t Expected1 = -1;
+      if (MatcherOpcode == GIM_CheckOpcodeIsEither)
+        Expected1 = MatchTable[CurrentIdx++];
 
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
       unsigned Opcode = State.MIs[InsnID]->getOpcode();
 
       DEBUG_WITH_TYPE(TgtInstructionSelector::getName(),
-                      dbgs() << CurrentIdx << ": GIM_CheckOpcode(MIs[" << InsnID
-                             << "], ExpectedOpcode=" << Expected
-                             << ") // Got=" << Opcode << "\n");
-      if (Opcode != Expected) {
+        << "], ExpectedOpcode=" << Expected0;
+        if (MatcherOpcode == GIM_CheckOpcodeIsEither)
+          dbgs() << " || " << Expected1;
+        dbgs() << ") // Got=" << Opcode << "\n";
+      );
+
+      if (Opcode != Expected0 && Opcode != Expected1) {
         if (handleReject() == RejectAndGiveUp)
           return false;
       }
       break;
     }
-
     case GIM_SwitchOpcode: {
       int64_t InsnID = MatchTable[CurrentIdx++];
       int64_t LowerBound = MatchTable[CurrentIdx++];
       int64_t UpperBound = MatchTable[CurrentIdx++];
       int64_t Default = MatchTable[CurrentIdx++];
 
       assert(State.MIs[InsnID] != nullptr && "Used insn before defined");
       const int64_t Opcode = State.MIs[InsnID]->getOpcode();

llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll

 ; GFX6-NEXT:    s_and_b32 s1, s4, s1
 ; GFX6-NEXT:    s_or_b32 s1, s2, s1
 ; GFX6-NEXT:    s_xor_b32 s1, s1, -1
 ; GFX6-NEXT:    s_and_b32 s0, s0, s1
 ; GFX6-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: s_andn2_v2i16:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_xor_b32 s0, s3, -1
-; GFX9-NEXT:    s_and_b32 s0, s2, s0
+; GFX9-NEXT:    s_andn2_b32 s0, s2, s3
 ; GFX9-NEXT:    ; return to shader part epilog
   %not.src1 = xor <2 x i16> %src1, <i16 -1, i16 -1>
   %and = and <2 x i16> %src0, %not.src1
   %cast = bitcast <2 x i16> %and to i32
   ret i32 %cast
 }
 
 define amdgpu_ps i32 @s_andn2_v2i16_commute(<2 x i16> inreg %src0, <2 x i16> inreg %src1) {
 ; GFX6-LABEL: s_andn2_v2i16_commute:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_mov_b32 s1, 0xffff
 ; GFX6-NEXT:    s_and_b32 s2, s2, s1
 ; GFX6-NEXT:    s_lshl_b32 s0, s3, 16
 ; GFX6-NEXT:    s_or_b32 s0, s0, s2
 ; GFX6-NEXT:    s_lshl_b32 s2, s5, 16
 ; GFX6-NEXT:    s_and_b32 s1, s4, s1
 ; GFX6-NEXT:    s_or_b32 s1, s2, s1
 ; GFX6-NEXT:    s_xor_b32 s1, s1, -1
 ; GFX6-NEXT:    s_and_b32 s0, s1, s0
 ; GFX6-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: s_andn2_v2i16_commute:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_xor_b32 s0, s3, -1
-; GFX9-NEXT:    s_and_b32 s0, s0, s2
+; GFX9-NEXT:    s_andn2_b32 s0, s2, s3
 ; GFX9-NEXT:    ; return to shader part epilog
   %not.src1 = xor <2 x i16> %src1, <i16 -1, i16 -1>
   %and = and <2 x i16> %not.src1, %src0
   %cast = bitcast <2 x i16> %and to i32
   ret i32 %cast
 }
 
 define amdgpu_ps { i32, i32 } @s_andn2_v2i16_multi_use(<2 x i16> inreg %src0, <2 x i16> inreg %src1) {
 ; GFX6-LABEL: s_andn2_v2i16_multi_use:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_mov_b32 s1, 0xffff
 ; GFX6-NEXT:    s_and_b32 s2, s2, s1
 ; GFX6-NEXT:    s_lshl_b32 s0, s3, 16
 ; GFX6-NEXT:    s_or_b32 s0, s0, s2
 ; GFX6-NEXT:    s_lshl_b32 s2, s5, 16
 ; GFX6-NEXT:    s_and_b32 s1, s4, s1
 ; GFX6-NEXT:    s_or_b32 s1, s2, s1
 ; GFX6-NEXT:    s_xor_b32 s1, s1, -1
 ; GFX6-NEXT:    s_and_b32 s0, s0, s1
 ; GFX6-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: s_andn2_v2i16_multi_use:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_xor_b32 s1, s3, -1
-; GFX9-NEXT:    s_and_b32 s0, s2, s1
+; GFX9-NEXT:    s_andn2_b32 s0, s2, s3
 ; GFX9-NEXT:    ; return to shader part epilog
   %not.src1 = xor <2 x i16> %src1, <i16 -1, i16 -1>
   %and = and <2 x i16> %src0, %not.src1
 
   %cast.0 = bitcast <2 x i16> %and to i32
   %cast.1 = bitcast <2 x i16> %not.src1 to i32
   %insert.0 = insertvalue { i32, i32 } undef, i32 %cast.0, 0
   %insert.1 = insertvalue { i32, i32 } %insert.0, i32 %cast.1, 1

 ; GFX6-NEXT:    s_or_b32 s1, s3, s1
 ; GFX6-NEXT:    s_xor_b32 s1, s1, -1
 ; GFX6-NEXT:    s_and_b32 s0, s0, s1
 ; GFX6-NEXT:    s_and_b32 s1, s2, s1
 ; GFX6-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: s_andn2_v2i16_multi_foldable_use:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_xor_b32 s1, s4, -1
-; GFX9-NEXT:    s_and_b32 s0, s2, s1
-; GFX9-NEXT:    s_and_b32 s1, s3, s1
+; GFX9-NEXT:    s_andn2_b32 s0, s2, s4
+; GFX9-NEXT:    s_andn2_b32 s1, s3, s4
 ; GFX9-NEXT:    ; return to shader part epilog
   %not.src2 = xor <2 x i16> %src2, <i16 -1, i16 -1>
   %and0 = and <2 x i16> %src0, %not.src2
   %and1 = and <2 x i16> %src1, %not.src2
 
   %cast.0 = bitcast <2 x i16> %and0 to i32
   %cast.1 = bitcast <2 x i16> %and1 to i32
   %insert.0 = insertvalue { i32, i32 } undef, i32 %cast.0, 0

llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll

 ; GFX6-NEXT:    s_and_b32 s1, s4, s1
 ; GFX6-NEXT:    s_or_b32 s1, s2, s1
 ; GFX6-NEXT:    s_xor_b32 s1, s1, -1
 ; GFX6-NEXT:    s_or_b32 s0, s0, s1
 ; GFX6-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: s_orn2_v2i16:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_xor_b32 s0, s3, -1
-; GFX9-NEXT:    s_or_b32 s0, s2, s0
+; GFX9-NEXT:    s_orn2_b32 s0, s2, s3
 ; GFX9-NEXT:    ; return to shader part epilog
   %not.src1 = xor <2 x i16> %src1, <i16 -1, i16 -1>
   %or = or <2 x i16> %src0, %not.src1
   %cast = bitcast <2 x i16> %or to i32
   ret i32 %cast
 }
 
 define amdgpu_ps i32 @s_orn2_v2i16_commute(<2 x i16> inreg %src0, <2 x i16> inreg %src1) {
 ; GFX6-LABEL: s_orn2_v2i16_commute:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_mov_b32 s1, 0xffff
 ; GFX6-NEXT:    s_and_b32 s2, s2, s1
 ; GFX6-NEXT:    s_lshl_b32 s0, s3, 16
 ; GFX6-NEXT:    s_or_b32 s0, s0, s2
 ; GFX6-NEXT:    s_lshl_b32 s2, s5, 16
 ; GFX6-NEXT:    s_and_b32 s1, s4, s1
 ; GFX6-NEXT:    s_or_b32 s1, s2, s1
 ; GFX6-NEXT:    s_xor_b32 s1, s1, -1
 ; GFX6-NEXT:    s_or_b32 s0, s1, s0
 ; GFX6-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: s_orn2_v2i16_commute:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_xor_b32 s0, s3, -1
-; GFX9-NEXT:    s_or_b32 s0, s0, s2
+; GFX9-NEXT:    s_orn2_b32 s0, s2, s3
 ; GFX9-NEXT:    ; return to shader part epilog
   %not.src1 = xor <2 x i16> %src1, <i16 -1, i16 -1>
   %or = or <2 x i16> %not.src1, %src0
   %cast = bitcast <2 x i16> %or to i32
   ret i32 %cast
 }
 
 define amdgpu_ps { i32, i32 } @s_orn2_v2i16_multi_use(<2 x i16> inreg %src0, <2 x i16> inreg %src1) {
 ; GFX6-LABEL: s_orn2_v2i16_multi_use:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_mov_b32 s1, 0xffff
 ; GFX6-NEXT:    s_and_b32 s2, s2, s1
 ; GFX6-NEXT:    s_lshl_b32 s0, s3, 16
 ; GFX6-NEXT:    s_or_b32 s0, s0, s2
 ; GFX6-NEXT:    s_lshl_b32 s2, s5, 16
 ; GFX6-NEXT:    s_and_b32 s1, s4, s1
 ; GFX6-NEXT:    s_or_b32 s1, s2, s1
 ; GFX6-NEXT:    s_xor_b32 s1, s1, -1
 ; GFX6-NEXT:    s_or_b32 s0, s0, s1
 ; GFX6-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: s_orn2_v2i16_multi_use:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_xor_b32 s1, s3, -1
-; GFX9-NEXT:    s_or_b32 s0, s2, s1
+; GFX9-NEXT:    s_orn2_b32 s0, s2, s3
 ; GFX9-NEXT:    ; return to shader part epilog
   %not.src1 = xor <2 x i16> %src1, <i16 -1, i16 -1>
   %or = or <2 x i16> %src0, %not.src1
 
   %cast.0 = bitcast <2 x i16> %or to i32
   %cast.1 = bitcast <2 x i16> %not.src1 to i32
   %insert.0 = insertvalue { i32, i32 } undef, i32 %cast.0, 0
   %insert.1 = insertvalue { i32, i32 } %insert.0, i32 %cast.1, 1

 ; GFX6-NEXT:    s_or_b32 s1, s3, s1
 ; GFX6-NEXT:    s_xor_b32 s1, s1, -1
 ; GFX6-NEXT:    s_or_b32 s0, s0, s1
 ; GFX6-NEXT:    s_or_b32 s1, s2, s1
 ; GFX6-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: s_orn2_v2i16_multi_foldable_use:
 ; GFX9:       ; %bb.0:
-; GFX9-NEXT:    s_xor_b32 s1, s4, -1
-; GFX9-NEXT:    s_or_b32 s0, s2, s1
-; GFX9-NEXT:    s_or_b32 s1, s3, s1
+; GFX9-NEXT:    s_orn2_b32 s0, s2, s4
+; GFX9-NEXT:    s_orn2_b32 s1, s3, s4
 ; GFX9-NEXT:    ; return to shader part epilog
   %not.src2 = xor <2 x i16> %src2, <i16 -1, i16 -1>
   %or0 = or <2 x i16> %src0, %not.src2
   %or1 = or <2 x i16> %src1, %not.src2
 
   %cast.0 = bitcast <2 x i16> %or0 to i32
   %cast.1 = bitcast <2 x i16> %or1 to i32
   %insert.0 = insertvalue { i32, i32 } undef, i32 %cast.0, 0

llvm/test/TableGen/GlobalISelEmitter-immAllZeroOne.td

 // RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefixes=GISEL-NOOPT,GISEL %s
 // RUN: llvm-tblgen -gen-global-isel -warn-on-skipped-patterns -optimize-match-table=true -I %p/../../include -I %p/Common %s -o - | FileCheck -check-prefixes=GISEL-OPT,GISEL %s
 
 include "llvm/Target/Target.td"
 include "GlobalISelEmitterCommon.td"
 
+// GISEL-OPT: GIM_SwitchOpcode
+// GISEL-OPT-NEXT: /*TargetOpcode::G_SHL*/
+// GISEL-OPT-NEXT: /*TargetOpcode::G_LSHR*/
+// GISEL-OPT-NEXT: // Label
 
+
+// GISEL-OPT: GIM_Try,
 // GISEL-OPT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
-// GISEL-OPT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BUILD_VECTOR,
+// GISEL-OPT: GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC,
 // GISEL-OPT: GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
 
+// GISEL-OPT: GIM_Try,
 // GISEL-OPT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
-// GISEL-OPT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BUILD_VECTOR,
+// GISEL-OPT: GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC,
 // GISEL-OPT: GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
 
 
 
 // GISEL-NOOPT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_LSHR,
 // GISEL-NOOPT: // MIs[0] Operand 2
 // GISEL-NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
 // GISEL-NOOPT-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
-// GISEL-NOOPT-NEXT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BUILD_VECTOR,
+// GISEL-NOOPT-NEXT: GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC,
 // GISEL-NOOPT-NEXT: GIM_CheckIsBuildVectorAllOnes, /*MI*/1,
 // GISEL-NOOPT-NEXT: // MIs[1] Operand 0
 // GISEL-NOOPT-NEXT: GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s16,
 // GISEL-NOOPT-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1,
 // GISEL-NOOPT-NEXT: // (srl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src0, immAllOnesV:{ *:[v4i16] })  =>  (VFOOONES:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src0)
 def VFOOONES : I<(outs VecReg128:$dst), (ins VecReg128:$src0),
   [(set v4i32:$dst, (srl v4i32:$src0, (v4i16 immAllOnesV)))]
 >;
 
 
 // GISEL-NOOPT: GIM_CheckOpcode, /*MI*/0, TargetOpcode::G_SHL,
 // GISEL-NOOPT: // MIs[0] Operand 2
 // GISEL-NOOPT-NEXT: GIM_CheckType, /*MI*/0, /*Op*/2, /*Type*/GILLT_v4s16,
 // GISEL-NOOPT-NEXT: GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1]
-// GISEL-NOOPT-NEXT: GIM_CheckOpcode, /*MI*/1, TargetOpcode::G_BUILD_VECTOR,
+// GISEL-NOOPT-NEXT: GIM_CheckOpcodeIsEither, /*MI*/1, TargetOpcode::G_BUILD_VECTOR, TargetOpcode::G_BUILD_VECTOR_TRUNC,
 // GISEL-NOOPT-NEXT: GIM_CheckIsBuildVectorAllZeros, /*MI*/1,
 // GISEL-NOOPT-NEXT: // MIs[1] Operand 0
 // GISEL-NOOPT-NEXT: GIM_CheckType, /*MI*/1, /*Op*/0, /*Type*/GILLT_v4s16,
 // GISEL-NOOPT-NEXT: GIM_CheckIsSafeToFold, /*InsnID*/1,
 // GISEL-NOOPT-NEXT: // (shl:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src0, immAllZerosV:{ *:[v4i16] })  =>  (VFOOZERO:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src0)
 def VFOOZERO : I<(outs VecReg128:$dst), (ins VecReg128:$src0),
   [(set v4i32:$dst, (shl v4i32:$src0, (v4i16 immAllZerosV)))]
 >;

llvm/utils/TableGen/GlobalISelEmitter.cpp

 std::string
 PredicateListMatcher<PredicateMatcher>::getNoPredicateComment() const {
   return "No instruction predicates";
 }
 
 /// Generates code to check the opcode of an instruction.
 class InstructionOpcodeMatcher : public InstructionPredicateMatcher {
 protected:
-  const CodeGenInstruction *I;
+  // Allow matching one to several, similar opcodes that share properties. This
+  // is to handle patterns where one SelectionDAG operation maps to multiple
+  // GlobalISel ones (e.g. G_BUILD_VECTOR and G_BUILD_VECTOR_TRUNC). The first
+  // is treated as the canonical opcode.
+  SmallVector<const CodeGenInstruction *, 2> Insts;
 
   static DenseMap<const CodeGenInstruction *, unsigned> OpcodeValues;
 
+
+  MatchTableRecord getInstValue(const CodeGenInstruction *I) const {
+    const auto VI = OpcodeValues.find(I);
+    if (VI != OpcodeValues.end())
+      return MatchTable::NamedValue(I->Namespace, I->TheDef->getName(),
+                                    VI->second);
+    return MatchTable::NamedValue(I->Namespace, I->TheDef->getName());
+  }
+
 public:
   static void initOpcodeValuesMap(const CodeGenTarget &Target) {
     OpcodeValues.clear();
 
     unsigned OpcodeValue = 0;
     for (const CodeGenInstruction *I : Target.getInstructionsByEnumValue())
       OpcodeValues[I] = OpcodeValue++;
   }
 
-  InstructionOpcodeMatcher(unsigned InsnVarID, const CodeGenInstruction *I)
-      : InstructionPredicateMatcher(IPM_Opcode, InsnVarID), I(I) {}
+  InstructionOpcodeMatcher(unsigned InsnVarID,
+                           ArrayRef<const CodeGenInstruction *> I)
+      : InstructionPredicateMatcher(IPM_Opcode, InsnVarID),
+        Insts(I.begin(), I.end()) {
+    assert((Insts.size() == 1 || Insts.size() == 2) &&
+           "unexpected number of opcode alternatives");
+  }
 
   static bool classof(const PredicateMatcher *P) {
     return P->getKind() == IPM_Opcode;
   }
 
   bool isIdentical(const PredicateMatcher &B) const override {
     return InstructionPredicateMatcher::isIdentical(B) &&
-           I == cast<InstructionOpcodeMatcher>(&B)->I;
+           Insts == cast<InstructionOpcodeMatcher>(&B)->Insts;
+  }
+
+  bool hasValue() const override {
+    return Insts.size() == 1 && OpcodeValues.count(Insts[0]);
   }
+
+  // TODO: This is used for the SwitchMatcher optimization. We should be able to
+  // return a list of the opcodes to match.
   MatchTableRecord getValue() const override {
+    assert(Insts.size() == 1);
+
+    const CodeGenInstruction *I = Insts[0];
     const auto VI = OpcodeValues.find(I);
     if (VI != OpcodeValues.end())
       return MatchTable::NamedValue(I->Namespace, I->TheDef->getName(),
                                     VI->second);
     return MatchTable::NamedValue(I->Namespace, I->TheDef->getName());
   }
-  bool hasValue() const override { return OpcodeValues.count(I); }
 
   void emitPredicateOpcodes(MatchTable &Table,
                             RuleMatcher &Rule) const override {
-    Table << MatchTable::Opcode("GIM_CheckOpcode") << MatchTable::Comment("MI")
-          << MatchTable::IntValue(InsnVarID) << getValue()
-          << MatchTable::LineBreak;
+    StringRef CheckType = Insts.size() == 1 ?
+                          "GIM_CheckOpcode" : "GIM_CheckOpcodeIsEither";
+    Table << MatchTable::Opcode(CheckType) << MatchTable::Comment("MI")
+          << MatchTable::IntValue(InsnVarID);
+
+    for (const CodeGenInstruction *I : Insts)
+      Table << getInstValue(I);
+    Table << MatchTable::LineBreak;
   }
 
   /// Compare the priority of this object and B.
   ///
   /// Returns true if this object is more important than B.
   bool
   isHigherPriorityThan(const InstructionPredicateMatcher &B) const override {
     if (InstructionPredicateMatcher::isHigherPriorityThan(B))
       return true;
     if (B.InstructionPredicateMatcher::isHigherPriorityThan(*this))
       return false;
 
     // Prioritize opcodes for cosmetic reasons in the generated source. Although
     // this is cosmetic at the moment, we may want to drive a similar ordering
     // using instruction frequency information to improve compile time.
     if (const InstructionOpcodeMatcher *BO =
             dyn_cast<InstructionOpcodeMatcher>(&B))
-      return I->TheDef->getName() < BO->I->TheDef->getName();
+      return Insts[0]->TheDef->getName() < BO->Insts[0]->TheDef->getName();
 
     return false;
   };
 
   bool isConstantInstruction() const {
-    return I->TheDef->getName() == "G_CONSTANT";
+    return Insts.size() == 1 && Insts[0]->TheDef->getName() == "G_CONSTANT";
+  }
+
+  // The first opcode is the canonical opcode, and later are alternatives.
+  StringRef getOpcode() const {
+    return Insts[0]->TheDef->getName();
+  }
+
+  ArrayRef<const CodeGenInstruction *> getAlternativeOpcodes() {
+    return Insts;
   }
 
-  StringRef getOpcode() const { return I->TheDef->getName(); }
-  bool isVariadicNumOperands() const { return I->Operands.isVariadic; }
+  bool isVariadicNumOperands() const {
+    // If one is variadic, they all should be.
+    return Insts[0]->Operands.isVariadic;
+  }
 
   StringRef getOperandType(unsigned OpIdx) const {
-    return I->Operands[OpIdx].OperandType;
+    // Types expected to be uniform for all alternatives.
+    return Insts[0]->Operands[OpIdx].OperandType;
   }
 };
 
 DenseMap<const CodeGenInstruction *, unsigned>
     InstructionOpcodeMatcher::OpcodeValues;
 
 class InstructionNumOperandsMatcher final : public InstructionPredicateMatcher {
   unsigned NumOperands = 0;
if (auto *ChildDefInit = dyn_cast<DefInit>(SrcChild->getLeafValue())) {
 
     const bool ImmAllOnesV = ChildRec->getName() == "immAllOnesV";
     if (ImmAllOnesV || ChildRec->getName() == "immAllZerosV") {
       auto MaybeInsnOperand = OM.addPredicate<InstructionOperandMatcher>(
           InsnMatcher.getRuleMatcher(), SrcChild->getName(), false);
       InstructionOperandMatcher &InsnOperand = **MaybeInsnOperand;
 
       ValueTypeByHwMode VTy = ChildTypes.front().getValueTypeByHwMode();
+
+      const CodeGenInstruction &BuildVector
+        = Target.getInstruction(RK.getDef("G_BUILD_VECTOR"));
+      const CodeGenInstruction &BuildVectorTrunc
+        = Target.getInstruction(RK.getDef("G_BUILD_VECTOR_TRUNC"));
+
+      // Treat G_BUILD_VECTOR as the canonical opcode, and G_BUILD_VECTOR_TRUNC
+      // as an alternative.
       InsnOperand.getInsnMatcher().addPredicate<InstructionOpcodeMatcher>(
-          &Target.getInstruction(RK.getDef("G_BUILD_VECTOR")));
+      makeArrayRef({&BuildVector, &BuildVectorTrunc}));
 
       // TODO: Handle both G_BUILD_VECTOR and G_BUILD_VECTOR_TRUNC We could
       // theoretically not emit any opcode check, but getOpcodeMatcher currently
       // has to succeed.
       OperandMatcher &OM =
           InsnOperand.getInsnMatcher().addOperand(0, "", TempOpIdx);
       if (auto Error =
               OM.addTypeCheckPredicate(VTy, false /* OperandIsAPointer */))