Update AMDGPU testcases after bebe6a6449811e877f7eba3f1798ddd1fa83e440

[paquette]

Summary

I didn't build AMDGPU locally so I didn't see this.

(logic_op (op x...), (op y...)) -> (op (logic_op x, y))

kicks in here.

Double-checking that this looks good.

[arsenm]

This immediate diff is better, but I'm not sure what the interaction with D85201 is going to be

[paquette]

I applied D85201 and the tests passed without any conflicts/updates, so it seems fine.

[arsenm]

In D85761#2210966, @paquette wrote:

I applied D85201 and the tests passed without any conflicts/updates, so it seems fine.

Probably also need D85203 and D85202. I guess fix the build for now and I'll have to sort this out when I rebase

llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll

 ; GFX6-NEXT:    s_xor_b32 s0, s3, -1
 ; GFX6-NEXT:    s_and_b32 s0, s2, s0
 ; GFX6-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: s_andn2_i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_mov_b32 s0, 0xffff
 ; GFX9-NEXT:    s_and_b32 s1, s3, s0
-; GFX9-NEXT:    s_xor_b32 s1, s1, s0
-; GFX9-NEXT:    s_and_b32 s2, s2, s0
-; GFX9-NEXT:    s_and_b32 s0, s1, s0
+; GFX9-NEXT:    s_xor_b32 s0, s1, s0
 ; GFX9-NEXT:    s_and_b32 s0, s2, s0
+; GFX9-NEXT:    s_bfe_u32 s0, s0, 0x100000
 ; GFX9-NEXT:    ; return to shader part epilog
   %not.src1 = xor i16 %src1, -1
   %and = and i16 %src0, %not.src1
   ret i16 %and
 }
 
 define amdgpu_ps i16 @s_andn2_i16_commute(i16 inreg %src0, i16 inreg %src1) {
 ; GFX6-LABEL: s_andn2_i16_commute:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_xor_b32 s0, s3, -1
 ; GFX6-NEXT:    s_and_b32 s0, s0, s2
 ; GFX6-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: s_andn2_i16_commute:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_mov_b32 s0, 0xffff
 ; GFX9-NEXT:    s_and_b32 s1, s3, s0
-; GFX9-NEXT:    s_xor_b32 s1, s1, s0
-; GFX9-NEXT:    s_and_b32 s1, s1, s0
-; GFX9-NEXT:    s_and_b32 s0, s2, s0
-; GFX9-NEXT:    s_and_b32 s0, s1, s0
+; GFX9-NEXT:    s_xor_b32 s0, s1, s0
+; GFX9-NEXT:    s_and_b32 s0, s0, s2
+; GFX9-NEXT:    s_bfe_u32 s0, s0, 0x100000
 ; GFX9-NEXT:    ; return to shader part epilog
   %not.src1 = xor i16 %src1, -1
   %and = and i16 %not.src1, %src0
   ret i16 %and
 }
 
 define amdgpu_ps { i16, i16 } @s_andn2_i16_multi_use(i16 inreg %src0, i16 inreg %src1) {
 ; GFX6-LABEL: s_andn2_i16_multi_use:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_xor_b32 s1, s3, -1
 ; GFX6-NEXT:    s_and_b32 s0, s2, s1
 ; GFX6-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: s_andn2_i16_multi_use:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_mov_b32 s0, 0xffff
 ; GFX9-NEXT:    s_and_b32 s1, s3, s0
 ; GFX9-NEXT:    s_xor_b32 s1, s1, s0
-; GFX9-NEXT:    s_and_b32 s2, s2, s0
-; GFX9-NEXT:    s_and_b32 s0, s1, s0
-; GFX9-NEXT:    s_and_b32 s0, s2, s0
+; GFX9-NEXT:    s_and_b32 s0, s2, s1
+; GFX9-NEXT:    s_bfe_u32 s0, s0, 0x100000
 ; GFX9-NEXT:    ; return to shader part epilog
   %not.src1 = xor i16 %src1, -1
   %and = and i16 %src0, %not.src1
   %insert.0 = insertvalue { i16, i16 } undef, i16 %and, 0
   %insert.1 = insertvalue { i16, i16 } %insert.0, i16 %not.src1, 1
   ret { i16, i16 } %insert.1
 }
 

llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll

 ; GFX6-NEXT:    s_xor_b32 s0, s3, -1
 ; GFX6-NEXT:    s_or_b32 s0, s2, s0
 ; GFX6-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: s_orn2_i16:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_mov_b32 s0, 0xffff
 ; GFX9-NEXT:    s_and_b32 s1, s3, s0
-; GFX9-NEXT:    s_xor_b32 s1, s1, s0
-; GFX9-NEXT:    s_and_b32 s2, s2, s0
-; GFX9-NEXT:    s_and_b32 s0, s1, s0
+; GFX9-NEXT:    s_xor_b32 s0, s1, s0
 ; GFX9-NEXT:    s_or_b32 s0, s2, s0
+; GFX9-NEXT:    s_bfe_u32 s0, s0, 0x100000
 ; GFX9-NEXT:    ; return to shader part epilog
   %not.src1 = xor i16 %src1, -1
   %or = or i16 %src0, %not.src1
   ret i16 %or
 }
 
 define amdgpu_ps i16 @s_orn2_i16_commute(i16 inreg %src0, i16 inreg %src1) {
 ; GFX6-LABEL: s_orn2_i16_commute:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_xor_b32 s0, s3, -1
 ; GFX6-NEXT:    s_or_b32 s0, s0, s2
 ; GFX6-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: s_orn2_i16_commute:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_mov_b32 s0, 0xffff
 ; GFX9-NEXT:    s_and_b32 s1, s3, s0
-; GFX9-NEXT:    s_xor_b32 s1, s1, s0
-; GFX9-NEXT:    s_and_b32 s1, s1, s0
-; GFX9-NEXT:    s_and_b32 s0, s2, s0
-; GFX9-NEXT:    s_or_b32 s0, s1, s0
+; GFX9-NEXT:    s_xor_b32 s0, s1, s0
+; GFX9-NEXT:    s_or_b32 s0, s0, s2
+; GFX9-NEXT:    s_bfe_u32 s0, s0, 0x100000
 ; GFX9-NEXT:    ; return to shader part epilog
   %not.src1 = xor i16 %src1, -1
   %or = or i16 %not.src1, %src0
   ret i16 %or
 }
 
 define amdgpu_ps { i16, i16 } @s_orn2_i16_multi_use(i16 inreg %src0, i16 inreg %src1) {
 ; GFX6-LABEL: s_orn2_i16_multi_use:
 ; GFX6:       ; %bb.0:
 ; GFX6-NEXT:    s_xor_b32 s1, s3, -1
 ; GFX6-NEXT:    s_or_b32 s0, s2, s1
 ; GFX6-NEXT:    ; return to shader part epilog
 ;
 ; GFX9-LABEL: s_orn2_i16_multi_use:
 ; GFX9:       ; %bb.0:
 ; GFX9-NEXT:    s_mov_b32 s0, 0xffff
 ; GFX9-NEXT:    s_and_b32 s1, s3, s0
 ; GFX9-NEXT:    s_xor_b32 s1, s1, s0
-; GFX9-NEXT:    s_and_b32 s2, s2, s0
-; GFX9-NEXT:    s_and_b32 s0, s1, s0
-; GFX9-NEXT:    s_or_b32 s0, s2, s0
+; GFX9-NEXT:    s_or_b32 s0, s2, s1
+; GFX9-NEXT:    s_bfe_u32 s0, s0, 0x100000
 ; GFX9-NEXT:    ; return to shader part epilog
   %not.src1 = xor i16 %src1, -1
   %or = or i16 %src0, %not.src1
   %insert.0 = insertvalue { i16, i16 } undef, i16 %or, 0
   %insert.1 = insertvalue { i16, i16 } %insert.0, i16 %not.src1, 1
   ret { i16, i16 } %insert.1
 }
 

llvm/test/CodeGen/AMDGPU/GlobalISel/xnor.ll

 ; GFX7-NEXT:    s_and_b32 s2, s2, s4
 ; GFX7-NEXT:    s_or_b32 s1, s1, s2
 ; GFX7-NEXT:    s_xor_b32 s0, s0, s1
 ; GFX7-NEXT:    s_xor_b32 s0, s0, -1
 ; GFX7-NEXT:    ; return to shader part epilog
 ;
 ; GFX8-LABEL: scalar_xnor_v2i16_one_use:
 ; GFX8:       ; %bb.0: ; %entry
+; GFX8-NEXT:    s_xor_b32 s0, s0, s1
 ; GFX8-NEXT:    s_mov_b32 s2, 0xffff
-; GFX8-NEXT:    s_lshr_b32 s5, s0, 16
-; GFX8-NEXT:    s_lshr_b32 s6, s1, 16
-; GFX8-NEXT:    s_and_b32 s4, s0, s2
-; GFX8-NEXT:    s_and_b32 s0, s1, s2
-; GFX8-NEXT:    s_and_b32 s5, s5, s2
-; GFX8-NEXT:    s_and_b32 s1, s6, s2
+; GFX8-NEXT:    s_lshr_b32 s1, s0, 16
 ; GFX8-NEXT:    s_mov_b32 s3, s2
-; GFX8-NEXT:    s_xor_b64 s[0:1], s[4:5], s[0:1]
+; GFX8-NEXT:    s_and_b32 s0, s0, s2
+; GFX8-NEXT:    s_and_b32 s1, s1, s2
 ; GFX8-NEXT:    s_and_b64 s[0:1], s[0:1], s[2:3]
 ; GFX8-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
 ; GFX8-NEXT:    s_lshl_b32 s1, s1, 16
 ; GFX8-NEXT:    s_and_b32 s0, s0, s2
 ; GFX8-NEXT:    s_or_b32 s0, s1, s0
 ; GFX8-NEXT:    ; return to shader part epilog
 ;
 ; GFX900-LABEL: scalar_xnor_v2i16_one_use:

 ; GFX7-NEXT:    s_mov_b32 s4, -1
 ; GFX7-NEXT:    s_mov_b32 s5, s4
 ; GFX7-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
 ; GFX7-NEXT:    s_xor_b64 s[0:1], s[0:1], s[4:5]
 ; GFX7-NEXT:    ; return to shader part epilog
 ;
 ; GFX8-LABEL: scalar_xnor_v4i16_one_use:
 ; GFX8:       ; %bb.0:
+; GFX8-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
 ; GFX8-NEXT:    s_mov_b32 s4, 0xffff
-; GFX8-NEXT:    s_lshr_b32 s5, s0, 16
-; GFX8-NEXT:    s_and_b32 s7, s5, s4
+; GFX8-NEXT:    s_lshr_b32 s3, s0, 16
 ; GFX8-NEXT:    s_lshr_b32 s5, s1, 16
-; GFX8-NEXT:    s_and_b32 s6, s0, s4
+; GFX8-NEXT:    s_and_b32 s2, s0, s4
 ; GFX8-NEXT:    s_and_b32 s0, s1, s4
 ; GFX8-NEXT:    s_and_b32 s1, s5, s4
-; GFX8-NEXT:    s_lshr_b32 s5, s2, 16
-; GFX8-NEXT:    s_and_b32 s8, s2, s4
-; GFX8-NEXT:    s_and_b32 s9, s5, s4
-; GFX8-NEXT:    s_lshr_b32 s5, s3, 16
-; GFX8-NEXT:    s_and_b32 s2, s3, s4
-; GFX8-NEXT:    s_and_b32 s3, s5, s4
-; GFX8-NEXT:    s_xor_b64 s[6:7], s[6:7], s[8:9]
 ; GFX8-NEXT:    s_mov_b32 s5, s4
-; GFX8-NEXT:    s_xor_b64 s[0:1], s[0:1], s[2:3]
-; GFX8-NEXT:    s_and_b64 s[2:3], s[6:7], s[4:5]
+; GFX8-NEXT:    s_and_b32 s3, s3, s4
+; GFX8-NEXT:    s_and_b64 s[2:3], s[2:3], s[4:5]
 ; GFX8-NEXT:    s_and_b64 s[0:1], s[0:1], s[4:5]
 ; GFX8-NEXT:    s_xor_b64 s[2:3], s[2:3], s[4:5]
 ; GFX8-NEXT:    s_xor_b64 s[6:7], s[0:1], s[4:5]
 ; GFX8-NEXT:    s_and_b32 s1, s2, s4
 ; GFX8-NEXT:    s_lshl_b32 s0, s3, 16
 ; GFX8-NEXT:    s_or_b32 s0, s0, s1
 ; GFX8-NEXT:    s_lshl_b32 s1, s7, 16
 ; GFX8-NEXT:    s_and_b32 s2, s6, s4