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Differential D85205

AMDGPU: Add flag to disable promotion of uniform i16 ops
ClosedPublic

Authored by arsenm on Aug 4 2020, 5:44 AM.

Details

Reviewers
rampitec
kerbowa
foad
mbrkusanin
Petar.Avramovic
Summary

This should really be disable for GlobalISel. However, the fallback
only re-runs the selection passes, and doesn't go back and rerun any
codegen IR passes. I haven't come up with a good solution to this
problem.

Diff Detail

Revision Contents

Diff 282885

llvm/test/CodeGen/AMDGPU/GlobalISel/andn2.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6 %s ; RUN: llc -global-isel -amdgpu-codegenprepare-widen-16-bit-ops=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6 %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s ; RUN: llc -global-isel -amdgpu-codegenprepare-widen-16-bit-ops=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s
define amdgpu_ps i32 @s_andn2_i32(i32 inreg %src0, i32 inreg %src1) { define amdgpu_ps i32 @s_andn2_i32(i32 inreg %src0, i32 inreg %src1) {
; GCN-LABEL: s_andn2_i32: ; GCN-LABEL: s_andn2_i32:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_andn2_b32 s0, s2, s3 ; GCN-NEXT: s_andn2_b32 s0, s2, s3
; GCN-NEXT: ; return to shader part epilog ; GCN-NEXT: ; return to shader part epilog
%not.src1 = xor i32 %src1, -1 %not.src1 = xor i32 %src1, -1
%and = and i32 %src0, %not.src1 %and = and i32 %src0, %not.src1
▲ Show 20 Lines • Show All 179 Lines • ▼ Show 20 Lines
; GCN-NEXT: s_andn2_b64 s[0:1], s[2:3], s[4:5] ; GCN-NEXT: s_andn2_b64 s[0:1], s[2:3], s[4:5]
; GCN-NEXT: ; return to shader part epilog ; GCN-NEXT: ; return to shader part epilog
%not.src1 = xor <2 x i32> %src1, <i32 -1, i32 -1> %not.src1 = xor <2 x i32> %src1, <i32 -1, i32 -1>
%and = and <2 x i32> %not.src1, %src0 %and = and <2 x i32> %not.src1, %src0
ret <2 x i32> %and ret <2 x i32> %and
} }
define amdgpu_ps i16 @s_andn2_i16(i16 inreg %src0, i16 inreg %src1) { define amdgpu_ps i16 @s_andn2_i16(i16 inreg %src0, i16 inreg %src1) {
; GFX6-LABEL: s_andn2_i16: ; GCN-LABEL: s_andn2_i16:
; GFX6: ; %bb.0: ; GCN: ; %bb.0:
; GFX6-NEXT: s_andn2_b32 s0, s2, s3 ; GCN-NEXT: s_andn2_b32 s0, s2, s3
; GFX6-NEXT: ; return to shader part epilog ; GCN-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_andn2_i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_mov_b32 s0, 0xffff
; GFX9-NEXT: s_and_b32 s1, s3, s0
; GFX9-NEXT: s_xor_b32 s1, s1, s0
; GFX9-NEXT: s_and_b32 s2, s2, s0
; GFX9-NEXT: s_and_b32 s0, s1, s0
; GFX9-NEXT: s_and_b32 s0, s2, s0
; GFX9-NEXT: ; return to shader part epilog
%not.src1 = xor i16 %src1, -1 %not.src1 = xor i16 %src1, -1
%and = and i16 %src0, %not.src1 %and = and i16 %src0, %not.src1
ret i16 %and ret i16 %and
} }
define amdgpu_ps i16 @s_andn2_i16_commute(i16 inreg %src0, i16 inreg %src1) { define amdgpu_ps i16 @s_andn2_i16_commute(i16 inreg %src0, i16 inreg %src1) {
; GFX6-LABEL: s_andn2_i16_commute: ; GCN-LABEL: s_andn2_i16_commute:
; GFX6: ; %bb.0: ; GCN: ; %bb.0:
; GFX6-NEXT: s_andn2_b32 s0, s2, s3 ; GCN-NEXT: s_andn2_b32 s0, s2, s3
; GFX6-NEXT: ; return to shader part epilog ; GCN-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_andn2_i16_commute:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_mov_b32 s0, 0xffff
; GFX9-NEXT: s_and_b32 s1, s3, s0
; GFX9-NEXT: s_xor_b32 s1, s1, s0
; GFX9-NEXT: s_and_b32 s1, s1, s0
; GFX9-NEXT: s_and_b32 s0, s2, s0
; GFX9-NEXT: s_and_b32 s0, s1, s0
; GFX9-NEXT: ; return to shader part epilog
%not.src1 = xor i16 %src1, -1 %not.src1 = xor i16 %src1, -1
%and = and i16 %not.src1, %src0 %and = and i16 %not.src1, %src0
ret i16 %and ret i16 %and
} }
define amdgpu_ps { i16, i16 } @s_andn2_i16_multi_use(i16 inreg %src0, i16 inreg %src1) { define amdgpu_ps { i16, i16 } @s_andn2_i16_multi_use(i16 inreg %src0, i16 inreg %src1) {
; GFX6-LABEL: s_andn2_i16_multi_use: ; GCN-LABEL: s_andn2_i16_multi_use:
; GFX6: ; %bb.0: ; GCN: ; %bb.0:
; GFX6-NEXT: s_xor_b32 s1, s3, -1 ; GCN-NEXT: s_xor_b32 s1, s3, -1
; GFX6-NEXT: s_andn2_b32 s0, s2, s3 ; GCN-NEXT: s_andn2_b32 s0, s2, s3
; GFX6-NEXT: ; return to shader part epilog ; GCN-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_andn2_i16_multi_use:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_mov_b32 s0, 0xffff
; GFX9-NEXT: s_and_b32 s1, s3, s0
; GFX9-NEXT: s_xor_b32 s1, s1, s0
; GFX9-NEXT: s_and_b32 s2, s2, s0
; GFX9-NEXT: s_and_b32 s0, s1, s0
; GFX9-NEXT: s_and_b32 s0, s2, s0
; GFX9-NEXT: ; return to shader part epilog
%not.src1 = xor i16 %src1, -1 %not.src1 = xor i16 %src1, -1
%and = and i16 %src0, %not.src1 %and = and i16 %src0, %not.src1
%insert.0 = insertvalue { i16, i16 } undef, i16 %and, 0 %insert.0 = insertvalue { i16, i16 } undef, i16 %and, 0
%insert.1 = insertvalue { i16, i16 } %insert.0, i16 %not.src1, 1 %insert.1 = insertvalue { i16, i16 } %insert.0, i16 %not.src1, 1
ret { i16, i16 } %insert.1 ret { i16, i16 } %insert.1
} }
define amdgpu_ps { i16, i16 } @s_andn2_i16_multi_foldable_use(i16 inreg %src0, i16 inreg %src1, i16 inreg %src2) { define amdgpu_ps { i16, i16 } @s_andn2_i16_multi_foldable_use(i16 inreg %src0, i16 inreg %src1, i16 inreg %src2) {
; GFX6-LABEL: s_andn2_i16_multi_foldable_use: ; GCN-LABEL: s_andn2_i16_multi_foldable_use:
; GFX6: ; %bb.0: ; GCN: ; %bb.0:
; GFX6-NEXT: s_andn2_b32 s0, s2, s4 ; GCN-NEXT: s_andn2_b32 s0, s2, s4
; GFX6-NEXT: s_andn2_b32 s1, s3, s4 ; GCN-NEXT: s_andn2_b32 s1, s3, s4
; GFX6-NEXT: ; return to shader part epilog ; GCN-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_andn2_i16_multi_foldable_use:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_mov_b32 s1, 0xffff
; GFX9-NEXT: s_and_b32 s0, s4, s1
; GFX9-NEXT: s_xor_b32 s0, s0, s1
; GFX9-NEXT: s_and_b32 s2, s2, s1
; GFX9-NEXT: s_and_b32 s4, s0, s1
; GFX9-NEXT: s_and_b32 s1, s3, s1
; GFX9-NEXT: s_and_b32 s0, s2, s4
; GFX9-NEXT: s_and_b32 s1, s1, s4
; GFX9-NEXT: ; return to shader part epilog
%not.src2 = xor i16 %src2, -1 %not.src2 = xor i16 %src2, -1
%and0 = and i16 %src0, %not.src2 %and0 = and i16 %src0, %not.src2
%and1 = and i16 %src1, %not.src2 %and1 = and i16 %src1, %not.src2
%insert.0 = insertvalue { i16, i16 } undef, i16 %and0, 0 %insert.0 = insertvalue { i16, i16 } undef, i16 %and0, 0
%insert.1 = insertvalue { i16, i16 } %insert.0, i16 %and1, 1 %insert.1 = insertvalue { i16, i16 } %insert.0, i16 %and1, 1
ret { i16, i16 } %insert.1 ret { i16, i16 } %insert.1
} }
Show All 19 Lines; GCN-NEXT: ; return to shader part epilog
%not.src1 = xor i16 %src1, -1 %not.src1 = xor i16 %src1, -1
%and = and i16 %src0, %not.src1 %and = and i16 %src0, %not.src1
%zext = zext i16 %and to i32 %zext = zext i16 %and to i32
%cast.zext = bitcast i32 %zext to float %cast.zext = bitcast i32 %zext to float
ret float %cast.zext ret float %cast.zext
} }
define amdgpu_ps float @v_andn2_i16_vs(i16 %src0, i16 inreg %src1) { define amdgpu_ps float @v_andn2_i16_vs(i16 %src0, i16 inreg %src1) {
; GFX6-LABEL: v_andn2_i16_vs: ; GCN-LABEL: v_andn2_i16_vs:
; GFX6: ; %bb.0: ; GCN: ; %bb.0:
; GFX6-NEXT: s_xor_b32 s0, s2, -1 ; GCN-NEXT: s_xor_b32 s0, s2, -1
; GFX6-NEXT: v_and_b32_e32 v0, s0, v0 ; GCN-NEXT: v_and_b32_e32 v0, s0, v0
; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16 ; GCN-NEXT: v_bfe_u32 v0, v0, 0, 16
; GFX6-NEXT: ; return to shader part epilog ; GCN-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: v_andn2_i16_vs:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_mov_b32 s0, 0xffff
; GFX9-NEXT: s_and_b32 s1, s2, s0
; GFX9-NEXT: s_xor_b32 s0, s1, s0
; GFX9-NEXT: v_and_b32_e32 v0, s0, v0
; GFX9-NEXT: v_bfe_u32 v0, v0, 0, 16
; GFX9-NEXT: ; return to shader part epilog
%not.src1 = xor i16 %src1, -1 %not.src1 = xor i16 %src1, -1
%and = and i16 %src0, %not.src1 %and = and i16 %src0, %not.src1
%zext = zext i16 %and to i32 %zext = zext i16 %and to i32
%cast.zext = bitcast i32 %zext to float %cast.zext = bitcast i32 %zext to float
ret float %cast.zext ret float %cast.zext
} }
define amdgpu_ps i32 @s_andn2_v2i16(<2 x i16> inreg %src0, <2 x i16> inreg %src1) { define amdgpu_ps i32 @s_andn2_v2i16(<2 x i16> inreg %src0, <2 x i16> inreg %src1) {
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llvm/test/CodeGen/AMDGPU/GlobalISel/orn2.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6 %s ; RUN: llc -global-isel -amdgpu-codegenprepare-widen-16-bit-ops=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX6 %s
; RUN: llc -global-isel -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s ; RUN: llc -global-isel -amdgpu-codegenprepare-widen-16-bit-ops=0 -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s
define amdgpu_ps i32 @s_orn2_i32(i32 inreg %src0, i32 inreg %src1) { define amdgpu_ps i32 @s_orn2_i32(i32 inreg %src0, i32 inreg %src1) {
; GCN-LABEL: s_orn2_i32: ; GCN-LABEL: s_orn2_i32:
; GCN: ; %bb.0: ; GCN: ; %bb.0:
; GCN-NEXT: s_orn2_b32 s0, s2, s3 ; GCN-NEXT: s_orn2_b32 s0, s2, s3
; GCN-NEXT: ; return to shader part epilog ; GCN-NEXT: ; return to shader part epilog
%not.src1 = xor i32 %src1, -1 %not.src1 = xor i32 %src1, -1
%or = or i32 %src0, %not.src1 %or = or i32 %src0, %not.src1
▲ Show 20 Lines • Show All 179 Lines • ▼ Show 20 Lines
; GCN-NEXT: s_orn2_b64 s[0:1], s[2:3], s[4:5] ; GCN-NEXT: s_orn2_b64 s[0:1], s[2:3], s[4:5]
; GCN-NEXT: ; return to shader part epilog ; GCN-NEXT: ; return to shader part epilog
%not.src1 = xor <2 x i32> %src1, <i32 -1, i32 -1> %not.src1 = xor <2 x i32> %src1, <i32 -1, i32 -1>
%or = or <2 x i32> %not.src1, %src0 %or = or <2 x i32> %not.src1, %src0
ret <2 x i32> %or ret <2 x i32> %or
} }
define amdgpu_ps i16 @s_orn2_i16(i16 inreg %src0, i16 inreg %src1) { define amdgpu_ps i16 @s_orn2_i16(i16 inreg %src0, i16 inreg %src1) {
; GFX6-LABEL: s_orn2_i16: ; GCN-LABEL: s_orn2_i16:
; GFX6: ; %bb.0: ; GCN: ; %bb.0:
; GFX6-NEXT: s_orn2_b32 s0, s2, s3 ; GCN-NEXT: s_orn2_b32 s0, s2, s3
; GFX6-NEXT: ; return to shader part epilog ; GCN-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_orn2_i16:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_mov_b32 s0, 0xffff
; GFX9-NEXT: s_and_b32 s1, s3, s0
; GFX9-NEXT: s_xor_b32 s1, s1, s0
; GFX9-NEXT: s_and_b32 s2, s2, s0
; GFX9-NEXT: s_and_b32 s0, s1, s0
; GFX9-NEXT: s_or_b32 s0, s2, s0
; GFX9-NEXT: ; return to shader part epilog
%not.src1 = xor i16 %src1, -1 %not.src1 = xor i16 %src1, -1
%or = or i16 %src0, %not.src1 %or = or i16 %src0, %not.src1
ret i16 %or ret i16 %or
} }
define amdgpu_ps i16 @s_orn2_i16_commute(i16 inreg %src0, i16 inreg %src1) { define amdgpu_ps i16 @s_orn2_i16_commute(i16 inreg %src0, i16 inreg %src1) {
; GFX6-LABEL: s_orn2_i16_commute: ; GCN-LABEL: s_orn2_i16_commute:
; GFX6: ; %bb.0: ; GCN: ; %bb.0:
; GFX6-NEXT: s_orn2_b32 s0, s2, s3 ; GCN-NEXT: s_orn2_b32 s0, s2, s3
; GFX6-NEXT: ; return to shader part epilog ; GCN-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_orn2_i16_commute:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_mov_b32 s0, 0xffff
; GFX9-NEXT: s_and_b32 s1, s3, s0
; GFX9-NEXT: s_xor_b32 s1, s1, s0
; GFX9-NEXT: s_and_b32 s1, s1, s0
; GFX9-NEXT: s_and_b32 s0, s2, s0
; GFX9-NEXT: s_or_b32 s0, s1, s0
; GFX9-NEXT: ; return to shader part epilog
%not.src1 = xor i16 %src1, -1 %not.src1 = xor i16 %src1, -1
%or = or i16 %not.src1, %src0 %or = or i16 %not.src1, %src0
ret i16 %or ret i16 %or
} }
define amdgpu_ps { i16, i16 } @s_orn2_i16_multi_use(i16 inreg %src0, i16 inreg %src1) { define amdgpu_ps { i16, i16 } @s_orn2_i16_multi_use(i16 inreg %src0, i16 inreg %src1) {
; GFX6-LABEL: s_orn2_i16_multi_use: ; GCN-LABEL: s_orn2_i16_multi_use:
; GFX6: ; %bb.0: ; GCN: ; %bb.0:
; GFX6-NEXT: s_xor_b32 s1, s3, -1 ; GCN-NEXT: s_xor_b32 s1, s3, -1
; GFX6-NEXT: s_orn2_b32 s0, s2, s3 ; GCN-NEXT: s_orn2_b32 s0, s2, s3
; GFX6-NEXT: ; return to shader part epilog ; GCN-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_orn2_i16_multi_use:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_mov_b32 s0, 0xffff
; GFX9-NEXT: s_and_b32 s1, s3, s0
; GFX9-NEXT: s_xor_b32 s1, s1, s0
; GFX9-NEXT: s_and_b32 s2, s2, s0
; GFX9-NEXT: s_and_b32 s0, s1, s0
; GFX9-NEXT: s_or_b32 s0, s2, s0
; GFX9-NEXT: ; return to shader part epilog
%not.src1 = xor i16 %src1, -1 %not.src1 = xor i16 %src1, -1
%or = or i16 %src0, %not.src1 %or = or i16 %src0, %not.src1
%insert.0 = insertvalue { i16, i16 } undef, i16 %or, 0 %insert.0 = insertvalue { i16, i16 } undef, i16 %or, 0
%insert.1 = insertvalue { i16, i16 } %insert.0, i16 %not.src1, 1 %insert.1 = insertvalue { i16, i16 } %insert.0, i16 %not.src1, 1
ret { i16, i16 } %insert.1 ret { i16, i16 } %insert.1
} }
define amdgpu_ps { i16, i16 } @s_orn2_i16_multi_foldable_use(i16 inreg %src0, i16 inreg %src1, i16 inreg %src2) { define amdgpu_ps { i16, i16 } @s_orn2_i16_multi_foldable_use(i16 inreg %src0, i16 inreg %src1, i16 inreg %src2) {
; GFX6-LABEL: s_orn2_i16_multi_foldable_use: ; GCN-LABEL: s_orn2_i16_multi_foldable_use:
; GFX6: ; %bb.0: ; GCN: ; %bb.0:
; GFX6-NEXT: s_orn2_b32 s0, s2, s4 ; GCN-NEXT: s_orn2_b32 s0, s2, s4
; GFX6-NEXT: s_orn2_b32 s1, s3, s4 ; GCN-NEXT: s_orn2_b32 s1, s3, s4
; GFX6-NEXT: ; return to shader part epilog ; GCN-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: s_orn2_i16_multi_foldable_use:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_mov_b32 s1, 0xffff
; GFX9-NEXT: s_and_b32 s0, s4, s1
; GFX9-NEXT: s_xor_b32 s0, s0, s1
; GFX9-NEXT: s_and_b32 s2, s2, s1
; GFX9-NEXT: s_and_b32 s4, s0, s1
; GFX9-NEXT: s_and_b32 s1, s3, s1
; GFX9-NEXT: s_or_b32 s0, s2, s4
; GFX9-NEXT: s_or_b32 s1, s1, s4
; GFX9-NEXT: ; return to shader part epilog
%not.src2 = xor i16 %src2, -1 %not.src2 = xor i16 %src2, -1
%or0 = or i16 %src0, %not.src2 %or0 = or i16 %src0, %not.src2
%or1 = or i16 %src1, %not.src2 %or1 = or i16 %src1, %not.src2
%insert.0 = insertvalue { i16, i16 } undef, i16 %or0, 0 %insert.0 = insertvalue { i16, i16 } undef, i16 %or0, 0
%insert.1 = insertvalue { i16, i16 } %insert.0, i16 %or1, 1 %insert.1 = insertvalue { i16, i16 } %insert.0, i16 %or1, 1
ret { i16, i16 } %insert.1 ret { i16, i16 } %insert.1
} }
Show All 19 Lines; GCN-NEXT: ; return to shader part epilog
%not.src1 = xor i16 %src1, -1 %not.src1 = xor i16 %src1, -1
%or = or i16 %src0, %not.src1 %or = or i16 %src0, %not.src1
%zext = zext i16 %or to i32 %zext = zext i16 %or to i32
%cast.zext = bitcast i32 %zext to float %cast.zext = bitcast i32 %zext to float
ret float %cast.zext ret float %cast.zext
} }
define amdgpu_ps float @v_orn2_i16_vs(i16 %src0, i16 inreg %src1) { define amdgpu_ps float @v_orn2_i16_vs(i16 %src0, i16 inreg %src1) {
; GFX6-LABEL: v_orn2_i16_vs: ; GCN-LABEL: v_orn2_i16_vs:
; GFX6: ; %bb.0: ; GCN: ; %bb.0:
; GFX6-NEXT: s_xor_b32 s0, s2, -1 ; GCN-NEXT: s_xor_b32 s0, s2, -1
; GFX6-NEXT: v_or_b32_e32 v0, s0, v0 ; GCN-NEXT: v_or_b32_e32 v0, s0, v0
; GFX6-NEXT: v_bfe_u32 v0, v0, 0, 16 ; GCN-NEXT: v_bfe_u32 v0, v0, 0, 16
; GFX6-NEXT: ; return to shader part epilog ; GCN-NEXT: ; return to shader part epilog
;
; GFX9-LABEL: v_orn2_i16_vs:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_mov_b32 s0, 0xffff
; GFX9-NEXT: s_and_b32 s1, s2, s0
; GFX9-NEXT: s_xor_b32 s0, s1, s0
; GFX9-NEXT: v_or_b32_e32 v0, s0, v0
; GFX9-NEXT: v_bfe_u32 v0, v0, 0, 16
; GFX9-NEXT: ; return to shader part epilog
%not.src1 = xor i16 %src1, -1 %not.src1 = xor i16 %src1, -1
%or = or i16 %src0, %not.src1 %or = or i16 %src0, %not.src1
%zext = zext i16 %or to i32 %zext = zext i16 %or to i32
%cast.zext = bitcast i32 %zext to float %cast.zext = bitcast i32 %zext to float
ret float %cast.zext ret float %cast.zext
} }
define amdgpu_ps i32 @s_orn2_v2i16(<2 x i16> inreg %src0, <2 x i16> inreg %src1) { define amdgpu_ps i32 @s_orn2_v2i16(<2 x i16> inreg %src0, <2 x i16> inreg %src1) {
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