[RISCV] Enable the use of the old mucounteren name

[mmxsrup]

Summary

RISC-V Privileged Specification 1.11 defines mcountinhibit, which has the same numeric CSR value as mucounteren from 1.09.1.
This patch enables the use of the old mucounteren name.

[jrtc27]

llvm/lib/Target/RISCV/RISCVSystemOperands.td

313–315

is the style used elsewhere in this file and the RISCVInstrInfo*.td files.

[jrtc27]

llvm/lib/Target/RISCV/RISCVSystemOperands.td

313–315

and please also add a blank line to separate it from the mhpmeventX definitions, as is done with mcycle(h)/minstret(h)

[jrtc27]

Patch looks good but please fix the title and description of this revision. It's not about adding AltName, it's about adding mountinhibit itself, and as part of that you're including support for the older name too.

[pzheng]

The mcountinhibit CSR has already been added in d36f2c6a6c4b. Looks like the patch needs to be rebased?

[mmxsrup]

I rebased.

[lenary]

LGTM with one minor change. Once we get the LGTM from @jrtc27 and @pzheng, then I'll commit this for you @mmxsrup!

llvm/lib/Target/RISCV/RISCVSystemOperands.td

313

[pzheng]

LGTM, thanks for rebasing the patch, @mmxsrup!

[lenary]

@pzheng please may you use the "Add Action…" dropdown to mark as approved?

[pzheng]

LGTM

[lenary]

@jrtc27 Do you have any remaining concerns?

[jrtc27]

Looks fine, other than please mention something about it being an alias in the commit subject when landing as currently it reads as if it's a new CSR (and I'd also personally change "This patch enables the use of mucounteren." to "This patch enables the use of the old mucounteren name." to make it completely clear, but if the subject is fixed then I don't think it's _necessary_).

llvm/lib/Target/RISCV/RISCVSystemOperands.td

 def: SysReg<"mhpmcounter29h", 0xB9D>;
 def: SysReg<"mhpmcounter30h", 0xB9E>;
 def: SysReg<"mhpmcounter31h", 0xB9F>;
 }
 
 //===--------------------------
 // Machine Counter Setup
 //===--------------------------
+let AltName = "mucounteren" in
 def : SysReg<"mcountinhibit", 0x320>;
+
 def : SysReg<"mhpmevent3", 0x323>;
 def : SysReg<"mhpmevent4", 0x324>;
 def : SysReg<"mhpmevent5", 0x325>;
 def : SysReg<"mhpmevent6", 0x326>;
 def : SysReg<"mhpmevent7", 0x327>;
 def : SysReg<"mhpmevent8", 0x328>;
 def : SysReg<"mhpmevent9", 0x329>;
 def : SysReg<"mhpmevent10", 0x32A>;

llvm/test/MC/RISCV/machine-csr-names.s

 # CHECK-INST: csrrs t2, mcountinhibit, zero
 # CHECK-ENC:  encoding: [0xf3,0x23,0x00,0x32]
 # CHECK-INST-ALIAS: csrr t2, mcountinhibit
 # name
 csrrs t1, mcountinhibit, zero
 # uimm12
 csrrs t2, 0x320, zero
 
+# mucounteren
+# name
+# CHECK-INST: csrrs t1, mcountinhibit, zero
+# CHECK-ENC:  encoding: [0x73,0x23,0x00,0x32]
+# CHECK-INST-ALIAS: csrr t1, mcountinhibit
+# uimm12
+# CHECK-INST: csrrs t2, mcountinhibit, zero
+# CHECK-ENC:  encoding: [0xf3,0x23,0x00,0x32]
+# CHECK-INST-ALIAS: csrr t2, mcountinhibit
+# name
+csrrs t1, mucounteren, zero
+# uimm12
+csrrs t2, 0x320, zero
+
 # mhpmevent3
 # name
 # CHECK-INST: csrrs t1, mhpmevent3, zero
 # CHECK-ENC:  encoding: [0x73,0x23,0x30,0x32]
 # CHECK-INST-ALIAS: csrr t1, mhpmevent3
 # uimm12
 # CHECK-INST: csrrs t2, mhpmevent3, zero
 # CHECK-ENC:  encoding: [0xf3,0x23,0x30,0x32]