[ARM][test] Add more tests of two-part immediates

[benshi001]

Summary

The ARM backend breaks some specific immediates to two parts
in binary operations. And this patch adds more tests
for that.

[benshi001]

This patch does two optimization:

1. mov Rx, 0x1ffff

before:

ldr
...
.long ...

after:

mov Rx, # 0x20000
sub Rx, Rx, 1

2. add Rx, Rx, # 0x1ffff

before

ldr
add
...
.long ...

after:

add Rx, # 0x20000
sub Rx, # 1

[benshi001]

The patch depends on https://reviews.llvm.org/D83928, it will show improvements based on it.

[benshi001]

ping

[samparker]

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

3300

NewUseOpc2 = NewUseOpc1, same for below.

3352

NewUseOpc2 = NewUseOpc1, same for below.

llvm/test/CodeGen/ARM/add-sub-imm.ll

2 ↗

(On Diff #284204)

We should have a test run for a Thumb2 target as well. It would also be a good idea for some edge-case negative tests to exercise isSOImmTwoPartValSub some more.

[benshi001]

I have added tests for thumb2, however current patch does not apply to thumb2.

I will submit another patch for thumb2 later, since smaller patches are easy to review.

[benshi001]

Also, two edge-case negative tests to exercise isSOImmTwoPartValSub are added.

[samparker]

Thanks for the test changes.

I have added tests for thumb2, however current patch does not apply to thumb2.

I'm a bit confused then why there are Thumb2 changes in FoldImmediate?

[benshi001]

In D84100#2209170, @samparker wrote:

Thanks for the test changes.

I have added tests for thumb2, however current patch does not apply to thumb2.

I'm a bit confused then why there are Thumb2 changes in FoldImmediate?

I do not think there are Thumb2 changes in FoldImmediate. You can see NewUseOpc1 and NewUseOpc2 are identical
for all thumb2 related code. Actually the original NewUseOpc is enough for thumb2. So I should change it back (only) for thumb2 in FoldImmediate?

[samparker]

If the logic isn't needed, then yes, I'd recommend removing. Currently I'm seeing logic added for Thumb2 opcodes so I would expect some changes and testing and if that isn't case, then I guess the changes aren't needed. Looks like the ORR and EOR paths also need to be tested?

[benshi001]

In D84100#2209387, @samparker wrote:

If the logic isn't needed, then yes, I'd recommend removing. Currently I'm seeing logic added for Thumb2 opcodes so I would expect some changes and testing and if that isn't case, then I guess the changes aren't needed. Looks like the ORR and EOR paths also need to be tested?

Sorry, I made a mistake, the changes to thumb are necessary, since

• BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(), get(NewUseOpc), + BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(), get(NewUseOpc1), NewReg) .addReg(Reg1, getKillRegState(isKill)) .addImm(SOImmValV1) .add(predOps(ARMCC::AL)) .add(condCodeOp());
• UseMI.setDesc(get(NewUseOpc)); + UseMI.setDesc(get(NewUseOpc2));

This piece of code is in the critical path, all cases will walk though it.

It is necessary to substitute NewUseOpc with NewUseOpc1 & NewUseOpc2.

I will upload a new patch later, with tests of orr and eor.

[benshi001]

In D84100#2209387, @samparker wrote:

If the logic isn't needed, then yes, I'd recommend removing. Currently I'm seeing logic added for Thumb2 opcodes so I would expect some changes and testing and if that isn't case, then I guess the changes aren't needed. Looks like the ORR and EOR paths also need to be tested?

Sorry, I made a mistake, the changes to thumb are necessary, since

\-  BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(), get(NewUseOpc),
\+  BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(), get(NewUseOpc1),
           NewReg)
       .addReg(Reg1, getKillRegState(isKill))
       .addImm(SOImmValV1)
       .add(predOps(ARMCC::AL))
       .add(condCodeOp());
\-  UseMI.setDesc(get(NewUseOpc));
\+  UseMI.setDesc(get(NewUseOpc2));

This piece of code is in the critical path, all cases will walk though it.

It is necessary to substitute NewUseOpc with NewUseOpc1 & NewUseOpc2.

I will upload a new patch later, with tests of orr and eor.

[benshi001]

In D84100#2209387, @samparker wrote:

If the logic isn't needed, then yes, I'd recommend removing. Currently I'm seeing logic added for Thumb2 opcodes so I would expect some changes and testing and if that isn't case, then I guess the changes aren't needed. Looks like the ORR and EOR paths also need to be tested?

Sorry, I made a mistake, the changes to thumb are necessary, since

BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(), get(NewUseOpc),
         NewReg)
     .addReg(Reg1, getKillRegState(isKill))
     .addImm(SOImmValV1)
     .add(predOps(ARMCC::AL))
     .add(condCodeOp());
UseMI.setDesc(get(NewUseOpc));

is changed to

BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(), get(NewUseOpc1),
       NewReg)
   .addReg(Reg1, getKillRegState(isKill))
   .addImm(SOImmValV1)
   .add(predOps(ARMCC::AL))
   .add(condCodeOp());
UseMI.setDesc(get(NewUseOpc2));

This piece of code is in the critical path, all cases will walk though it.

It is necessary to substitute NewUseOpc with NewUseOpc1 & NewUseOpc2.

I will upload a new patch later, with tests of orr and eor.

[benshi001]

In D84100#2209387, @samparker wrote:

If the logic isn't needed, then yes, I'd recommend removing. Currently I'm seeing logic added for Thumb2 opcodes so I would expect some changes and testing and if that isn't case, then I guess the changes aren't needed. Looks like the ORR and EOR paths also need to be tested?

I have uploaded a new patch with tests of eor and orr.

The changes for Thumb2 are unavoidable due to the piece of code in the critical path.

[benshi001]

I have uploaded a new patch, in which more tests for orr and eor are added.

My patch also affect (improve) eor and orr, which I did not realize.

Currently, 12 positive test cases and 2 negative test cases are introduced, which should cover all corners.

[samparker]

I think the fact that you're having to make some Thumb2 changes to get around how the code is organised, suggests that the code should be reorganised instead. I'd suggest:

• Pre-commit the two-part-imm.ll test.
• Split the arm and thumb paths in an NFC patch, refactoring common code.
• Then make your arm changes.

[benshi001]

In D84100#2212804, @samparker wrote:

I think the fact that you're having to make some Thumb2 changes to get around how the code is organised, suggests that the code should be reorganised instead. I'd suggest:

• Pre-commit the two-part-imm.ll test.
• Split the arm and thumb paths in an NFC patch, refactoring common code.
• Then make your arm changes.

Thanks. This patch now only contains the improved test case two-part-imm.ll. And I will
submit the split of the arm and thumb paths in another NFC patch.

Really appreciate your suggestion.

[benshi001]

More tests are added for testing future patches.

[samparker]

Thanks, but please feel free to commit tests without review.

llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp

if (UseMCID.hasOptionalDef()) {
     unsigned NumOps = UseMCID.getNumOperands();
     if (UseMI.getOperand(NumOps - 1).getReg() == ARM::CPSR)
       // If the instruction sets the flag, do not attempt this optimization
       // since it may change the semantics of the code.
       return false;
   }
 
   unsigned UseOpc = UseMI.getOpcode();
-  unsigned NewUseOpc = 0;
+  unsigned NewUseOpc1 = 0, NewUseOpc2 = 0;
   uint32_t ImmVal = (uint32_t)DefMI.getOperand(1).getImm();
   uint32_t SOImmValV1 = 0, SOImmValV2 = 0;
   bool Commute = false;
   switch (UseOpc) {
   default: return false;
   case ARM::SUBrr:
   case ARM::ADDrr:
   case ARM::ORRrr:
   case ARM::EORrr:
   case ARM::t2SUBrr:
   case ARM::t2ADDrr:
   case ARM::t2ORRrr:
   case ARM::t2EORrr: {
     Commute = UseMI.getOperand(2).getReg() != Reg;
     switch (UseOpc) {
     default: break;
     case ARM::ADDrr:
-    case ARM::SUBrr:
+    case ARM::SUBrr: {
       if (UseOpc == ARM::SUBrr && Commute)
         return false;
 
+      bool IsSub = false;
       // ADD/SUB are special because they're essentially the same operation, so
       // we can handle a larger range of immediates.
-      if (ARM_AM::isSOImmTwoPartVal(ImmVal))
-        NewUseOpc = UseOpc == ARM::ADDrr ? ARM::ADDri : ARM::SUBri;
-      else if (ARM_AM::isSOImmTwoPartVal(-ImmVal)) {
+      if (ARM_AM::isSOImmTwoPartVal(ImmVal)) {
+        NewUseOpc1 = UseOpc == ARM::ADDrr ? ARM::ADDri : ARM::SUBri;
+        NewUseOpc2 = UseOpc == ARM::ADDrr ? ARM::ADDri : ARM::SUBri;
+      } else if (ARM_AM::isSOImmTwoPartVal(-ImmVal)) {
         ImmVal = -ImmVal;
-        NewUseOpc = UseOpc == ARM::ADDrr ? ARM::SUBri : ARM::ADDri;
-      } else
+        NewUseOpc1 = UseOpc == ARM::ADDrr ? ARM::SUBri : ARM::ADDri;
+        NewUseOpc2 = UseOpc == ARM::ADDrr ? ARM::SUBri : ARM::ADDri;
+      } else if (ARM_AM::isSOImmTwoPartValSub(ImmVal, &SOImmValV2,
+                                              &SOImmValV1)) {
+        IsSub = true;
+        NewUseOpc1 = UseOpc == ARM::ADDrr ? ARM::ADDri : ARM::SUBri;
+        NewUseOpc2 = UseOpc == ARM::ADDrr ? ARM::SUBri : ARM::ADDri;
+      } else if (ARM_AM::isSOImmTwoPartValSub(-ImmVal, &SOImmValV2,
+                                              &SOImmValV1)) {
+        IsSub = true;
+        NewUseOpc1 = UseOpc == ARM::ADDrr ? ARM::SUBri : ARM::ADDri;
+        NewUseOpc2 = UseOpc == ARM::ADDrr ? ARM::ADDri : ARM::SUBri;
+      } else {
         return false;
+      }
+
+      if (!IsSub) {
         SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
         SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
+      }
       break;
+    }
     case ARM::ORRrr:
     case ARM::EORrr:
       if (!ARM_AM::isSOImmTwoPartVal(ImmVal))
         return false;
       SOImmValV1 = (uint32_t)ARM_AM::getSOImmTwoPartFirst(ImmVal);
       SOImmValV2 = (uint32_t)ARM_AM::getSOImmTwoPartSecond(ImmVal);
       switch (UseOpc) {
       default: break;
-      case ARM::ORRrr: NewUseOpc = ARM::ORRri; break;
-      case ARM::EORrr: NewUseOpc = ARM::EORri; break;
+      case ARM::ORRrr:
+         NewUseOpc1 = NewUseOpc2 = ARM::ORRri;
+         break;
+      case ARM::EORrr:
+         NewUseOpc1 = NewUseOpc2 = ARM::EORri;
+         break;
       }
       break;
     case ARM::t2ADDrr:
     case ARM::t2SUBrr: {
       if (UseOpc == ARM::t2SUBrr && Commute)
         return false;
 
       // ADD/SUB are special because they're essentially the same operation, so
       // we can handle a larger range of immediates.
       const bool ToSP = DefMI.getOperand(0).getReg() == ARM::SP;
       const unsigned t2ADD = ToSP ? ARM::t2ADDspImm : ARM::t2ADDri;
       const unsigned t2SUB = ToSP ? ARM::t2SUBspImm : ARM::t2SUBri;
-      if (ARM_AM::isT2SOImmTwoPartVal(ImmVal))
-        NewUseOpc = UseOpc == ARM::t2ADDrr ? t2ADD : t2SUB;
-      else if (ARM_AM::isT2SOImmTwoPartVal(-ImmVal)) {
+      if (ARM_AM::isT2SOImmTwoPartVal(ImmVal)) {
+        NewUseOpc1 = UseOpc == ARM::t2ADDrr ? t2ADD : t2SUB;
+        NewUseOpc2 = UseOpc == ARM::t2ADDrr ? t2ADD : t2SUB;
+      } else if (ARM_AM::isT2SOImmTwoPartVal(-ImmVal)) {
         ImmVal = -ImmVal;
-        NewUseOpc = UseOpc == ARM::t2ADDrr ? t2SUB : t2ADD;
+        NewUseOpc1 = UseOpc == ARM::t2ADDrr ? t2SUB : t2ADD;
+        NewUseOpc2 = UseOpc == ARM::t2ADDrr ? t2SUB : t2ADD;
       } else
         return false;
       SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
       SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
       break;
     }
     case ARM::t2ORRrr:
     case ARM::t2EORrr:
       if (!ARM_AM::isT2SOImmTwoPartVal(ImmVal))
         return false;
       SOImmValV1 = (uint32_t)ARM_AM::getT2SOImmTwoPartFirst(ImmVal);
       SOImmValV2 = (uint32_t)ARM_AM::getT2SOImmTwoPartSecond(ImmVal);
       switch (UseOpc) {
       default: break;
-      case ARM::t2ORRrr: NewUseOpc = ARM::t2ORRri; break;
-      case ARM::t2EORrr: NewUseOpc = ARM::t2EORri; break;
+      case ARM::t2ORRrr:
+        NewUseOpc1 = NewUseOpc2 = ARM::t2ORRri;
+        break;
+      case ARM::t2EORrr:
+        NewUseOpc1 = NewUseOpc2 = ARM::t2EORri;
+        break;
       }
       break;
     }
   }
   }
 
   unsigned OpIdx = Commute ? 2 : 1;
   Register Reg1 = UseMI.getOperand(OpIdx).getReg();
   bool isKill = UseMI.getOperand(OpIdx).isKill();
   const TargetRegisterClass *TRC = MRI->getRegClass(Reg);
   Register NewReg = MRI->createVirtualRegister(TRC);
-  BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(), get(NewUseOpc),
+  BuildMI(*UseMI.getParent(), UseMI, UseMI.getDebugLoc(), get(NewUseOpc1),
           NewReg)
       .addReg(Reg1, getKillRegState(isKill))
       .addImm(SOImmValV1)
       .add(predOps(ARMCC::AL))
       .add(condCodeOp());
-  UseMI.setDesc(get(NewUseOpc));
+  UseMI.setDesc(get(NewUseOpc2));
   UseMI.getOperand(1).setReg(NewReg);
   UseMI.getOperand(1).setIsKill();
   UseMI.getOperand(2).ChangeToImmediate(SOImmValV2);
   DefMI.eraseFromParent();
   // FIXME: t2ADDrr should be split, as different rulles apply when writing to SP.
   // Just as t2ADDri, that was split to [t2ADDri, t2ADDspImm].
   // Then the below code will not be needed, as the input/output register
   // classes will be rgpr or gprSP.
   // For now, we fix the UseMI operand explicitly here:
-  switch(NewUseOpc){
-    case ARM::t2ADDspImm:
-    case ARM::t2SUBspImm:
-    case ARM::t2ADDri:
-    case ARM::t2SUBri:
-      MRI->setRegClass(UseMI.getOperand(0).getReg(), TRC);
+  switch(NewUseOpc1) {
+    assert(NewUseOpc1 == NewUseOpc2);
   }
   return true;
 }
 
 static unsigned getNumMicroOpsSwiftLdSt(const InstrItineraryData *ItinData,
                                         const MachineInstr &MI) {
   switch (MI.getOpcode()) {
   default: {
if (Subtarget->isThumb()) {
     if (ARM_AM::getSOImmVal(Val) != -1) // MOV
       return ForCodesize ? 4 : 1;
     if (ARM_AM::getSOImmVal(~Val) != -1) // MVN
       return ForCodesize ? 4 : 1;
     if (Subtarget->hasV6T2Ops() && Val <= 0xffff) // MOVW
       return ForCodesize ? 4 : 1;
     if (ARM_AM::isSOImmTwoPartVal(Val)) // two instrs
       return ForCodesize ? 8 : 2;
+    if (ARM_AM::isSOImmTwoPartValSub(Val)) // two instrs
+      return ForCodesize ? 8 : 2;
   }
   if (Subtarget->useMovt()) // MOVW + MOVT
     return ForCodesize ? 8 : 2;
   return ForCodesize ? 8 : 3; // Literal pool load
 }
 
 bool llvm::HasLowerConstantMaterializationCost(unsigned Val1, unsigned Val2,
                                                const ARMSubtarget *Subtarget,

llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp

void ARMExpandPseudo::ExpandMOV32BitImm(MachineBasicBlock &MBB,
   MachineInstrBuilder LO16, HI16;
   LLVM_DEBUG(dbgs() << "Expanding: "; MI.dump());
 
   if (!STI->hasV6T2Ops() &&
       (Opcode == ARM::MOVi32imm || Opcode == ARM::MOVCCi32imm)) {
     // FIXME Windows CE supports older ARM CPUs
     assert(!STI->isTargetWindows() && "Windows on ARM requires ARMv7+");
 
+    assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!");
+    unsigned ImmVal = (unsigned)MO.getImm();
+    unsigned SOImmValV1 = 0, SOImmValV2 = 0;
+
+    if (ARM_AM::isSOImmTwoPartVal(ImmVal)) {
       // Expand into a movi + orr.
       LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
       HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::ORRri))
              .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
              .addReg(DstReg);
+      SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
+      SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
+    } else if (ARM_AM::isSOImmTwoPartValSub(ImmVal, &SOImmValV2, &SOImmValV1)) {
+      // Expand into a movi + subri.
+      LO16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::MOVi), DstReg);
+      HI16 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::SUBri))
+             .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead))
+             .addReg(DstReg);
+    } else {
+      llvm_unreachable("unknown immediate type");
+    }
 
-    assert (MO.isImm() && "MOVi32imm w/ non-immediate source operand!");
-    unsigned ImmVal = (unsigned)MO.getImm();
-    unsigned SOImmValV1 = ARM_AM::getSOImmTwoPartFirst(ImmVal);
-    unsigned SOImmValV2 = ARM_AM::getSOImmTwoPartSecond(ImmVal);
     unsigned MIFlags = MI.getFlags();
     LO16 = LO16.addImm(SOImmValV1);
     HI16 = HI16.addImm(SOImmValV2);
     LO16.cloneMemRefs(MI);
     HI16.cloneMemRefs(MI);
     LO16.setMIFlags(MIFlags);
     HI16.setMIFlags(MIFlags);
     LO16.addImm(Pred).addReg(PredReg).add(condCodeOp());

llvm/lib/Target/ARM/ARMInstrInfo.td

def mod_imm_neg : Operand<i32>, PatLeaf<(imm), [{
   }], imm_neg_XFORM> {
   let ParserMatchClass = ModImmNegAsmOperand;
 }
 
 /// arm_i32imm - True for +V6T2, or when isSOImmTwoParVal()
 def arm_i32imm : IntImmLeaf<i32, [{
   if (Subtarget->useMovt())
     return true;
-  return ARM_AM::isSOImmTwoPartVal(Imm.getZExtValue());
+  if (ARM_AM::isSOImmTwoPartVal(Imm.getZExtValue()))
+    return true;
+  return ARM_AM::isSOImmTwoPartValSub(Imm.getZExtValue());
 }]>;
 
 /// imm0_1 predicate - Immediate in the range [0,1].
 def Imm0_1AsmOperand: ImmAsmOperand<0,1> { let Name = "Imm0_1"; }
 def imm0_1 : Operand<i32> { let ParserMatchClass = Imm0_1AsmOperand; }
 
 /// imm0_3 predicate - Immediate in the range [0,3].
 def Imm0_3AsmOperand: ImmAsmOperand<0,3> { let Name = "Imm0_3"; }

llvm/lib/Target/ARM/MCTargetDesc/ARMAddressingModes.h

inline int getSOImmVal(unsigned Arg) {
     // If this cannot be handled with a single shifter_op, bail out.
     if (rotr32(~255U, RotAmt) & Arg)
       return -1;
 
     // Encode this correctly.
     return rotl32(Arg, RotAmt) | ((RotAmt>>1) << 8);
   }
 
+  /// isSOImmTwoPartValSub - Return true if the specified value V can be
+  /// obtained by two SOImmVal's subtraction: V = Y - X.
+  inline bool isSOImmTwoPartValSub(unsigned V, unsigned *PX = nullptr,
+                                   unsigned *PY = nullptr) {
+    // If this can be handled with a single shifter_op, bail out.
+    if ((rotr32(~255U, getSOImmValRotate(V)) & V) == 0)
+      return false;
+    // Check if V can be obtained by Y-X, both Y and X are SOImmVal.
+    // Suppose V in the form of
+    // {leading 00, upper effective bits, lower 8 effective bits, trailing 00}
+    // The first step is calculating the top bit position of the lower 8
+    // effective bits.
+    unsigned Bits = countTrailingZeros(V);
+    Bits += Bits & 1 ? 7 : 8;
+    // The second step is calculating X.
+    unsigned XMask = (1 << Bits) - 1;
+    unsigned X = (1 << Bits) - (V & XMask);
+    // The third step is calculating Y.
+    unsigned Y = V + X;
+    // Check if Y is SOImmVal.
+    if ((rotr32(~255U, getSOImmValRotate(Y)) & Y) != 0)
+      return false;
+    if (PX)
+      *PX = X;
+    if (PY)
+      *PY = Y;
+    return true;
+  }
+
   /// isSOImmTwoPartVal - Return true if the specified value can be obtained by
   /// or'ing together two SOImmVal's.
   inline bool isSOImmTwoPartVal(unsigned V) {
     // If this can be handled with a single shifter_op, bail out.
     V = rotr32(~255U, getSOImmValRotate(V)) & V;
     if (V == 0)
       return false;
 

llvm/test/CodeGen/ARM/sadd_sat.ll

 ;
 ; CHECK-ARMNODPS-LABEL: func16:
 ; CHECK-ARMNODPS:       @ %bb.0:
 ; CHECK-ARMNODPS-NEXT:    add r0, r0, r1
 ; CHECK-ARMNODPS-NEXT:    mov r1, #255
 ; CHECK-ARMNODPS-NEXT:    orr r1, r1, #32512
 ; CHECK-ARMNODPS-NEXT:    cmp r0, r1
 ; CHECK-ARMNODPS-NEXT:    movlt r1, r0
-; CHECK-ARMNODPS-NEXT:    ldr r0, .LCPI2_0
+; CHECK-ARMNODPS-NEXT:    mov r0, #0
+; CHECK-ARMNODPS-NEXT:    sub r0, r0, #32768
 ; CHECK-ARMNODPS-NEXT:    cmn r1, #32768
 ; CHECK-ARMNODPS-NEXT:    movgt r0, r1
 ; CHECK-ARMNODPS-NEXT:    bx lr
-; CHECK-ARMNODPS-NEXT:    .p2align 2
-; CHECK-ARMNODPS-NEXT:  @ %bb.1:
-; CHECK-ARMNODPS-NEXT:  .LCPI2_0:
-; CHECK-ARMNODPS-NEXT:    .long 4294934528 @ 0xffff8000
 ;
 ; CHECK-ARMBASEDSP-LABEL: func16:
 ; CHECK-ARMBASEDSP:       @ %bb.0:
 ; CHECK-ARMBASEDSP-NEXT:    lsl r0, r0, #16
 ; CHECK-ARMBASEDSP-NEXT:    lsl r1, r1, #16
 ; CHECK-ARMBASEDSP-NEXT:    qadd r0, r0, r1
 ; CHECK-ARMBASEDSP-NEXT:    asr r0, r0, #16
 ; CHECK-ARMBASEDSP-NEXT:    bx lr

llvm/test/CodeGen/ARM/ssub_sat.ll

 ;
 ; CHECK-ARMNODPS-LABEL: func16:
 ; CHECK-ARMNODPS:       @ %bb.0:
 ; CHECK-ARMNODPS-NEXT:    sub r0, r0, r1
 ; CHECK-ARMNODPS-NEXT:    mov r1, #255
 ; CHECK-ARMNODPS-NEXT:    orr r1, r1, #32512
 ; CHECK-ARMNODPS-NEXT:    cmp r0, r1
 ; CHECK-ARMNODPS-NEXT:    movlt r1, r0
-; CHECK-ARMNODPS-NEXT:    ldr r0, .LCPI2_0
+; CHECK-ARMNODPS-NEXT:    mov r0, #0
+; CHECK-ARMNODPS-NEXT:    sub r0, r0, #32768
 ; CHECK-ARMNODPS-NEXT:    cmn r1, #32768
 ; CHECK-ARMNODPS-NEXT:    movgt r0, r1
 ; CHECK-ARMNODPS-NEXT:    bx lr
-; CHECK-ARMNODPS-NEXT:    .p2align 2
-; CHECK-ARMNODPS-NEXT:  @ %bb.1:
-; CHECK-ARMNODPS-NEXT:  .LCPI2_0:
-; CHECK-ARMNODPS-NEXT:    .long 4294934528 @ 0xffff8000
 ;
 ; CHECK-ARMBASEDSP-LABEL: func16:
 ; CHECK-ARMBASEDSP:       @ %bb.0:
 ; CHECK-ARMBASEDSP-NEXT:    lsl r0, r0, #16
 ; CHECK-ARMBASEDSP-NEXT:    lsl r1, r1, #16
 ; CHECK-ARMBASEDSP-NEXT:    qsub r0, r0, r1
 ; CHECK-ARMBASEDSP-NEXT:    asr r0, r0, #16
 ; CHECK-ARMBASEDSP-NEXT:    bx lr