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[AArch64][SVE] Don't align the last SVE callee save.

Authored by sdesmalen on Jul 17 2020, 9:37 AM.



Instead of aligning the last callee-saved-register slot to the stack
alignment (16 bytes), just align the SVE callee-saved block. This also
simplifies the code that allocates space for the callee-saves.

This change is needed to make sure the offset to which the callee-saved
register is spilled, corresponds to the offset used for e.g. unwind call
frame instructions.

Diff Detail

Event Timeline

sdesmalen created this revision.Jul 17 2020, 9:37 AM
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paulwalker-arm added inline comments.Jul 23 2020, 6:33 AM

Since ZPRs are architecturally defined in multiplies of 16-bytes I don't see why anything needs fixing up.

At the same time I think PPRs are more problematic because they're defined in multiples of 2-bytes and thus we'd need a group of 8 to fulfil alignment.

efriedma added inline comments.Jul 23 2020, 3:36 PM

It seems weird to introduce a gap in the middle of the callee-saves; I mean, the CPU doesn't care where the gap is, but it seems less readable for people. I'd prefer to keep this as-is, and change whatever code is assuming the other layout.

sdesmalen updated this revision to Diff 280495.Jul 24 2020, 9:31 AM
sdesmalen retitled this revision from [AArch64][SVE] Fix alignment of last predicate callee save to [AArch64][SVE] Don't align the last SVE callee save..
sdesmalen edited the summary of this revision. (Show Details)
sdesmalen marked 2 inline comments as done.Jul 24 2020, 9:34 AM
This revision is now accepted and ready to land.Jul 24 2020, 3:22 PM