[PowerPC] Implement Vector Expand Mask builtins in LLVM/Clang

[amyk]

Summary

This patch implements the vec_expandm function prototypes in altivec.h in order to utilize
the vector expand with mask instructions introduced in Power10.

Depends on D82675.

[amyk]

I will need to update this patch to remove the instruction definition and MC tests.

[amyk]

Rebased the patch and removed MC tests.

[amyk]

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

589

I have no idea why this indentation is off, since it did not appear like that previously. In any case, I can address this during the commit if it is OK.

[NeHuang]

Overall LGTM. I only have some comments on the nits.

clang/test/CodeGen/builtins-ppc-p10vector.c

94

nit: can we change the naming convention to be consistent as above? (e.g. "test_vec_expandm_uc")

I do not have a strong preference for either way since we did have different naming conventions in builtins-ppc-p10vector.c and p10-vector-mask-ops.ll for the vector extract cases.

100

ditto

106

ditto

112

ditto

118

ditto

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

589

This seems does not cause any clang-format check error during phabricator pre-merge check. I tried downloading this patch and found the indentation is as expected. It seems like a display issue from phabricator.

[amyk]

Update clang test names for vec_expandm.

[Conanap]

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

589

Nit: Please make this indentation inline with the others

[Conanap]

Minor nit, okay if changed for commit

[hubert.reinterpretcast]

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

588–609

The commit added "physical" tab characters instead of spaces here.

clang/include/clang/Basic/BuiltinsPPC.def

 
 // P10 Vector Extract with Mask built-ins.
 BUILTIN(__builtin_altivec_vextractbm, "UiV16Uc", "")
 BUILTIN(__builtin_altivec_vextracthm, "UiV8Us", "")
 BUILTIN(__builtin_altivec_vextractwm, "UiV4Ui", "")
 BUILTIN(__builtin_altivec_vextractdm, "UiV2ULLi", "")
 BUILTIN(__builtin_altivec_vextractqm, "UiV1ULLLi", "")
 
+// P10 Vector Expand with Mask built-ins.
+BUILTIN(__builtin_altivec_vexpandbm, "V16UcV16Uc", "")
+BUILTIN(__builtin_altivec_vexpandhm, "V8UsV8Us", "")
+BUILTIN(__builtin_altivec_vexpandwm, "V4UiV4Ui", "")
+BUILTIN(__builtin_altivec_vexpanddm, "V2ULLiV2ULLi", "")
+BUILTIN(__builtin_altivec_vexpandqm, "V1ULLLiV1ULLLi", "")
+
 // P10 Vector Parallel Bits built-ins.
 BUILTIN(__builtin_altivec_vpdepd, "V2ULLiV2ULLiV2ULLi", "")
 BUILTIN(__builtin_altivec_vpextd, "V2ULLiV2ULLiV2ULLi", "")
 
 // P10 Vector Centrifuge built-in.
 BUILTIN(__builtin_altivec_vcfuged, "V2ULLiV2ULLiV2ULLi", "")
 
 // P10 Vector Gather Every N-th Bit built-in.

clang/lib/Headers/altivec.h

 /*===---- altivec.h - Standard header for type generic math ---------------===*\
  *
  * Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
  * See https://llvm.org/LICENSE.txt for license information.
  * SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
  *
 \*===----------------------------------------------------------------------===*/
 
 #ifndef __ALTIVEC_H
 #define __ALTIVEC_H
 
 #ifndef __ALTIVEC__
 #error "AltiVec support not enabled"
 #endif
 
 /* Constants for mapping CR6 bits to predicate result. */
 
 #define __CR6_EQ 0
 #define __CR6_EQ_REV 1
 #define __CR6_LT 2
 #define __CR6_LT_REV 3
#define __VEC_CLASS_FP_NOT_NORMAL (__VEC_CLASS_FP_NAN        | \
                                    __VEC_CLASS_FP_INFINITY)
 
 #define __ATTRS_o_ai __attribute__((__overloadable__, __always_inline__))
 
 #ifdef __POWER9_VECTOR__
 #include <stddef.h>
 #endif
 
 static __inline__ vector signed char __ATTRS_o_ai vec_perm(
     vector signed char __a, vector signed char __b, vector unsigned char __c);
 
 static __inline__ vector unsigned char __ATTRS_o_ai
 vec_perm(vector unsigned char __a, vector unsigned char __b,
          vector unsigned char __c);
 
 static __inline__ vector bool char __ATTRS_o_ai
 vec_perm(vector bool char __a, vector bool char __b, vector unsigned char __c);
 
 static __inline__ vector short __ATTRS_o_ai vec_perm(vector signed short __a,
                                                      vector signed short __b,
                                                      vector unsigned char __c);
 
 static __inline__ vector unsigned short __ATTRS_o_ai
 vec_perm(vector unsigned short __a, vector unsigned short __b,
          vector unsigned char __c);
 
 static __inline__ vector bool short __ATTRS_o_ai vec_perm(
     vector bool short __a, vector bool short __b, vector unsigned char __c);
 
 static __inline__ vector pixel __ATTRS_o_ai vec_perm(vector pixel __a,
                                                      vector pixel __b,
                                                      vector unsigned char __c);
vec_extractm(vector unsigned long long __a) {
   return __builtin_altivec_vextractdm(__a);
 }
 
 static __inline__ unsigned int __ATTRS_o_ai
 vec_extractm(vector unsigned __int128 __a) {
   return __builtin_altivec_vextractqm(__a);
 }
 
+/* vec_expandm */
+
+static __inline__ vector unsigned char __ATTRS_o_ai
+vec_expandm(vector unsigned char __a) {
+  return __builtin_altivec_vexpandbm(__a);
+}
+
+static __inline__ vector unsigned short __ATTRS_o_ai
+vec_expandm(vector unsigned short __a) {
+  return __builtin_altivec_vexpandhm(__a);
+}
+
+static __inline__ vector unsigned int __ATTRS_o_ai
+vec_expandm(vector unsigned int __a) {
+  return __builtin_altivec_vexpandwm(__a);
+}
+
+static __inline__ vector unsigned long long __ATTRS_o_ai
+vec_expandm(vector unsigned long long __a) {
+  return __builtin_altivec_vexpanddm(__a);
+}
+
+static __inline__ vector unsigned __int128 __ATTRS_o_ai
+vec_expandm(vector unsigned __int128 __a) {
+  return __builtin_altivec_vexpandqm(__a);
+}
+
 /* vec_pdep */
 
 static __inline__ vector unsigned long long __ATTRS_o_ai
 vec_pdep(vector unsigned long long __a, vector unsigned long long __b) {
   return __builtin_altivec_vpdepd(__a, __b);
 }
 
 /* vec_pext */

clang/test/CodeGen/builtins-ppc-p10vector.c

 }
 
 unsigned int test_vec_extractm_u128(void) {
   // CHECK: @llvm.ppc.altivec.vextractqm(<1 x i128>
   // CHECK-NEXT: ret i32
   return vec_extractm(vui128a);
 }
 
+vector unsigned char test_vexpandm_uc(void) {
+  // CHECK: @llvm.ppc.altivec.vexpandbm(<16 x i8>
+  // CHECK-NEXT: ret <16 x i8>
+  return vec_expandm(vuca);
+}
+
+vector unsigned short test_vexpandm_us(void) {
+  // CHECK: @llvm.ppc.altivec.vexpandhm(<8 x i16>
+  // CHECK-NEXT: ret <8 x i16>
+  return vec_expandm(vusa);
+}
+
+vector unsigned int test_vexpandm_ui(void) {
+  // CHECK: @llvm.ppc.altivec.vexpandwm(<4 x i32>
+  // CHECK-NEXT: ret <4 x i32>
+  return vec_expandm(vuia);
+}
+
+vector unsigned long long test_vexpandm_ull(void) {
+  // CHECK: @llvm.ppc.altivec.vexpanddm(<2 x i64>
+  // CHECK-NEXT: ret <2 x i64>
+  return vec_expandm(vulla);
+}
+
+vector unsigned __int128 test_vexpandm_u128(void) {
+  // CHECK: @llvm.ppc.altivec.vexpandqm(<1 x i128>
+  // CHECK-NEXT: ret <1 x i128>
+  return vec_expandm(vui128a);
+}
+
 vector unsigned long long test_vpdepd(void) {
   // CHECK: @llvm.ppc.altivec.vpdepd(<2 x i64>
   // CHECK-NEXT: ret <2 x i64>
   return vec_pdep(vulla, vullb);
 }
 
 vector unsigned long long test_vpextd(void) {
   // CHECK: @llvm.ppc.altivec.vpextd(<2 x i64>
   // CHECK-NEXT: ret <2 x i64>
   return vec_pext(vulla, vullb);
 }
 
 vector unsigned long long test_vcfuged(void) {
   // CHECK: @llvm.ppc.altivec.vcfuged(<2 x i64>
   // CHECK-NEXT: ret <2 x i64>
   return vec_cfuge(vulla, vullb);
 }
 
 unsigned long long test_vgnb_1(void) {
   // CHECK: @llvm.ppc.altivec.vgnb(<1 x i128> %{{.+}}, i32 2)
   // CHECK-NEXT: ret i64
   return vec_gnb(vui128a, 2);
 }
 
 unsigned long long test_vgnb_2(void) {
   // CHECK: @llvm.ppc.altivec.vgnb(<1 x i128> %{{.+}}, i32 7)
   // CHECK-NEXT: ret i64
   return vec_gnb(vui128a, 7);
 }
 
 unsigned long long test_vgnb_3(void) {
   // CHECK: @llvm.ppc.altivec.vgnb(<1 x i128> %{{.+}}, i32 5)
   // CHECK-NEXT: ret i64
   return vec_gnb(vui128a, 5);
 }
 
 vector unsigned char test_xxeval_uc(void) {
   // CHECK: @llvm.ppc.vsx.xxeval(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, <2 x i64> %{{.+}}, i32 0)
   // CHECK: ret <16 x i8>
   return vec_ternarylogic(vuca, vucb, vucc, 0);
 }
 
 vector unsigned short test_xxeval_us(void) {
   // CHECK: @llvm.ppc.vsx.xxeval(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, <2 x i64> %{{.+}}, i32 255)
   // CHECK: ret <8 x i16>
   return vec_ternarylogic(vusa, vusb, vusc, 255);
 }
 
 vector unsigned int test_xxeval_ui(void) {
   // CHECK: @llvm.ppc.vsx.xxeval(<2 x i64> %{{.+}}, <2 x i64> %{{.+}}, <2 x i64> %{{.+}}, i32 150)
   // CHECK: ret <4 x i32>

llvm/include/llvm/IR/IntrinsicsPowerPC.td

def int_ppc_altivec_vextracthm : GCCBuiltin<"__builtin_altivec_vextracthm">,
               Intrinsic<[llvm_i32_ty], [llvm_v8i16_ty], [IntrNoMem]>;
   def int_ppc_altivec_vextractwm : GCCBuiltin<"__builtin_altivec_vextractwm">,
               Intrinsic<[llvm_i32_ty], [llvm_v4i32_ty], [IntrNoMem]>;
   def int_ppc_altivec_vextractdm : GCCBuiltin<"__builtin_altivec_vextractdm">,
               Intrinsic<[llvm_i32_ty], [llvm_v2i64_ty], [IntrNoMem]>;
   def int_ppc_altivec_vextractqm : GCCBuiltin<"__builtin_altivec_vextractqm">,
               Intrinsic<[llvm_i32_ty], [llvm_v1i128_ty], [IntrNoMem]>;
 
+  // P10 Vector Expand with Mask
+  def int_ppc_altivec_vexpandbm : GCCBuiltin<"__builtin_altivec_vexpandbm">,
+              Intrinsic<[llvm_v16i8_ty], [llvm_v16i8_ty], [IntrNoMem]>;
+  def int_ppc_altivec_vexpandhm : GCCBuiltin<"__builtin_altivec_vexpandhm">,
+              Intrinsic<[llvm_v8i16_ty], [llvm_v8i16_ty], [IntrNoMem]>;
+  def int_ppc_altivec_vexpandwm : GCCBuiltin<"__builtin_altivec_vexpandwm">,
+              Intrinsic<[llvm_v4i32_ty], [llvm_v4i32_ty], [IntrNoMem]>;
+  def int_ppc_altivec_vexpanddm : GCCBuiltin<"__builtin_altivec_vexpanddm">,
+              Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty], [IntrNoMem]>;
+  def int_ppc_altivec_vexpandqm : GCCBuiltin<"__builtin_altivec_vexpandqm">,
+              Intrinsic<[llvm_v1i128_ty], [llvm_v1i128_ty], [IntrNoMem]>;
+
   // P10 Vector Parallel Bits Deposit/Extract Doubleword Builtins.
   def int_ppc_altivec_vpdepd : GCCBuiltin<"__builtin_altivec_vpdepd">,
               Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
                         [IntrNoMem]>;
   def int_ppc_altivec_vpextd : GCCBuiltin<"__builtin_altivec_vpextd">,
               Intrinsic<[llvm_v2i64_ty], [llvm_v2i64_ty, llvm_v2i64_ty],
                         [IntrNoMem]>;
 

llvm/lib/Target/PowerPC/PPCInstrPrefix.td

def VEXTRACTWM : VXForm_RD5_XO5_RS5<1602, 10, (outs gprc:$rD), (ins vrrc:$vB),
                                       (int_ppc_altivec_vextractwm v4i32:$vB))]>;
   def VEXTRACTDM : VXForm_RD5_XO5_RS5<1602, 11, (outs gprc:$rD), (ins vrrc:$vB),
                                       "vextractdm $rD, $vB", IIC_VecGeneral,
                                       [(set i32:$rD,
                                       (int_ppc_altivec_vextractdm v2i64:$vB))]>;
   def VEXTRACTQM : VXForm_RD5_XO5_RS5<1602, 12, (outs gprc:$rD), (ins vrrc:$vB),
                                       "vextractqm $rD, $vB", IIC_VecGeneral,
                                       [(set i32:$rD,
                                       (int_ppc_altivec_vextractqm v1i128:$vB))]>;
+  def VEXPANDBM : VXForm_RD5_XO5_RS5<1602, 0, (outs vrrc:$vD), (ins vrrc:$vB),
+                                     "vexpandbm $vD, $vB", IIC_VecGeneral,
+                                     [(set v16i8:$vD,
+                                     (int_ppc_altivec_vexpandbm v16i8:$vB))]>;
+  def VEXPANDHM : VXForm_RD5_XO5_RS5<1602, 1, (outs vrrc:$vD), (ins vrrc:$vB),
+                                     "vexpandhm $vD, $vB", IIC_VecGeneral,
+                                     [(set v8i16:$vD,
+                                     (int_ppc_altivec_vexpandhm v8i16:$vB))]>;
+  def VEXPANDWM : VXForm_RD5_XO5_RS5<1602, 2, (outs vrrc:$vD), (ins vrrc:$vB),
+                                     "vexpandwm $vD, $vB", IIC_VecGeneral,
+                                     [(set v4i32:$vD,
+                                     (int_ppc_altivec_vexpandwm v4i32:$vB))]>;
+  def VEXPANDDM : VXForm_RD5_XO5_RS5<1602, 3, (outs vrrc:$vD), (ins vrrc:$vB),
+                                     "vexpanddm $vD, $vB", IIC_VecGeneral,
+                                     [(set v2i64:$vD,
+                                     (int_ppc_altivec_vexpanddm v2i64:$vB))]>;
+  def VEXPANDQM : VXForm_RD5_XO5_RS5<1602, 4, (outs vrrc:$vD), (ins vrrc:$vB),
+                                     "vexpandqm $vD, $vB", IIC_VecGeneral,
+                                     [(set v1i128:$vD,
+                                     (int_ppc_altivec_vexpandqm v1i128:$vB))]>;
    def VPDEPD : VXForm_1<1485, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                          "vpdepd $vD, $vA, $vB", IIC_VecGeneral,
                          [(set v2i64:$vD,
                          (int_ppc_altivec_vpdepd v2i64:$vA, v2i64:$vB))]>;
    def VPEXTD : VXForm_1<1421, (outs vrrc:$vD), (ins vrrc:$vA, vrrc:$vB),
                          "vpextd $vD, $vA, $vB", IIC_VecGeneral,
                          [(set v2i64:$vD,
                          (int_ppc_altivec_vpextd v2i64:$vA, v2i64:$vB))]>;
    def PDEPD : XForm_6<31, 156, (outs g8rc:$rA), (ins g8rc:$rS, g8rc:$rB),

llvm/test/CodeGen/PowerPC/p10-vector-mask-ops.ll

entry:
   ret i32 %ext
 }
 
 declare i32 @llvm.ppc.altivec.vextractbm(<16 x i8>)
 declare i32 @llvm.ppc.altivec.vextracthm(<8 x i16>)
 declare i32 @llvm.ppc.altivec.vextractwm(<4 x i32>)
 declare i32 @llvm.ppc.altivec.vextractdm(<2 x i64>)
 declare i32 @llvm.ppc.altivec.vextractqm(<1 x i128>)
+
+define <16 x i8> @test_vexpandbm(<16 x i8> %a) {
+; CHECK-LABEL: test_vexpandbm:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vexpandbm v2, v2
+; CHECK-NEXT:    blr
+entry:
+  %exp = tail call <16 x i8> @llvm.ppc.altivec.vexpandbm(<16 x i8> %a)
+  ret <16 x i8> %exp
+}
+
+define <8 x i16> @test_vexpandhm(<8 x i16> %a) {
+; CHECK-LABEL: test_vexpandhm:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vexpandhm v2, v2
+; CHECK-NEXT:    blr
+entry:
+  %exp = tail call <8 x i16> @llvm.ppc.altivec.vexpandhm(<8 x i16> %a)
+  ret <8 x i16> %exp
+}
+
+define <4 x i32> @test_vexpandwm(<4 x i32> %a) {
+; CHECK-LABEL: test_vexpandwm:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vexpandwm v2, v2
+; CHECK-NEXT:    blr
+entry:
+  %exp = tail call <4 x i32> @llvm.ppc.altivec.vexpandwm(<4 x i32> %a)
+  ret <4 x i32> %exp
+}
+
+define <2 x i64> @test_vexpanddm(<2 x i64> %a) {
+; CHECK-LABEL: test_vexpanddm:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vexpanddm v2, v2
+; CHECK-NEXT:    blr
+entry:
+  %exp = tail call <2 x i64> @llvm.ppc.altivec.vexpanddm(<2 x i64> %a)
+  ret <2 x i64> %exp
+}
+
+define <1 x i128> @test_vexpandqm(<1 x i128> %a) {
+; CHECK-LABEL: test_vexpandqm:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    vexpandqm v2, v2
+; CHECK-NEXT:    blr
+entry:
+  %exp = tail call <1 x i128> @llvm.ppc.altivec.vexpandqm(<1 x i128> %a)
+  ret <1 x i128> %exp
+}
+
+declare <16 x i8> @llvm.ppc.altivec.vexpandbm(<16 x i8>)
+declare <8 x i16> @llvm.ppc.altivec.vexpandhm(<8 x i16>)
+declare <4 x i32> @llvm.ppc.altivec.vexpandwm(<4 x i32>)
+declare <2 x i64> @llvm.ppc.altivec.vexpanddm(<2 x i64>)
+declare <1 x i128> @llvm.ppc.altivec.vexpandqm(<1 x i128>)

llvm/test/MC/Disassembler/PowerPC/p10insts.txt

 0x10 0x2a 0x16 0x42
 
 # CHECK: vextractdm 1, 2
 0x10 0x2b 0x16 0x42
 
 # CHECK: vextractqm 1, 2
 0x10 0x2c 0x16 0x42
 
+# CHECK: vexpandbm 1, 2
+0x10 0x20 0x16 0x42
+
+# CHECK: vexpandhm 1, 2
+0x10 0x21 0x16 0x42
+
+# CHECK: vexpandwm 1, 2
+0x10 0x22 0x16 0x42
+
+# CHECK: vexpanddm 1, 2
+0x10 0x23 0x16 0x42
+
+# CHECK: vexpandqm 1, 2
+0x10 0x24 0x16 0x42
+
 # CHECK: vpdepd 1, 2, 0
 0x10 0x22 0x05 0xcd
 
 # CHECK: vpextd 1, 2, 0
 0x10 0x22 0x05 0x8d
 
 # CHECK: pdepd 1, 2, 4
 0x7c 0x41 0x21 0x38

llvm/test/MC/PowerPC/p10.s

 # CHECK-LE: vextractwm 1, 2                       # encoding: [0x42,0x16,0x2a,0x10]
             vextractwm 1, 2
 # CHECK-BE: vextractdm 1, 2                       # encoding: [0x10,0x2b,0x16,0x42]
 # CHECK-LE: vextractdm 1, 2                       # encoding: [0x42,0x16,0x2b,0x10]
             vextractdm 1, 2
 # CHECK-BE: vextractqm 1, 2                       # encoding: [0x10,0x2c,0x16,0x42]
 # CHECK-LE: vextractqm 1, 2                       # encoding: [0x42,0x16,0x2c,0x10]
             vextractqm 1, 2
+# CHECK-BE: vexpandbm 1, 2                        # encoding: [0x10,0x20,0x16,0x42]
+# CHECK-LE: vexpandbm 1, 2                        # encoding: [0x42,0x16,0x20,0x10]
+            vexpandbm 1, 2
+# CHECK-BE: vexpandhm 1, 2                        # encoding: [0x10,0x21,0x16,0x42]
+# CHECK-LE: vexpandhm 1, 2                        # encoding: [0x42,0x16,0x21,0x10]
+            vexpandhm 1, 2
+# CHECK-BE: vexpandwm 1, 2                        # encoding: [0x10,0x22,0x16,0x42]
+# CHECK-LE: vexpandwm 1, 2                        # encoding: [0x42,0x16,0x22,0x10]
+            vexpandwm 1, 2
+# CHECK-BE: vexpanddm 1, 2                        # encoding: [0x10,0x23,0x16,0x42]
+# CHECK-LE: vexpanddm 1, 2                        # encoding: [0x42,0x16,0x23,0x10]
+            vexpanddm 1, 2
+# CHECK-BE: vexpandqm 1, 2                        # encoding: [0x10,0x24,0x16,0x42]
+# CHECK-LE: vexpandqm 1, 2                        # encoding: [0x42,0x16,0x24,0x10]
+            vexpandqm 1, 2
 # CHECK-BE: vpdepd 1, 2, 0                        # encoding: [0x10,0x22,0x05,0xcd]
 # CHECK-LE: vpdepd 1, 2, 0                        # encoding: [0xcd,0x05,0x22,0x10]
             vpdepd 1, 2, 0
 # CHECK-BE: vpextd 1, 2, 0                        # encoding: [0x10,0x22,0x05,0x8d]
 # CHECK-LE: vpextd 1, 2, 0                        # encoding: [0x8d,0x05,0x22,0x10]
             vpextd 1, 2, 0
 # CHECK-BE: pdepd 1, 2, 4                         # encoding: [0x7c,0x41,0x21,0x38]
 # CHECK-LE: pdepd 1, 2, 4                         # encoding: [0x38,0x21,0x41,0x7c]